Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2007 AMD |
| 5 | * Written by Yinghai Lu <yinghailu@amd.com> for AMD. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 20 | */ |
| 21 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 22 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 23 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
| 24 | #endif |
| 25 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 26 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 27 | #include <string.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 28 | #include <device/pci_def.h> |
| 29 | #include <device/pci_ids.h> |
| 30 | #include <arch/io.h> |
| 31 | #include <device/pnp_def.h> |
| 32 | #include <arch/romcc_io.h> |
| 33 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 34 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 35 | #include <console/console.h> |
Patrick Georgi | 5692c57 | 2010-10-05 13:40:31 +0000 | [diff] [blame] | 36 | #include <usbdebug.h> |
Uwe Hermann | 6dc92f0 | 2010-11-21 11:36:03 +0000 | [diff] [blame] | 37 | #include <spd.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 38 | #include <cpu/amd/model_fxx_rev.h> |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 39 | #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" |
| 40 | #include "northbridge/amd/amdk8/raminit.h" |
| 41 | #include "cpu/amd/model_fxx/apic_timer.c" |
| 42 | #include "lib/delay.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 43 | #include "cpu/x86/lapic/boot_cpu.c" |
| 44 | #include "northbridge/amd/amdk8/reset_test.c" |
| 45 | #include "superio/ite/it8716f/it8716f_early_serial.c" |
| 46 | #include "superio/ite/it8716f/it8716f_early_init.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 47 | #include "cpu/x86/bist.h" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 48 | #include "northbridge/amd/amdk8/debug.c" |
Stefan Reinauer | 5d3dee8 | 2010-04-14 11:40:34 +0000 | [diff] [blame] | 49 | #include "cpu/x86/mtrr/earlymtrr.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 50 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 51 | #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 52 | |
| 53 | #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 54 | #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 55 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 56 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
| 57 | static void activate_spd_rom(const struct mem_controller *ctrl) { } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 58 | |
| 59 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 60 | { |
| 61 | return smbus_read_byte(device, address); |
| 62 | } |
| 63 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 64 | #define MCP55_MB_SETUP \ |
Torsten Duwe | e7537f1 | 2007-10-31 00:49:38 +0000 | [diff] [blame] | 65 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \ |
| 66 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \ |
| 67 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x68,/* GPIO40 PCI_GNT2 */ \ |
| 68 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x68,/* GPIO41 PCI_REQ2 */ \ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 69 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ |
| 70 | RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ |
| 71 | |
| 72 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" |
| 73 | #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 74 | #include "northbridge/amd/amdk8/amdk8_f.h" |
| 75 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
| 76 | #include "northbridge/amd/amdk8/coherent_ht.c" |
| 77 | #include "northbridge/amd/amdk8/raminit_f.c" |
| 78 | #include "lib/generic_sdram.c" |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 79 | #include "resourcemap.c" |
Stefan Reinauer | d55e26f | 2010-04-25 13:54:30 +0000 | [diff] [blame] | 80 | #include "cpu/amd/dualcore/dualcore.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 81 | #include "cpu/amd/car/post_cache_as_ram.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 82 | #include "cpu/amd/model_fxx/init_cpus.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 83 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 84 | #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" |
| 85 | #include "northbridge/amd/amdk8/early_ht.c" |
| 86 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 87 | static void sio_setup(void) |
| 88 | { |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 89 | uint32_t dword; |
| 90 | uint8_t byte; |
| 91 | |
| 92 | byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 93 | byte |= 0x20; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 94 | pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 95 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 96 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); |
| 97 | dword |= (1<<0); |
| 98 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 99 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 100 | dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); |
| 101 | dword |= (1<<16); |
| 102 | pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); |
| 103 | } |
| 104 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 105 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 106 | { |
| 107 | static const uint16_t spd_addr [] = { |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 108 | // Node 0 |
| 109 | DIMM0, DIMM2, 0, 0, |
| 110 | DIMM1, DIMM3, 0, 0, |
| 111 | // Node 1 |
| 112 | DIMM4, DIMM6, 0, 0, |
| 113 | DIMM5, DIMM7, 0, 0, |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 114 | }; |
| 115 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 116 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 117 | + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 118 | int needs_reset = 0; |
| 119 | unsigned bsp_apicid = 0; |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 120 | uint8_t tmp = 0; |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 121 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 122 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 123 | /* Nothing special needs to be done to find bus 0 */ |
| 124 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 125 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 126 | sio_setup(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 127 | mcp55_enable_rom(); |
| 128 | } |
| 129 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 130 | if (bist == 0) |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 131 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 132 | |
| 133 | pnp_enter_ext_func_mode(SERIAL_DEV); |
Carl-Daniel Hailfinger | e13abe5 | 2007-11-14 17:57:04 +0000 | [diff] [blame] | 134 | /* The following line will set CLKIN to 24 MHz, external */ |
| 135 | pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 136 | tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP); |
| 137 | /* Is serial flash enabled? Then enable writing to serial flash. */ |
| 138 | if (tmp & 0x0e) { |
| 139 | pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10); |
| 140 | pnp_set_logical_device(GPIO_DEV); |
| 141 | /* Set Serial Flash interface to 0x0820 */ |
| 142 | pnp_write_config(GPIO_DEV, 0x64, 0x08); |
| 143 | pnp_write_config(GPIO_DEV, 0x65, 0x20); |
Carl-Daniel Hailfinger | 34153ac | 2007-11-14 15:09:30 +0000 | [diff] [blame] | 144 | } |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 145 | it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 146 | pnp_exit_ext_func_mode(SERIAL_DEV); |
| 147 | |
| 148 | setup_mb_resource_map(); |
| 149 | |
| 150 | uart_init(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 151 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 152 | /* Halt if there was a built in self test failure */ |
| 153 | report_bist_failure(bist); |
| 154 | |
Stefan Reinauer | 7e00a44 | 2010-05-25 17:09:05 +0000 | [diff] [blame] | 155 | #if CONFIG_USBDEBUG |
Uwe Hermann | 7ac4c26 | 2010-09-27 18:03:18 +0000 | [diff] [blame] | 156 | mcp55_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT); |
Stefan Reinauer | 75a05dc | 2010-05-25 16:35:51 +0000 | [diff] [blame] | 157 | early_usbdebug_init(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 158 | #endif |
| 159 | console_init(); |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 160 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 161 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 162 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 163 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 164 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 165 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
| 166 | #endif |
| 167 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 168 | |
| 169 | wait_all_core0_started(); |
| 170 | #if CONFIG_LOGICAL_CPUS==1 |
| 171 | // It is said that we should start core1 after all core0 launched |
| 172 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| 173 | * So here need to make sure last core0 is started, esp for two way system, |
| 174 | * (there may be apic id conflicts in that case) |
| 175 | */ |
| 176 | start_other_cores(); |
| 177 | wait_all_other_cores_started(bsp_apicid); |
| 178 | #endif |
| 179 | |
| 180 | /* it will set up chains and store link pair for optimization later */ |
| 181 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 182 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 183 | #if CONFIG_SET_FIDVID |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 184 | { |
| 185 | msr_t msr; |
| 186 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 187 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 188 | } |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 189 | enable_fid_change(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 190 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 191 | init_fidvid_bsp(bsp_apicid); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 192 | // show final fid and vid |
| 193 | { |
| 194 | msr_t msr; |
| 195 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 196 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 197 | } |
| 198 | #endif |
| 199 | |
Stefan Reinauer | bcb8c97 | 2010-04-25 18:06:32 +0000 | [diff] [blame] | 200 | init_timer(); // Need to use TMICT to synconize FID/VID |
| 201 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 202 | needs_reset |= optimize_link_coherent_ht(); |
| 203 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 204 | needs_reset |= mcp55_early_setup_x(); |
| 205 | |
| 206 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 207 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 208 | print_info("ht reset -\n"); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 209 | soft_reset(); |
| 210 | } |
| 211 | allow_all_aps_stop(bsp_apicid); |
| 212 | |
| 213 | //It's the time to set ctrl in sysinfo now; |
| 214 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 215 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 216 | enable_smbus(); |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 217 | |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 218 | /* all ap stopped? */ |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 219 | |
| 220 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 221 | |
| 222 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | f55b58d | 2007-02-17 14:28:11 +0000 | [diff] [blame] | 223 | } |