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Felix Held4a8cd722020-04-18 22:26:39 +02001# SPDX-License-Identifier: GPL-2.0-only
Martin Roth5c354b92019-04-22 14:55:16 -06002
Martin Roth1f337622019-04-22 16:08:31 -06003config SOC_AMD_PICASSO
Martin Roth5c354b92019-04-22 14:55:16 -06004 bool
5 help
Martin Roth1f337622019-04-22 16:08:31 -06006 AMD Picasso support
Martin Roth5c354b92019-04-22 14:55:16 -06007
Martin Roth1f337622019-04-22 16:08:31 -06008if SOC_AMD_PICASSO
Martin Roth5c354b92019-04-22 14:55:16 -06009
10config CPU_SPECIFIC_OPTIONS
11 def_bool y
12 select ARCH_BOOTBLOCK_X86_32
Martin Rothc7acf162020-05-28 00:44:50 -060013 select ARCH_VERSTAGE_X86_32 if !VBOOT_STARTS_BEFORE_BOOTBLOCK
Martin Roth5c354b92019-04-22 14:55:16 -060014 select ARCH_ROMSTAGE_X86_32
15 select ARCH_RAMSTAGE_X86_32
Felix Held46673222020-04-04 02:37:04 +020016 select RESET_VECTOR_IN_RAM
Martin Roth5c354b92019-04-22 14:55:16 -060017 select X86_AMD_FIXED_MTRRS
Marshall Dawson34c30562019-07-16 15:18:00 -060018 select X86_AMD_INIT_SIPI
Martin Roth5c354b92019-04-22 14:55:16 -060019 select ACPI_AMD_HARDWARE_SLEEP_VALUES
Martin Roth5c354b92019-04-22 14:55:16 -060020 select DRIVERS_I2C_DESIGNWARE
Raul E Rangel0357ab72020-07-09 12:08:58 -060021 select DRIVERS_USB_PCI_XHCI
Martin Roth5c354b92019-04-22 14:55:16 -060022 select GENERIC_GPIO_LIB
Furquan Shaikh8e915092020-06-17 23:15:35 -070023 select IDT_IN_EVERY_STAGE
Martin Roth5c354b92019-04-22 14:55:16 -060024 select IOAPIC
Furquan Shaikh0eabe132020-04-28 21:57:07 -070025 select HAVE_EM100_SUPPORT
Martin Roth5c354b92019-04-22 14:55:16 -060026 select HAVE_USBDEBUG_OPTIONS
Marshall Dawson80d0b012019-06-19 12:29:23 -060027 select TSC_MONOTONIC_TIMER
Richard Spiegel65562cd652019-08-21 10:27:05 -070028 select SOC_AMD_COMMON_BLOCK_SPI
Martin Roth5c354b92019-04-22 14:55:16 -060029 select TSC_SYNC_LFENCE
Marshall Dawson80d0b012019-06-19 12:29:23 -060030 select UDELAY_TSC
Martin Roth5c354b92019-04-22 14:55:16 -060031 select SOC_AMD_COMMON
32 select SOC_AMD_COMMON_BLOCK
Furquan Shaikh702cf302020-05-09 18:30:51 -070033 select SOC_AMD_COMMON_BLOCK_HAS_ESPI
Martin Roth5c354b92019-04-22 14:55:16 -060034 select SOC_AMD_COMMON_BLOCK_IOMMU
35 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
36 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
37 select SOC_AMD_COMMON_BLOCK_ACPI
Furquan Shaikh9e1a49c2020-04-23 14:01:12 -070038 select SOC_AMD_COMMON_BLOCK_GRAPHICS
Martin Roth5c354b92019-04-22 14:55:16 -060039 select SOC_AMD_COMMON_BLOCK_LPC
40 select SOC_AMD_COMMON_BLOCK_PCI
41 select SOC_AMD_COMMON_BLOCK_HDA
42 select SOC_AMD_COMMON_BLOCK_SATA
Aaron Durbin3d2e18a2020-01-28 11:20:05 -070043 select SOC_AMD_COMMON_BLOCK_SMBUS
Marshall Dawson5a73fc32020-01-24 09:42:57 -070044 select SOC_AMD_COMMON_BLOCK_PSP_GEN2
Aaron Durbin1d0b99b2020-04-11 11:58:57 -060045 select PROVIDES_ROM_SHARING
Martin Roth5c354b92019-04-22 14:55:16 -060046 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
47 select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
Martin Roth5c354b92019-04-22 14:55:16 -060048 select PARALLEL_MP
49 select PARALLEL_MP_AP_WORK
50 select HAVE_SMI_HANDLER
Martin Roth5c354b92019-04-22 14:55:16 -060051 select SSE2
52 select RTC
Marshall Dawson00a22082020-01-20 23:05:31 -070053 select PLATFORM_USES_FSP2_0
Furquan Shaikhc3063c52020-05-28 11:58:20 -070054 select FSP_COMPRESS_FSP_M_LZMA
55 select FSP_COMPRESS_FSP_S_LZMA
Marshall Dawson00a22082020-01-20 23:05:31 -070056 select UDK_2017_BINDING
57 select HAVE_CF9_RESET
Zheng Bao6ba591b2020-06-09 09:47:06 +080058 select SUPPORT_CPU_UCODE_IN_CBFS
Kyösti Mälkkic3c55212020-06-17 10:34:26 +030059 select ACPI_NO_SMI_GNVS
Martin Roth5c354b92019-04-22 14:55:16 -060060
Furquan Shaikh3b032062020-06-10 11:52:49 -070061config MEMLAYOUT_LD_FILE
62 string
63 default "src/soc/amd/picasso/memlayout.ld"
64
Furquan Shaikhbc456502020-06-10 16:37:23 -070065config EARLY_RESERVED_DRAM_BASE
66 hex
67 default 0x2000000
68 help
69 This variable defines the base address of the DRAM which is reserved
70 for usage by coreboot in early stages (i.e. before ramstage is up).
71 This memory gets reserved in BIOS tables to ensure that the OS does
72 not use it, thus preventing corruption of OS memory in case of S3
73 resume.
74
75config EARLYRAM_BSP_STACK_SIZE
76 hex
77 default 0x1000
78
79config PSP_APOB_DRAM_ADDRESS
80 hex
81 default 0x2001000
82 help
83 Location in DRAM where the PSP will copy the AGESA PSP Output
84 Block.
85
86config PSP_SHAREDMEM_BASE
87 hex
88 default 0x2011000 if VBOOT
89 default 0x0
90 help
91 This variable defines the base address in DRAM memory where PSP copies
92 vboot workbuf to. This is used in linker script to have a static
93 allocation for the buffer as well as for adding relevant entries in
94 BIOS directory table for the PSP.
95
96config PSP_SHAREDMEM_SIZE
97 hex
98 default 0x8000 if VBOOT
99 default 0x0
100 help
101 Sets the maximum size for the PSP to pass the vboot workbuf and
102 any logs or timestamps back to coreboot. This will be copied
103 into main memory by the PSP and will be available when the x86 is
104 started. The workbuf's base depends on the address of the reset
105 vector.
106
Martin Roth5c354b92019-04-22 14:55:16 -0600107config PRERAM_CBMEM_CONSOLE_SIZE
108 hex
109 default 0x1600
110 help
111 Increase this value if preram cbmem console is getting truncated
112
Furquan Shaikhbc456502020-06-10 16:37:23 -0700113config BOOTBLOCK_ADDR
114 hex
115 default 0x2030000
116 help
117 Sets the address in DRAM where bootblock should be loaded.
118
119config C_ENV_BOOTBLOCK_SIZE
120 hex
121 default 0x10000
122 help
123 Sets the size of the bootblock stage that should be loaded in DRAM.
124 This variable controls the DRAM allocation size in linker script
125 for bootblock stage.
126
127config X86_RESET_VECTOR
128 hex
129 depends on ARCH_X86
130 default 0x203fff0
131 help
132 Sets the reset vector within bootblock where x86 starts execution.
133 Reset vector is supposed to live at offset -0x10 from end of
134 bootblock i.e. BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10.
135
136config ROMSTAGE_ADDR
137 hex
138 default 0x2040000
139 help
140 Sets the address in DRAM where romstage should be loaded.
141
142config ROMSTAGE_SIZE
143 hex
144 default 0x80000
145 help
146 Sets the size of DRAM allocation for romstage in linker script.
147
148config FSP_M_ADDR
149 hex
150 default 0x20C0000
151 help
152 Sets the address in DRAM where FSP-M should be loaded. cbfstool
153 performs relocation of FSP-M to this address.
154
155config FSP_M_SIZE
156 hex
157 default 0x80000
158 help
159 Sets the size of DRAM allocation for FSP-M in linker script.
160
161config VERSTAGE_ADDR
162 hex
163 depends on VBOOT_SEPARATE_VERSTAGE
164 default 0x2140000
165 help
166 Sets the address in DRAM where verstage should be loaded if running
167 as a separate stage on x86.
168
169config VERSTAGE_SIZE
170 hex
171 depends on VBOOT_SEPARATE_VERSTAGE
172 default 0x80000
173 help
174 Sets the size of DRAM allocation for verstage in linker script if
175 running as a separate stage on x86.
176
177config RAMBASE
178 hex
179 default 0x10000000
180
Martin Roth5c354b92019-04-22 14:55:16 -0600181config CPU_ADDR_BITS
182 int
183 default 48
184
Martin Roth5c354b92019-04-22 14:55:16 -0600185config MMCONF_BASE_ADDRESS
186 hex
187 default 0xF8000000
188
189config MMCONF_BUS_NUMBER
190 int
191 default 64
192
Raul E Rangel5f52c0e2020-05-13 13:22:48 -0600193config VERSTAGE_ADDR
194 hex
195 default 0x4000000
196
Martin Roth5c354b92019-04-22 14:55:16 -0600197config VGA_BIOS_ID
198 string
Martin Roth86ba0d72020-02-05 16:46:30 -0700199 default "1002,15d8,c1"
Martin Roth5c354b92019-04-22 14:55:16 -0600200 help
201 The default VGA BIOS PCI vendor/device ID should be set to the
Martin Roth86ba0d72020-02-05 16:46:30 -0700202 result of the map_oprom_vendev_rev() function in northbridge.c.
Martin Roth5c354b92019-04-22 14:55:16 -0600203
204config VGA_BIOS_FILE
205 string
Raul E Rangelf39dab12020-05-13 16:46:57 -0600206 default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
Martin Roth5c354b92019-04-22 14:55:16 -0600207
Martin Roth86ba0d72020-02-05 16:46:30 -0700208config VGA_BIOS_SECOND
209 def_bool y
210
211config VGA_BIOS_SECOND_ID
212 string
213 default "1002,15dd,c4"
214 help
215 Because Dali and Picasso need different video BIOSes, but have the
216 same vendor/device IDs, we need an alternate method to determine the
217 correct video BIOS. In map_oprom_vendev_rev(), we look at the cpuid
218 and decide which rom to load.
219
220 Even though the hardware has the same vendor/device IDs, the vBIOS
221 contains a *different* device ID, confusing the situation even more.
222
223config VGA_BIOS_SECOND_FILE
224 string
225 default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
226
227config CHECK_REV_IN_OPROM_NAME
228 bool
229 default y
230 help
231 Select this in the platform BIOS or chipset if the option rom has a
232 revision that needs to be checked when searching CBFS.
233
Martin Roth5c354b92019-04-22 14:55:16 -0600234config S3_VGA_ROM_RUN
235 bool
236 default n
237
238config HEAP_SIZE
239 hex
240 default 0xc0000
241
242config EHCI_BAR
243 hex
244 default 0xfef00000
245
Marshall Dawson39c64b02020-09-04 12:07:27 -0600246config PICASSO_FCH_IOAPIC_ID
247 hex
248 default 0x8
249 help
250 The Picasso APU has two IOAPICs, one in the FCH and one in the
251 northbridge. Set this value for the intended ID to assign to the
252 FCH IOAPIC. The value should be >= MAX_CPUS and different from
253 the GNB's IOAPIC_ID.
254
255config PICASSO_GNB_IOAPIC_ID
256 hex
257 default 0x9
258 help
259 The Picasso APU has two IOAPICs, one in the FCH and one in the
260 northbridge. Set this value for the intended ID to assign to the
261 GNB IOAPIC. The value should be >= MAX_CPUS and different from
262 the FCH's IOAPIC_ID.
263
Martin Roth5c354b92019-04-22 14:55:16 -0600264config SERIRQ_CONTINUOUS_MODE
265 bool
266 default n
267 help
268 Set this option to y for serial IRQ in continuous mode.
269 Otherwise it is in quiet mode.
270
Marshall Dawsonbc4c9032019-06-11 12:18:20 -0600271config PICASSO_ACPI_IO_BASE
Martin Roth5c354b92019-04-22 14:55:16 -0600272 hex
273 default 0x400
274 help
275 Base address for the ACPI registers.
Martin Roth5c354b92019-04-22 14:55:16 -0600276
Felix Held097e4492020-06-16 15:35:20 +0200277config PICASSO_CONSOLE_UART
278 bool "Use Picasso UART controller for console"
Martin Roth5c354b92019-04-22 14:55:16 -0600279 default n
280 select DRIVERS_UART_8250MEM
281 select DRIVERS_UART_8250MEM_32
282 select NO_UART_ON_SUPERIO
283 select UART_OVERRIDE_REFCLK
284 help
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600285 There are four memory-mapped UARTs controllers in Picasso at:
286 0: 0xfedc9000
287 1: 0xfedca000
288 2: 0xfedc3000
289 3: 0xfedcf000
290
Martin Roth87fafca2020-07-23 13:28:30 -0600291choice
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600292 prompt "UART Frequency"
Felix Held097e4492020-06-16 15:35:20 +0200293 depends on PICASSO_CONSOLE_UART
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600294 default PICASSO_UART_48MZ
295
296config PICASSO_UART_48MZ
297 bool "48 MHz clock"
298 help
299 Select this option for the most compatibility.
300
301config PICASSO_UART_1_8MZ
302 bool "1.8432 MHz clock"
303 help
304 Select this option if an old payload or Linux ttyS0 arguments
305 require it.
306
307endchoice
308
309config PICASSO_UART_LEGACY
310 bool "Decode legacy I/O range"
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600311 help
Rob Barnes28cb14b2020-01-30 10:54:28 -0700312 Assign I/O 3F8, 2F8, etc. to a Picasso UART. A UART accessed with I/O
313 does not allow all the features of MMIO. The MMIO decode is still
314 present when this option is used.
Martin Roth5c354b92019-04-22 14:55:16 -0600315
316config CONSOLE_UART_BASE_ADDRESS
Felix Held097e4492020-06-16 15:35:20 +0200317 depends on CONSOLE_SERIAL && PICASSO_CONSOLE_UART
Martin Roth5c354b92019-04-22 14:55:16 -0600318 hex
Marshall Dawsonc0b8d0d2019-06-20 10:29:29 -0600319 default 0xfedc9000 if UART_FOR_CONSOLE = 0
320 default 0xfedca000 if UART_FOR_CONSOLE = 1
321 default 0xfedc3000 if UART_FOR_CONSOLE = 2
322 default 0xfedcf000 if UART_FOR_CONSOLE = 3
Martin Roth5c354b92019-04-22 14:55:16 -0600323
324config SMM_TSEG_SIZE
325 hex
326 default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER
327 default 0x0
328
329config SMM_RESERVED_SIZE
330 hex
Marshall Dawson3e2fabf2020-06-12 10:28:04 -0600331 default 0x180000
Martin Roth5c354b92019-04-22 14:55:16 -0600332
333config SMM_MODULE_STACK_SIZE
334 hex
335 default 0x800
336
337config ACPI_CPU_STRING
338 string
Jason Gleneskf2a59a42020-08-10 00:58:37 -0700339 default "\\_SB.C%03d"
Martin Roth5c354b92019-04-22 14:55:16 -0600340
341config ACPI_BERT
342 bool "Build ACPI BERT Table"
343 default y
344 depends on HAVE_ACPI_TABLES
345 help
346 Report Machine Check errors identified in POST to the OS in an
Marshall Dawson03743b72020-06-18 10:23:48 -0600347 ACPI Boot Error Record Table.
Martin Roth5c354b92019-04-22 14:55:16 -0600348
Marshall Dawson901cb9c2020-01-21 14:53:45 -0700349config ACPI_BERT_SIZE
350 hex
Marshall Dawson03743b72020-06-18 10:23:48 -0600351 default 0x4000 if ACPI_BERT
352 default 0x0
Marshall Dawson901cb9c2020-01-21 14:53:45 -0700353 help
354 Specify the amount of DRAM reserved for gathering the data used to
355 generate the ACPI table.
356
Furquan Shaikh40a38882020-05-01 10:43:48 -0700357config CHROMEOS
358 select CHROMEOS_RAMOOPS_DYNAMIC
Rob Barnes5ac928d2020-07-07 16:16:12 -0600359 select ALWAYS_LOAD_OPROM
360 select ALWAYS_RUN_OPROM
Furquan Shaikh40a38882020-05-01 10:43:48 -0700361
Marshall Dawson62611412019-06-19 11:46:06 -0600362config RO_REGION_ONLY
363 string
364 depends on CHROMEOS
365 default "apu/amdfw"
Martin Roth5c354b92019-04-22 14:55:16 -0600366
Marshall Dawson62611412019-06-19 11:46:06 -0600367config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
368 int
Martin Roth4017de02019-12-16 23:21:05 -0700369 default 150
Marshall Dawson62611412019-06-19 11:46:06 -0600370
Marshall Dawson39a4ac12019-06-20 16:28:33 -0600371config PICASSO_LPC_IOMUX
372 bool
373 help
374 Picasso's LPC bus signals are MUXed with some of the EMMC signals.
375 Select this option if LPC signals are required.
376
Aaron Durbin1d0b99b2020-04-11 11:58:57 -0600377config DISABLE_SPI_FLASH_ROM_SHARING
378 def_bool n
379 help
380 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
381 which indicates a board level ROM transaction request. This
382 removes arbitration with board and assumes the chipset controls
383 the SPI flash bus entirely.
384
Marshall Dawson62611412019-06-19 11:46:06 -0600385config MAINBOARD_POWER_RESTORE
386 def_bool n
387 help
388 This option determines what state to go to once power is restored
389 after having been lost in S0. Select this option to automatically
390 return to S0. Otherwise the system will remain in S5 once power
391 is restored.
392
Marshall Dawson00a22082020-01-20 23:05:31 -0700393config FSP_TEMP_RAM_SIZE
394 hex
Marshall Dawson00a22082020-01-20 23:05:31 -0700395 default 0x40000
396 help
397 The amount of coreboot-allocated heap and stack usage by the FSP.
398
Marshall Dawson62611412019-06-19 11:46:06 -0600399menu "PSP Configuration Options"
Martin Roth5c354b92019-04-22 14:55:16 -0600400
Martin Roth5c354b92019-04-22 14:55:16 -0600401config AMDFW_OUTSIDE_CBFS
Furquan Shaikhd4ef9a42020-04-24 11:49:32 -0700402 bool
Martin Roth5c354b92019-04-22 14:55:16 -0600403 default n
404 help
405 The AMDFW (PSP) is typically locatable in cbfs. Select this
406 option to manually attach the generated amdfw.rom outside of
407 cbfs. The location is selected by the FWM position.
408
409config AMD_FWM_POSITION_INDEX
410 int "Firmware Directory Table location (0 to 5)"
411 range 0 5
412 default 0 if BOARD_ROMSIZE_KB_512
413 default 1 if BOARD_ROMSIZE_KB_1024
414 default 2 if BOARD_ROMSIZE_KB_2048
415 default 3 if BOARD_ROMSIZE_KB_4096
416 default 4 if BOARD_ROMSIZE_KB_8192
417 default 5 if BOARD_ROMSIZE_KB_16384
418 help
419 Typically this is calculated by the ROM size, but there may
420 be situations where you want to put the firmware directory
421 table in a different location.
422 0: 512 KB - 0xFFFA0000
423 1: 1 MB - 0xFFF20000
424 2: 2 MB - 0xFFE20000
425 3: 4 MB - 0xFFC20000
426 4: 8 MB - 0xFF820000
427 5: 16 MB - 0xFF020000
428
429comment "AMD Firmware Directory Table set to location for 512KB ROM"
430 depends on AMD_FWM_POSITION_INDEX = 0
431comment "AMD Firmware Directory Table set to location for 1MB ROM"
432 depends on AMD_FWM_POSITION_INDEX = 1
433comment "AMD Firmware Directory Table set to location for 2MB ROM"
434 depends on AMD_FWM_POSITION_INDEX = 2
435comment "AMD Firmware Directory Table set to location for 4MB ROM"
436 depends on AMD_FWM_POSITION_INDEX = 3
437comment "AMD Firmware Directory Table set to location for 8MB ROM"
438 depends on AMD_FWM_POSITION_INDEX = 4
439comment "AMD Firmware Directory Table set to location for 16MB ROM"
440 depends on AMD_FWM_POSITION_INDEX = 5
441
Marshall Dawson62611412019-06-19 11:46:06 -0600442config AMD_PUBKEY_FILE
Furquan Shaikhd4ef9a42020-04-24 11:49:32 -0700443 string
Raul E Rangelf39dab12020-05-13 16:46:57 -0600444 default "3rdparty/amd_blobs/picasso/PSP/AmdPubKeyRV.bin"
Martin Roth5c354b92019-04-22 14:55:16 -0600445
Zheng Bao6252b602020-09-11 17:06:19 +0800446config USE_PSPSECUREOS
Furquan Shaikhd4ef9a42020-04-24 11:49:32 -0700447 bool
Marshall Dawson62611412019-06-19 11:46:06 -0600448 default y
449 help
450 Include the PspSecureOs and PspTrustlet binaries in the PSP build.
451
452 If unsure, answer 'y'
453
454config PSP_LOAD_MP2_FW
Furquan Shaikhd4ef9a42020-04-24 11:49:32 -0700455 bool
Furquan Shaikh47cdf432020-04-23 18:01:34 -0700456 default n
Marshall Dawson62611412019-06-19 11:46:06 -0600457 help
458 Include the MP2 firmwares and configuration into the PSP build.
459
Furquan Shaikh47cdf432020-04-23 18:01:34 -0700460 If unsure, answer 'n'
Marshall Dawson62611412019-06-19 11:46:06 -0600461
462config PSP_LOAD_S0I3_FW
Furquan Shaikhd4ef9a42020-04-24 11:49:32 -0700463 bool
Furquan Shaikh30bc5b32020-04-23 18:02:53 -0700464 default n
Marshall Dawson62611412019-06-19 11:46:06 -0600465 help
466 Select this item to include the S0i3 file into the PSP build.
467
468config HAVE_PSP_WHITELIST_FILE
469 bool "Include a debug whitelist file in PSP build"
470 default n
471 help
472 Support secured unlock prior to reset using a whitelisted
473 number? This feature requires a signed whitelist image and
474 bootloader from AMD.
475
476 If unsure, answer 'n'
477
478config PSP_WHITELIST_FILE
Martin Roth49b09a02020-02-20 13:54:06 -0700479 string "Debug whitelist file path"
Marshall Dawson62611412019-06-19 11:46:06 -0600480 depends on HAVE_PSP_WHITELIST_FILE
Raul E Rangelf39dab12020-05-13 16:46:57 -0600481 default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin"
Marshall Dawson62611412019-06-19 11:46:06 -0600482
Martin Roth49b09a02020-02-20 13:54:06 -0700483config PSP_BOOTLOADER_FILE
484 string "Specify the PSP Bootloader file path"
485 default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_WL_RV.sbin" if HAVE_PSP_WHITELIST_FILE
486 default "3rdparty/amd_blobs/picasso/PSP/PspBootLoader_prod_RV.sbin"
487 help
488 Supply the name of the PSP bootloader file.
489
490 Note that this option may conflict with the whitelist file if a
491 different PSP bootloader binary is specified.
492
Martin Rothc7acf162020-05-28 00:44:50 -0600493config PSP_SHAREDMEM_SIZE
494 hex "Maximum size of shared memory area"
495 default 0x3000 if VBOOT
496 default 0x0
497 help
498 Sets the maximum size for the PSP to pass the vboot workbuf and
499 any logs or timestamps back to coreboot. This will be copied
500 into main memory by the PSP and will be available when the x86 is
501 started.
502
Furquan Shaikh577db022020-04-24 15:52:04 -0700503config PSP_UNLOCK_SECURE_DEBUG
504 bool "Unlock secure debug"
505 default n
506 help
507 Select this item to enable secure debug options in PSP.
508
Martin Rothde498332020-09-01 11:00:28 -0600509config PSP_VERSTAGE_FILE
510 string "Specify the PSP_verstage file path"
511 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
512 default "$(obj)/psp_verstage.bin"
513 help
514 Add psp_verstage file to the build & PSP Directory Table
515
Martin Rothfe87d762020-09-01 11:04:21 -0600516config PSP_VERSTAGE_SIGNING_TOKEN
517 string "Specify the PSP_verstage Signature Token file path"
518 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
519 default ""
520 help
521 Add psp_verstage signature token to the build & PSP Directory Table
522
Marshall Dawson62611412019-06-19 11:46:06 -0600523endmenu
Martin Roth5c354b92019-04-22 14:55:16 -0600524
Martin Rothc7acf162020-05-28 00:44:50 -0600525
526config VBOOT
527 select VBOOT_VBNV_CMOS
Martin Rothe7e6c4e2020-07-15 11:54:14 -0600528 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
Martin Rothc7acf162020-05-28 00:44:50 -0600529
530config VBOOT_STARTS_BEFORE_BOOTBLOCK
531 def_bool n
532 depends on VBOOT
533 select ARCH_VERSTAGE_ARMV7
534 help
535 Runs verstage on the PSP. Only available on
536 certain Chrome OS branded parts from AMD.
537
Martin Roth50cca762020-08-13 11:06:18 -0600538config CMOS_RECOVERY_BYTE
539 hex
540 default 0x51
541 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
542 help
543 If the workbuf is not passed from the PSP to coreboot, set the
544 recovery flag and reboot. The PSP will read this byte, mark the
545 recovery request in VBNV, and reset the system into recovery mode.
546
547 This is the byte before the default first byte used by VBNV
548 (0x26 + 0x0E - 1)
549
Martin Roth9aa8d112020-06-04 21:31:41 -0600550if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
551
552config RWA_REGION_ONLY
553 string
554 default "apu/amdfw_a"
555 help
556 Add a space-delimited list of filenames that should only be in the
557 RW-A section.
558
559config RWB_REGION_ONLY
560 string
561 default "apu/amdfw_b"
562 help
563 Add a space-delimited list of filenames that should only be in the
564 RW-B section.
565
566config PICASSO_FW_A_POSITION
567 hex
568 help
569 Location of the AMD firmware in the RW_A region
570
571config PICASSO_FW_B_POSITION
572 hex
573 help
574 Location of the AMD firmware in the RW_B region
575
576endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
577
Martin Roth1f337622019-04-22 16:08:31 -0600578endif # SOC_AMD_PICASSO