soc/amd/picasso: Assign IOAPIC IDs, GNB APIC base with FSP
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index ec5ff76..29ebc6d 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -243,6 +243,24 @@
hex
default 0xfef00000
+config PICASSO_FCH_IOAPIC_ID
+ hex
+ default 0x8
+ help
+ The Picasso APU has two IOAPICs, one in the FCH and one in the
+ northbridge. Set this value for the intended ID to assign to the
+ FCH IOAPIC. The value should be >= MAX_CPUS and different from
+ the GNB's IOAPIC_ID.
+
+config PICASSO_GNB_IOAPIC_ID
+ hex
+ default 0x9
+ help
+ The Picasso APU has two IOAPICs, one in the FCH and one in the
+ northbridge. Set this value for the intended ID to assign to the
+ GNB IOAPIC. The value should be >= MAX_CPUS and different from
+ the FCH's IOAPIC_ID.
+
config SERIRQ_CONTINUOUS_MODE
bool
default n