Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | config SOC_INTEL_SKYLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Skylake support |
| 5 | |
Rizwan Qureshi | 0700dca | 2017-02-09 15:57:45 +0530 | [diff] [blame] | 6 | config SOC_INTEL_KABYLAKE |
| 7 | bool |
| 8 | default n |
| 9 | select SOC_INTEL_SKYLAKE |
| 10 | help |
| 11 | Intel Kabylake support |
| 12 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 13 | if SOC_INTEL_SKYLAKE |
| 14 | |
| 15 | config CPU_SPECIFIC_OPTIONS |
| 16 | def_bool y |
Aaron Durbin | e0a4914 | 2016-07-13 23:20:51 -0500 | [diff] [blame] | 17 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 18 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 19 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 20 | select ARCH_ROMSTAGE_X86_32 |
| 21 | select ARCH_VERSTAGE_X86_32 |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 22 | select ACPI_NHLT |
Teo Boon Tiong | 673a4d0 | 2016-11-10 21:06:51 +0800 | [diff] [blame] | 23 | select BOOTBLOCK_CONSOLE |
Aaron Durbin | e4cc8cd | 2016-08-11 23:55:39 -0500 | [diff] [blame] | 24 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
Aaron Durbin | e8e118d | 2016-08-12 15:00:10 -0500 | [diff] [blame] | 25 | select BOOT_DEVICE_SUPPORTS_WRITES |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 26 | select CACHE_MRC_SETTINGS |
Alexandru Gagniuc | 27fea06 | 2015-08-29 20:00:24 -0700 | [diff] [blame] | 27 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 28 | select C_ENVIRONMENT_BOOTBLOCK |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 29 | select COLLECT_TIMESTAMPS |
Duncan Laurie | 135c2c4 | 2016-10-17 19:47:51 -0700 | [diff] [blame] | 30 | select COMMON_FADT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 31 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Aaron Durbin | ffdf901 | 2015-07-24 13:00:36 -0500 | [diff] [blame] | 32 | select GENERIC_GPIO_LIB |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 33 | select HAVE_HARD_RESET |
Aaron Durbin | 387084c | 2015-07-30 13:41:01 -0500 | [diff] [blame] | 34 | select HAVE_INTEL_FIRMWARE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 35 | select HAVE_MONOTONIC_TIMER |
| 36 | select HAVE_SMI_HANDLER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 37 | select IOAPIC |
Aaron Durbin | f5ff854 | 2016-05-05 10:38:03 -0500 | [diff] [blame] | 38 | select NO_FIXED_XIP_ROM_SIZE |
Duncan Laurie | 205ed2d | 2016-06-02 15:23:42 -0700 | [diff] [blame] | 39 | select MRC_SETTINGS_PROTECT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 40 | select PARALLEL_MP |
Furquan Shaikh | a585358 | 2017-05-06 12:40:15 -0700 | [diff] [blame] | 41 | select PARALLEL_MP_AP_WORK |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 42 | select PCIEXP_ASPM |
| 43 | select PCIEXP_COMMON_CLOCK |
| 44 | select PCIEXP_CLK_PM |
Aaron Durbin | 27d153c | 2015-07-13 13:50:34 -0500 | [diff] [blame] | 45 | select PCIEXP_L1_SUB_STATE |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 46 | select PCIEX_LENGTH_64MB |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 47 | select REG_SCRIPT |
| 48 | select RELOCATABLE_MODULES |
| 49 | select RELOCATABLE_RAMSTAGE |
Aaron Durbin | 16246ea | 2016-08-05 21:23:37 -0500 | [diff] [blame] | 50 | select RTC |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 51 | select SOC_INTEL_COMMON |
Duncan Laurie | a1c8b34d | 2015-09-08 16:12:44 -0700 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK |
Barnali Sarkar | 7146445 | 2017-03-31 18:11:49 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_FAST_SPI |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_GSPI |
Bora Guvendik | 43c3109 | 2017-04-11 16:05:23 -0700 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_ITSS |
Rizwan Qureshi | ae6a4b6 | 2017-04-26 21:06:35 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_I2C |
Aamir Bohra | 015c643 | 2017-04-06 11:15:18 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_LPSS |
Aamir Bohra | 5196642 | 2017-05-11 20:31:06 +0530 | [diff] [blame^] | 59 | select SOC_INTEL_COMMON_BLOCK_PCIE |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_PCR |
Subrata Banik | e0268d3 | 2017-03-09 13:56:17 +0530 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_RTC |
Subrata Banik | 93ebe49 | 2017-03-14 18:24:47 +0530 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_SA |
Aamir Bohra | 502131a | 2017-04-19 22:34:25 +0530 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_SMBUS |
Aamir Bohra | c1f260e | 2017-03-31 21:02:16 +0530 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_UART |
Subrata Banik | e074d62 | 2017-02-16 16:16:37 +0530 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_XHCI |
Aaron Durbin | c14a1a9 | 2016-06-28 15:41:07 -0500 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_NHLT |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_RESET |
Furquan Shaikh | d0c00052 | 2016-11-21 09:19:53 -0800 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_SPI_FLASH_PROTECT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 69 | select SMM_TSEG |
| 70 | select SMP |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 71 | select SSE2 |
| 72 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 73 | select TSC_CONSTANT_RATE |
| 74 | select TSC_SYNC_MFENCE |
| 75 | select UDELAY_TSC |
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 76 | select ACPI_NHLT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 77 | |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 78 | config MAINBOARD_USES_FSP2_0 |
| 79 | bool |
| 80 | default n |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 81 | |
| 82 | config USE_FSP2_0_DRIVER |
| 83 | bool "Build with FSP 2.0" |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 84 | depends on MAINBOARD_USES_FSP2_0 |
| 85 | default y if MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 86 | select PLATFORM_USES_FSP2_0 |
| 87 | select ADD_VBT_DATA_FILE |
| 88 | select SOC_INTEL_COMMON_GFX_OPREGION |
Aaron Durbin | 79f0741 | 2017-04-16 21:49:29 -0500 | [diff] [blame] | 89 | select POSTCAR_CONSOLE |
| 90 | select POSTCAR_STAGE |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 91 | |
| 92 | config USE_FSP1_1_DRIVER |
| 93 | bool "Build with FSP 1.1" |
Naresh G Solanki | fe517f6 | 2016-10-17 17:21:08 +0530 | [diff] [blame] | 94 | depends on !MAINBOARD_USES_FSP2_0 |
| 95 | default y if !MAINBOARD_USES_FSP2_0 |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 96 | select PLATFORM_USES_FSP1_1 |
| 97 | select GOP_SUPPORT |
| 98 | select DISPLAY_FSP_ENTRY_POINTS |
| 99 | |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 100 | config CHROMEOS |
| 101 | select CHROMEOS_RAMOOPS_DYNAMIC |
Julius Werner | 58c3938 | 2017-02-13 17:53:29 -0800 | [diff] [blame] | 102 | |
| 103 | config VBOOT |
| 104 | select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC |
| 105 | select VBOOT_SEPARATE_VERSTAGE |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 106 | select VBOOT_OPROM_MATTERS |
Furquan Shaikh | b8257df | 2016-07-22 09:20:56 -0700 | [diff] [blame] | 107 | select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT |
Aaron Durbin | a6914d2 | 2016-08-24 08:49:29 -0500 | [diff] [blame] | 108 | select VBOOT_STARTS_IN_BOOTBLOCK |
Furquan Shaikh | 2a12e2e | 2016-07-25 11:48:03 -0700 | [diff] [blame] | 109 | select VBOOT_VBNV_CMOS |
| 110 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
Furquan Shaikh | 610a33a | 2016-07-22 16:17:53 -0700 | [diff] [blame] | 111 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 112 | config BOOTBLOCK_RESETS |
| 113 | string |
| 114 | default "soc/intel/common/reset.c" |
| 115 | |
Martin Roth | 59ff340 | 2016-02-09 09:06:46 -0700 | [diff] [blame] | 116 | config CBFS_SIZE |
| 117 | hex |
| 118 | default 0x200000 |
| 119 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 120 | config CPU_ADDR_BITS |
| 121 | int |
| 122 | default 36 |
| 123 | |
| 124 | config DCACHE_RAM_BASE |
| 125 | hex "Base address of cache-as-RAM" |
| 126 | default 0xfef00000 |
| 127 | |
| 128 | config DCACHE_RAM_SIZE |
| 129 | hex "Length in bytes of cache-as-RAM" |
Rizwan Qureshi | 3ad6356 | 2016-08-14 15:48:33 +0530 | [diff] [blame] | 130 | default 0x40000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 131 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 132 | The size of the cache-as-ram region required during bootblock |
| 133 | and/or romstage. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 134 | |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 135 | config DCACHE_BSP_STACK_SIZE |
| 136 | hex |
| 137 | default 0x4000 |
| 138 | help |
| 139 | The amount of anticipated stack usage in CAR by bootblock and |
| 140 | other stages. |
| 141 | |
| 142 | config C_ENV_BOOTBLOCK_SIZE |
| 143 | hex |
Furquan Shaikh | 7038596 | 2016-08-24 10:28:30 -0700 | [diff] [blame] | 144 | default 0xC000 |
Subrata Banik | 68d5d8b | 2016-07-18 14:13:52 +0530 | [diff] [blame] | 145 | |
Subrata Banik | 086730b | 2015-12-02 11:42:04 +0530 | [diff] [blame] | 146 | config EXCLUDE_NATIVE_SD_INTERFACE |
| 147 | bool |
| 148 | default n |
| 149 | help |
| 150 | If you set this option to n, will not use native SD controller. |
| 151 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 152 | config HEAP_SIZE |
| 153 | hex |
| 154 | default 0x80000 |
| 155 | |
| 156 | config IED_REGION_SIZE |
| 157 | hex |
| 158 | default 0x400000 |
| 159 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 160 | config MONOTONIC_TIMER_MSR |
| 161 | def_bool y |
| 162 | select HAVE_MONOTONIC_TIMER |
| 163 | help |
| 164 | Provide a monotonic timer using the 24MHz MSR counter. |
| 165 | |
Subrata Banik | e7ceae7 | 2017-03-08 17:59:40 +0530 | [diff] [blame] | 166 | config PCR_BASE_ADDRESS |
| 167 | hex |
| 168 | default 0xfd000000 |
| 169 | help |
| 170 | This option allows you to select MMIO Base Address of sideband bus. |
| 171 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 172 | config PRE_GRAPHICS_DELAY |
| 173 | int "Graphics initialization delay in ms" |
| 174 | default 0 |
| 175 | help |
| 176 | On some systems, coreboot boots so fast that connected monitors |
| 177 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 178 | VBIOS. On those systems we need to wait for a bit before executing |
| 179 | the VBIOS. |
| 180 | |
| 181 | config SERIAL_CPU_INIT |
| 182 | bool |
| 183 | default n |
| 184 | |
| 185 | config SERIRQ_CONTINUOUS_MODE |
| 186 | bool |
pchandri | 1d77c72 | 2015-09-09 17:22:09 -0700 | [diff] [blame] | 187 | default n |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 188 | help |
| 189 | If you set this option to y, the serial IRQ machine will be |
| 190 | operated in continuous mode. |
| 191 | |
| 192 | config SMM_RESERVED_SIZE |
| 193 | hex |
| 194 | default 0x200000 |
| 195 | |
| 196 | config SMM_TSEG_SIZE |
| 197 | hex |
| 198 | default 0x800000 |
| 199 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 200 | config VGA_BIOS_ID |
| 201 | string |
| 202 | default "8086,0406" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 203 | |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 204 | config UART_DEBUG |
| 205 | bool "Enable UART debug port." |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 206 | default n |
Martin Roth | 1afcb23 | 2015-08-15 17:36:15 -0600 | [diff] [blame] | 207 | select CONSOLE_SERIAL |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 208 | select DRIVERS_UART |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 209 | select DRIVERS_UART_8250MEM_32 |
Furquan Shaikh | b168db7 | 2016-08-01 19:37:38 -0700 | [diff] [blame] | 210 | select NO_UART_ON_SUPERIO |
Aaron Durbin | e33a172 | 2015-07-30 16:52:56 -0500 | [diff] [blame] | 211 | |
Teo Boon Tiong | 2fc06c8 | 2016-09-15 11:11:45 +0800 | [diff] [blame] | 212 | config SKYLAKE_SOC_PCH_H |
| 213 | bool |
| 214 | default n |
| 215 | help |
| 216 | Choose this option if you have a PCH-H chipset. |
| 217 | |
Aaron Durbin | 3953e39 | 2015-09-03 00:41:29 -0500 | [diff] [blame] | 218 | config CHIPSET_BOOTBLOCK_INCLUDE |
| 219 | string |
| 220 | default "soc/intel/skylake/bootblock/timestamp.inc" |
| 221 | |
Aaron Durbin | ed8a723 | 2015-11-24 12:35:06 -0600 | [diff] [blame] | 222 | config NHLT_DMIC_2CH |
| 223 | bool |
| 224 | default n |
| 225 | help |
| 226 | Include DSP firmware settings for 2 channel DMIC array. |
| 227 | |
| 228 | config NHLT_DMIC_4CH |
| 229 | bool |
| 230 | default n |
| 231 | help |
| 232 | Include DSP firmware settings for 4 channel DMIC array. |
| 233 | |
| 234 | config NHLT_NAU88L25 |
| 235 | bool |
| 236 | default n |
| 237 | help |
| 238 | Include DSP firmware settings for nau88l25 headset codec. |
| 239 | |
| 240 | config NHLT_MAX98357 |
| 241 | bool |
| 242 | default n |
| 243 | help |
| 244 | Include DSP firmware settings for max98357 amplifier. |
| 245 | |
| 246 | config NHLT_SSM4567 |
| 247 | bool |
| 248 | default n |
| 249 | help |
| 250 | Include DSP firmware settings for ssm4567 smart amplifier. |
| 251 | |
Duncan Laurie | 4a75a66 | 2017-03-02 10:13:51 -0800 | [diff] [blame] | 252 | config NHLT_RT5514 |
| 253 | bool |
| 254 | default n |
| 255 | help |
| 256 | Include DSP firmware settings for rt5514 DSP. |
| 257 | |
Rizwan Qureshi | 17335fa | 2017-01-14 06:08:21 +0530 | [diff] [blame] | 258 | config NHLT_RT5663 |
| 259 | bool |
| 260 | default n |
| 261 | help |
| 262 | Include DSP firmware settings for rt5663 headset codec. |
| 263 | |
| 264 | config NHLT_MAX98927 |
| 265 | bool |
| 266 | default n |
| 267 | help |
| 268 | Include DSP firmware settings for max98927 amplifier. |
| 269 | |
Subrata Banik | 03e971c | 2017-03-07 14:02:23 +0530 | [diff] [blame] | 270 | choice |
| 271 | prompt "Cache-as-ram implementation" |
| 272 | default CAR_NEM_ENHANCED |
| 273 | help |
| 274 | This option allows you to select how cache-as-ram (CAR) is set up. |
| 275 | |
| 276 | config CAR_NEM_ENHANCED |
| 277 | bool "Enhanced Non-evict mode" |
| 278 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 279 | select INTEL_CAR_NEM_ENHANCED |
| 280 | help |
| 281 | A current limitation of NEM (Non-Evict mode) is that code and data sizes |
| 282 | are derived from the requirement to not write out any modified cache line. |
| 283 | With NEM, if there is no physical memory behind the cached area, |
| 284 | the modified data will be lost and NEM results will be inconsistent. |
| 285 | ENHANCED NEM guarantees that modified data is always |
| 286 | kept in cache while clean data is replaced. |
| 287 | |
| 288 | config USE_SKYLAKE_FSP_CAR |
| 289 | bool "Use FSP CAR" |
| 290 | select FSP_CAR |
| 291 | help |
| 292 | Use FSP APIs to initialize & tear Down the Cache-As-Ram. |
| 293 | |
| 294 | endchoice |
| 295 | |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 296 | config SKIP_FSP_CAR |
Martin Roth | b00ddec | 2016-01-31 10:39:47 -0700 | [diff] [blame] | 297 | bool "Skip cache as RAM setup in FSP" |
| 298 | default y |
| 299 | help |
| 300 | Skip Cache as RAM setup in FSP. |
Subrata Banik | fbdc719 | 2016-01-19 19:19:15 +0530 | [diff] [blame] | 301 | |
Aaron Durbin | e56191e | 2016-08-11 09:50:49 -0500 | [diff] [blame] | 302 | config SPI_FLASH_INCLUDE_ALL_DRIVERS |
| 303 | bool |
| 304 | default n |
| 305 | |
Rizwan Qureshi | d8bb69a | 2016-11-08 21:01:09 +0530 | [diff] [blame] | 306 | config MAX_ROOT_PORTS |
| 307 | int |
| 308 | default 24 if PLATFORM_USES_FSP2_0 |
| 309 | default 20 if PLATFORM_USES_FSP1_1 |
| 310 | |
Jenny TC | 2864f85 | 2017-02-09 16:01:59 +0530 | [diff] [blame] | 311 | config NO_FADT_8042 |
| 312 | bool |
| 313 | default n |
| 314 | help |
| 315 | Choose this option if you want to disable 8042 Keyboard |
| 316 | |
Furquan Shaikh | 340908a | 2017-04-04 11:47:19 -0700 | [diff] [blame] | 317 | config SOC_INTEL_COMMON_LPSS_CLOCK_MHZ |
| 318 | int |
| 319 | default 120 |
| 320 | |
Furquan Shaikh | 05a6f29 | 2017-03-31 14:02:47 -0700 | [diff] [blame] | 321 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 322 | int |
| 323 | default 2 |
| 324 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 325 | endif |