Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 1 | config SOC_INTEL_SKYLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Skylake support |
| 5 | |
| 6 | if SOC_INTEL_SKYLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 11 | select ARCH_RAMSTAGE_X86_32 |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 12 | select ARCH_ROMSTAGE_X86_32 |
| 13 | select ARCH_VERSTAGE_X86_32 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 14 | select ALWAYS_LOAD_OPROM |
| 15 | select BACKUP_DEFAULT_SMM_REGION |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 16 | select CACHE_MRC_SETTINGS |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 17 | select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM |
| 18 | select CACHE_ROM |
| 19 | select CAR_MIGRATION |
| 20 | select COLLECT_TIMESTAMPS |
| 21 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 22 | select CPU_MICROCODE_IN_CBFS |
| 23 | select HAS_PRECBMEM_TIMESTAMP_REGION |
| 24 | select HAVE_HARD_RESET |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 25 | select HAVE_MONOTONIC_TIMER |
| 26 | select HAVE_SMI_HANDLER |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 27 | select IOAPIC |
| 28 | select MMCONF_SUPPORT |
| 29 | select MMCONF_SUPPORT_DEFAULT |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 30 | select PARALLEL_MP |
| 31 | select PCIEXP_ASPM |
| 32 | select PCIEXP_COMMON_CLOCK |
| 33 | select PCIEXP_CLK_PM |
Aaron Durbin | 27d153c | 2015-07-13 13:50:34 -0500 | [diff] [blame^] | 34 | select PCIEXP_L1_SUB_STATE |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 35 | select PLATFORM_USES_FSP1_1 |
| 36 | select REG_SCRIPT |
| 37 | select RELOCATABLE_MODULES |
| 38 | select RELOCATABLE_RAMSTAGE |
| 39 | select SOC_INTEL_COMMON |
| 40 | select SOC_INTEL_COMMON_FSP_RAM_INIT |
| 41 | select SOC_INTEL_COMMON_FSP_ROMSTAGE |
| 42 | select SOC_INTEL_COMMON_RESET |
| 43 | select SOC_INTEL_COMMON_STACK |
| 44 | select SOC_INTEL_COMMON_STAGE_CACHE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 45 | select SMM_MODULES |
| 46 | select SMM_TSEG |
| 47 | select SMP |
| 48 | select SPI_FLASH |
| 49 | select SSE2 |
| 50 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 51 | select TSC_CONSTANT_RATE |
| 52 | select TSC_SYNC_MFENCE |
| 53 | select UDELAY_TSC |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 54 | select USE_GENERIC_FSP_CAR_INC |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 55 | |
| 56 | config BOOTBLOCK_CPU_INIT |
| 57 | string |
| 58 | default "soc/intel/skylake/bootblock/cpu.c" |
| 59 | |
| 60 | config BOOTBLOCK_NORTHBRIDGE_INIT |
| 61 | string |
| 62 | default "soc/intel/skylake/bootblock/systemagent.c" |
| 63 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 64 | config BOOTBLOCK_RESETS |
| 65 | string |
| 66 | default "soc/intel/common/reset.c" |
| 67 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 68 | config BOOTBLOCK_SOUTHBRIDGE_INIT |
| 69 | string |
| 70 | default "soc/intel/skylake/bootblock/pch.c" |
| 71 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 72 | config CBFS_SIZE |
| 73 | hex "Size of CBFS filesystem in ROM" |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 74 | default 0x200000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 75 | help |
| 76 | The firmware image has to store more than just coreboot, including: |
| 77 | - a firmware descriptor |
| 78 | - Intel Management Engine firmware |
| 79 | - MRC cache information |
| 80 | This option allows to limit the size of the CBFS portion in the |
| 81 | firmware image. |
| 82 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 83 | config CPU_ADDR_BITS |
| 84 | int |
| 85 | default 36 |
| 86 | |
| 87 | config DCACHE_RAM_BASE |
| 88 | hex "Base address of cache-as-RAM" |
| 89 | default 0xfef00000 |
| 90 | |
| 91 | config DCACHE_RAM_SIZE |
| 92 | hex "Length in bytes of cache-as-RAM" |
| 93 | default 0x4000 |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 94 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 95 | The size of the cache-as-ram region required during bootblock |
| 96 | and/or romstage. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 97 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 98 | config EXTRA_MICROCODE_INCLUDE_PATH |
| 99 | string "Include path for extra microcode patches." |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 100 | help |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 101 | The path to any extra microcode patches from other sources. |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 102 | |
| 103 | config HAVE_IFD_BIN |
| 104 | bool "Use Intel Firmware Descriptor from existing binary" |
| 105 | default n |
| 106 | |
| 107 | config BUILD_WITH_FAKE_IFD |
| 108 | bool "Build with a fake IFD" |
| 109 | default y if !HAVE_IFD_BIN |
| 110 | help |
| 111 | If you don't have an Intel Firmware Descriptor (ifd.bin) for your |
| 112 | board, you can select this option and coreboot will build without it. |
| 113 | Though, the resulting coreboot.rom will not contain all parts required |
| 114 | to get coreboot running on your board. You can however write only the |
| 115 | BIOS section to your board's flash ROM and keep the other sections |
| 116 | untouched. Unfortunately the current version of flashrom doesn't |
| 117 | support this yet. But there is a patch pending [1]. |
| 118 | |
| 119 | WARNING: Never write a complete coreboot.rom to your flash ROM if it |
| 120 | was built with a fake IFD. It just won't work. |
| 121 | |
| 122 | [1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html |
| 123 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 124 | config HAVE_ME_BIN |
| 125 | bool "Add Intel Management Engine firmware" |
| 126 | default y |
| 127 | help |
| 128 | The Intel processor in the selected system requires a special firmware |
| 129 | for an integrated controller called Management Engine (ME). The ME |
| 130 | firmware might be provided in coreboot's 3rdparty/blobs repository. If |
| 131 | not and if you don't have the firmware elsewhere, you can still |
| 132 | build coreboot without it. In this case however, you'll have to make |
| 133 | sure that you don't overwrite your ME firmware on your flash ROM. |
| 134 | |
| 135 | config HEAP_SIZE |
| 136 | hex |
| 137 | default 0x80000 |
| 138 | |
| 139 | config IED_REGION_SIZE |
| 140 | hex |
| 141 | default 0x400000 |
| 142 | |
| 143 | config IFD_BIN_PATH |
| 144 | string "Path to intel firmware descriptor" |
| 145 | depends on !BUILD_WITH_FAKE_IFD |
| 146 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin" |
| 147 | |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 148 | config IFD_BIOS_SECTION |
| 149 | depends on BUILD_WITH_FAKE_IFD |
| 150 | string |
| 151 | default "" |
| 152 | |
| 153 | config IFD_ME_SECTION |
| 154 | depends on BUILD_WITH_FAKE_IFD |
| 155 | string |
| 156 | default "" |
| 157 | |
| 158 | config IFD_PLATFORM_SECTION |
| 159 | depends on BUILD_WITH_FAKE_IFD |
| 160 | string |
| 161 | default "" |
| 162 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 163 | config INTEL_PCH_UART_CONSOLE |
| 164 | bool "Use Serial IO UART for console" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 165 | default n |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 166 | select HAVE_UART_MEMORY_MAPPED |
| 167 | select CONSOLE_SERIAL8250MEM |
| 168 | depends on !CONFIG_DRIVERS_OXFORD_OXPCIE |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 169 | |
Lee Leahy | 1d14b3e | 2015-05-12 18:23:27 -0700 | [diff] [blame] | 170 | config INTEL_PCH_UART_CONSOLE_NUMBER |
| 171 | hex "Serial IO UART number to use for console" |
| 172 | default "0x0" |
| 173 | depends on INTEL_PCH_UART_CONSOLE |
| 174 | |
| 175 | config ME_BIN_PATH |
| 176 | string "Path to management engine firmware" |
| 177 | depends on HAVE_ME_BIN |
| 178 | default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/me.bin" |
| 179 | |
| 180 | config MICROCODE_INCLUDE_PATH |
| 181 | string |
| 182 | default "src/soc/intel/skylake/microcode" |
| 183 | |
| 184 | config MMCONF_BASE_ADDRESS |
| 185 | hex "MMIO Base Address" |
| 186 | default 0xe0000000 |
| 187 | |
| 188 | config MONOTONIC_TIMER_MSR |
| 189 | def_bool y |
| 190 | select HAVE_MONOTONIC_TIMER |
| 191 | help |
| 192 | Provide a monotonic timer using the 24MHz MSR counter. |
| 193 | |
| 194 | config PRE_GRAPHICS_DELAY |
| 195 | int "Graphics initialization delay in ms" |
| 196 | default 0 |
| 197 | help |
| 198 | On some systems, coreboot boots so fast that connected monitors |
| 199 | (mostly TVs) won't be able to wake up fast enough to talk to the |
| 200 | VBIOS. On those systems we need to wait for a bit before executing |
| 201 | the VBIOS. |
| 202 | |
| 203 | config SERIAL_CPU_INIT |
| 204 | bool |
| 205 | default n |
| 206 | |
| 207 | config SERIRQ_CONTINUOUS_MODE |
| 208 | bool |
| 209 | default y |
| 210 | help |
| 211 | If you set this option to y, the serial IRQ machine will be |
| 212 | operated in continuous mode. |
| 213 | |
| 214 | config SMM_RESERVED_SIZE |
| 215 | hex |
| 216 | default 0x200000 |
| 217 | |
| 218 | config SMM_TSEG_SIZE |
| 219 | hex |
| 220 | default 0x800000 |
| 221 | |
| 222 | config TTYS0_BASE |
| 223 | hex |
| 224 | default 0xfe034000 |
| 225 | depends on INTEL_PCH_UART_CONSOLE |
| 226 | |
| 227 | config VGA_BIOS_ID |
| 228 | string |
| 229 | default "8086,0406" |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 230 | |
| 231 | endif |