soc/intel/common/block: Add cache as ram init and teardown code
Create sample model for common car init and teardown programming.
TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED
and CAR_NEM configs till post code 0x2a.
Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18381
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index a56d044..ebdcbe3 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -255,6 +255,32 @@
help
Include DSP firmware settings for max98927 amplifier.
+choice
+ prompt "Cache-as-ram implementation"
+ default CAR_NEM_ENHANCED
+ help
+ This option allows you to select how cache-as-ram (CAR) is set up.
+
+config CAR_NEM_ENHANCED
+ bool "Enhanced Non-evict mode"
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select INTEL_CAR_NEM_ENHANCED
+ help
+ A current limitation of NEM (Non-Evict mode) is that code and data sizes
+ are derived from the requirement to not write out any modified cache line.
+ With NEM, if there is no physical memory behind the cached area,
+ the modified data will be lost and NEM results will be inconsistent.
+ ENHANCED NEM guarantees that modified data is always
+ kept in cache while clean data is replaced.
+
+config USE_SKYLAKE_FSP_CAR
+ bool "Use FSP CAR"
+ select FSP_CAR
+ help
+ Use FSP APIs to initialize & tear Down the Cache-As-Ram.
+
+endchoice
+
config SKIP_FSP_CAR
bool "Skip cache as RAM setup in FSP"
default y