soc/intel/skylake: use postcar stage for fsp 2.0
Utilize the postcar stage for tearing down CAR and initializing
the MTRRs once ram is up. This flow is consistent with apollolake
and allows CAR_GLOBAL variables to be directly accessed and no
need for migrating CAR_GLOBAL variables as romstage doesn't
run with and without CAR being available.
Change-Id: I76de447710ae1d405886eb9420dc4064aa26eccc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19335
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 3024196..23801b0 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -81,6 +81,8 @@
select PLATFORM_USES_FSP2_0
select ADD_VBT_DATA_FILE
select SOC_INTEL_COMMON_GFX_OPREGION
+ select POSTCAR_CONSOLE
+ select POSTCAR_STAGE
config USE_FSP1_1_DRIVER
bool "Build with FSP 1.1"