Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 5 | #include <cpu/intel/microcode.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 6 | #include <device/device.h> |
| 7 | #include <device/pci.h> |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 9 | #include <fsp/api.h> |
| 10 | #include <fsp/ppi/mp_service_ppi.h> |
| 11 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 12 | #include <option.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 13 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 14 | #include <intelblocks/lpss.h> |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 15 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 16 | #include <intelblocks/xdci.h> |
| 17 | #include <intelpch/lockdown.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 18 | #include <intelblocks/tcss.h> |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 19 | #include <soc/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 20 | #include <soc/gpio_soc_defs.h> |
| 21 | #include <soc/intel/common/vbt.h> |
| 22 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 23 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 24 | #include <soc/ramstage.h> |
| 25 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 26 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 27 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 28 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 29 | |
| 30 | /* THC assignment definition */ |
| 31 | #define THC_NONE 0 |
| 32 | #define THC_0 1 |
| 33 | #define THC_1 2 |
| 34 | |
| 35 | /* SATA DEVSLP idle timeout default values */ |
| 36 | #define DEF_DMVAL 15 |
| 37 | #define DEF_DITOVAL 625 |
| 38 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 39 | /* VccIn Aux Imon IccMax values in mA */ |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 40 | #define MILLIAMPS_TO_AMPS 1000 |
| 41 | #define ICC_MAX_TDP_45W 34250 |
| 42 | #define ICC_MAX_TDP_15W_28W 32000 |
| 43 | #define ICC_MAX_ID_ADL_M_MA 12000 |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 44 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 45 | /* |
| 46 | * ME End of Post configuration |
| 47 | * 0 - Disable EOP. |
| 48 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 49 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 50 | */ |
| 51 | enum fsp_end_of_post { |
| 52 | EOP_DISABLE = 0, |
| 53 | EOP_PEI = 1, |
| 54 | EOP_DXE = 2, |
| 55 | }; |
| 56 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 57 | static const struct slot_irq_constraints irq_constraints[] = { |
| 58 | { |
| 59 | .slot = SA_DEV_SLOT_IGD, |
| 60 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 61 | /* INTERRUPT_PIN is RO/0x01 */ |
| 62 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 63 | }, |
| 64 | }, |
| 65 | { |
| 66 | .slot = SA_DEV_SLOT_DPTF, |
| 67 | .fns = { |
| 68 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 69 | }, |
| 70 | }, |
| 71 | { |
| 72 | .slot = SA_DEV_SLOT_IPU, |
| 73 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 74 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 75 | but S0ix fails when not set to 16 (b/193434192) */ |
| 76 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 77 | }, |
| 78 | }, |
| 79 | { |
| 80 | .slot = SA_DEV_SLOT_CPU_6, |
| 81 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 82 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 83 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 84 | }, |
| 85 | }, |
| 86 | { |
| 87 | .slot = SA_DEV_SLOT_TBT, |
| 88 | .fns = { |
| 89 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 90 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 91 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 92 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 93 | }, |
| 94 | }, |
| 95 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 96 | .slot = SA_DEV_SLOT_GNA, |
| 97 | .fns = { |
| 98 | /* INTERRUPT_PIN is RO/0x01 */ |
| 99 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 100 | }, |
| 101 | }, |
| 102 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 103 | .slot = SA_DEV_SLOT_TCSS, |
| 104 | .fns = { |
| 105 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 106 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 107 | }, |
| 108 | }, |
| 109 | { |
| 110 | .slot = PCH_DEV_SLOT_SIO0, |
| 111 | .fns = { |
| 112 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 113 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 114 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 115 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 116 | }, |
| 117 | }, |
| 118 | { |
| 119 | .slot = PCH_DEV_SLOT_SIO6, |
| 120 | .fns = { |
| 121 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 122 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 123 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 124 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 125 | }, |
| 126 | }, |
| 127 | { |
| 128 | .slot = PCH_DEV_SLOT_ISH, |
| 129 | .fns = { |
| 130 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 131 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 132 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 133 | }, |
| 134 | }, |
| 135 | { |
| 136 | .slot = PCH_DEV_SLOT_SIO2, |
| 137 | .fns = { |
| 138 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 139 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 140 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 141 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 142 | }, |
| 143 | }, |
| 144 | { |
| 145 | .slot = PCH_DEV_SLOT_XHCI, |
| 146 | .fns = { |
| 147 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 148 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 149 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 150 | }, |
| 151 | }, |
| 152 | { |
| 153 | .slot = PCH_DEV_SLOT_SIO3, |
| 154 | .fns = { |
| 155 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 156 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 157 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 158 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 159 | }, |
| 160 | }, |
| 161 | { |
| 162 | .slot = PCH_DEV_SLOT_CSE, |
| 163 | .fns = { |
| 164 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 165 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 166 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 167 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 168 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 169 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 170 | }, |
| 171 | }, |
| 172 | { |
| 173 | .slot = PCH_DEV_SLOT_SATA, |
| 174 | .fns = { |
| 175 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 176 | }, |
| 177 | }, |
| 178 | { |
| 179 | .slot = PCH_DEV_SLOT_SIO4, |
| 180 | .fns = { |
| 181 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 182 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 183 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 184 | }, |
| 185 | }, |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 186 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 187 | { |
| 188 | .slot = PCH_DEV_SLOT_EMMC, |
| 189 | .fns = { |
| 190 | ANY_PIRQ(PCH_DEVFN_EMMC), |
| 191 | }, |
| 192 | }, |
| 193 | #endif |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 194 | { |
| 195 | .slot = PCH_DEV_SLOT_PCIE, |
| 196 | .fns = { |
| 197 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 198 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 199 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 200 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 201 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 202 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 203 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 204 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 205 | }, |
| 206 | }, |
| 207 | { |
| 208 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 209 | .fns = { |
| 210 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 211 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 212 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 213 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 214 | }, |
| 215 | }, |
| 216 | { |
| 217 | .slot = PCH_DEV_SLOT_SIO5, |
| 218 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 219 | /* UART0 shares an interrupt line with TSN0, so must use |
| 220 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 221 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 222 | /* UART1 shares an interrupt line with TSN1, so must use |
| 223 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 224 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 225 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 226 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 227 | }, |
| 228 | }, |
| 229 | { |
| 230 | .slot = PCH_DEV_SLOT_ESPI, |
| 231 | .fns = { |
| 232 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 233 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 234 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 235 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 236 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 237 | }, |
| 238 | }, |
| 239 | }; |
| 240 | |
| 241 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 242 | { |
| 243 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 244 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 245 | size_t pch_total = 0; |
| 246 | size_t cfg_count = 0; |
| 247 | |
| 248 | if (!entry) |
| 249 | return NULL; |
| 250 | |
| 251 | /* Count PCH devices */ |
| 252 | while (entry) { |
| 253 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 254 | ++pch_total; |
| 255 | entry = entry->next; |
| 256 | } |
| 257 | |
| 258 | /* Convert PCH device entries to FSP format */ |
| 259 | config = calloc(pch_total, sizeof(*config)); |
| 260 | entry = get_cached_pci_irqs(); |
| 261 | while (entry) { |
| 262 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 263 | entry = entry->next; |
| 264 | continue; |
| 265 | } |
| 266 | |
| 267 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 268 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 269 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 270 | config[cfg_count].Irq = entry->irq; |
| 271 | ++cfg_count; |
| 272 | |
| 273 | entry = entry->next; |
| 274 | } |
| 275 | |
| 276 | *out_count = cfg_count; |
| 277 | |
| 278 | return config; |
| 279 | } |
| 280 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 281 | /* |
| 282 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 283 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 284 | * In order to ensure that mainboard setting does not disable L1 substates |
| 285 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 286 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 287 | * value is set in fsp_params. |
| 288 | * 0: Use FSP UPD default |
| 289 | * 1: Disable L1 substates |
| 290 | * 2: Use L1.1 |
| 291 | * 3: Use L1.2 (FSP UPD default) |
| 292 | */ |
| 293 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 294 | { |
| 295 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 296 | ctl = L1_SS_L1_2; |
| 297 | return ctl - 1; |
| 298 | } |
| 299 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 300 | /* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */ |
| 301 | static uint16_t get_vccin_aux_imon_iccmax(void) |
| 302 | { |
| 303 | uint16_t mch_id = 0; |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 304 | uint8_t tdp; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 305 | |
| 306 | if (!mch_id) { |
| 307 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 308 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 309 | } |
| 310 | |
| 311 | switch (mch_id) { |
Curtis Chen | 0c54461 | 2021-11-19 11:38:12 +0800 | [diff] [blame] | 312 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_1: |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 313 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 314 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 315 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_6: |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 316 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: |
Curtis Chen | ea1bb5f | 2021-11-25 13:17:42 +0800 | [diff] [blame] | 317 | tdp = get_cpu_tdp(); |
| 318 | if (tdp == TDP_45W) |
| 319 | return ICC_MAX_TDP_45W; |
| 320 | return ICC_MAX_TDP_15W_28W; |
Bora Guvendik | 3160595 | 2021-09-01 17:32:07 -0700 | [diff] [blame] | 321 | case PCI_DEVICE_ID_INTEL_ADL_M_ID_1: |
| 322 | case PCI_DEVICE_ID_INTEL_ADL_M_ID_2: |
| 323 | return ICC_MAX_ID_ADL_M_MA; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 324 | default: |
| 325 | printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", |
| 326 | mch_id); |
| 327 | return 0; |
| 328 | } |
| 329 | } |
| 330 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 331 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 332 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 333 | /* Override settings per board. */ |
| 334 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 335 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 336 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 337 | const struct soc_intel_alderlake_config *config) |
| 338 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 339 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 340 | s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 341 | |
| 342 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 343 | s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 344 | s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 345 | s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 346 | } |
| 347 | |
| 348 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 349 | s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 350 | } |
| 351 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 352 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 353 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 354 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 355 | const struct microcode *microcode_file; |
| 356 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 357 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 358 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 359 | microcode_file = intel_microcode_find(); |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 360 | |
Selma Bensaid | 291294d | 2021-10-11 16:37:36 -0700 | [diff] [blame] | 361 | if (microcode_file != NULL) { |
| 362 | microcode_len = get_microcode_size(microcode_file); |
| 363 | if (microcode_len != 0) { |
| 364 | /* Update CPU Microcode patch base address/size */ |
| 365 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
| 366 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
| 367 | } |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 368 | } |
| 369 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 370 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 371 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 372 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 373 | } |
| 374 | |
| 375 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 376 | const struct soc_intel_alderlake_config *config) |
| 377 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 378 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 379 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 380 | |
| 381 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 382 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 383 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 384 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 385 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 386 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 387 | const struct soc_intel_alderlake_config *config) |
| 388 | { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 389 | const struct device *tcss_port_arr[] = { |
| 390 | DEV_PTR(tcss_usb3_port1), |
| 391 | DEV_PTR(tcss_usb3_port2), |
| 392 | DEV_PTR(tcss_usb3_port3), |
| 393 | DEV_PTR(tcss_usb3_port4), |
| 394 | }; |
| 395 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 396 | s_cfg->TcssAuxOri = config->TcssAuxOri; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 397 | |
| 398 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 399 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 400 | |
| 401 | /* |
| 402 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 403 | * evaluate this UPD value and skip sending command. There will be no |
| 404 | * delay for command completion. |
| 405 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 406 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 407 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 408 | /* D3Hot and D3Cold for TCSS */ |
| 409 | s_cfg->D3HotEnable = !config->TcssD3HotDisable; |
| 410 | s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 411 | |
| 412 | s_cfg->UsbTcPortEn = 0; |
| 413 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 414 | if (is_dev_enabled(tcss_port_arr[i])) |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 415 | s_cfg->UsbTcPortEn |= BIT(i); |
| 416 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 417 | } |
| 418 | |
| 419 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 420 | const struct soc_intel_alderlake_config *config) |
| 421 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 422 | /* Chipset Lockdown */ |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 423 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 424 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 425 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
Subrata Banik | 393b093 | 2022-01-11 11:59:39 +0530 | [diff] [blame] | 426 | s_cfg->PchUnlockGpioPads = lockdown_by_fsp; |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 427 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 091dfa1 | 2021-08-24 09:32:09 -0600 | [diff] [blame] | 428 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 429 | |
| 430 | /* coreboot will send EOP before loading payload */ |
| 431 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 432 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 433 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 434 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 435 | const struct soc_intel_alderlake_config *config) |
| 436 | { |
| 437 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 438 | /* USB */ |
| 439 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 440 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 441 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 442 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 443 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 444 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 445 | |
| 446 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 447 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 448 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 449 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Anil Kumar | c6b65c1 | 2022-02-01 12:59:03 -0800 | [diff] [blame] | 450 | |
| 451 | if (config->usb2_ports[i].type_c) |
| 452 | s_cfg->PortResetMessageEnable[i] = 1; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 453 | } |
| 454 | |
| 455 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 456 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 457 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 458 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 459 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 460 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 461 | |
| 462 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 463 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 464 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 465 | } |
| 466 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 467 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 468 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 469 | config->usb3_ports[i].tx_downscale_amp; |
| 470 | } |
| 471 | } |
| 472 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 473 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 474 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 475 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 476 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 477 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 478 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 479 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 480 | const struct soc_intel_alderlake_config *config) |
| 481 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 482 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 483 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 484 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 485 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 486 | const struct soc_intel_alderlake_config *config) |
| 487 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 488 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 489 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 490 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 491 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 492 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 493 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 494 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 495 | const struct soc_intel_alderlake_config *config) |
| 496 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 497 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 498 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 499 | if (s_cfg->SataEnable) { |
| 500 | s_cfg->SataMode = config->SataMode; |
| 501 | s_cfg->SataSalpSupport = config->SataSalpSupport; |
| 502 | memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, |
| 503 | sizeof(s_cfg->SataPortsEnable)); |
| 504 | memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, |
| 505 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 509 | * Power Optimizer for SATA. |
| 510 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 511 | * Boards not needing the optimizers explicitly disables them by setting |
| 512 | * these disable variables to 1 in devicetree overrides. |
| 513 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 514 | s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 515 | /* |
| 516 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 517 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 518 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 519 | * The default values can be changed from devicetree. |
| 520 | */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 521 | for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 522 | if (config->SataPortsEnableDitoConfig[i]) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 523 | s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 524 | s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 525 | } |
| 526 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 527 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 528 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 529 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 530 | const struct soc_intel_alderlake_config *config) |
| 531 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 532 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 533 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 534 | |
| 535 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 536 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 537 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 538 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 539 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 540 | const struct soc_intel_alderlake_config *config) |
| 541 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 542 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 543 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 544 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 545 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 546 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 547 | const struct soc_intel_alderlake_config *config) |
| 548 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 549 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 550 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 551 | s_cfg->CnviBtCore = config->CnviBtCore; |
| 552 | s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 553 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 554 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 555 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 556 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 557 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 558 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 559 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 560 | const struct soc_intel_alderlake_config *config) |
| 561 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 562 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 563 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 564 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 565 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 566 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 567 | const struct soc_intel_alderlake_config *config) |
| 568 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 569 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 570 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 571 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 572 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 573 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 574 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 575 | const struct soc_intel_alderlake_config *config) |
| 576 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 577 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 578 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 579 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 580 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 581 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 582 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 583 | const struct soc_intel_alderlake_config *config) |
| 584 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 585 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 586 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 587 | s_cfg->Enable8254ClockGating = !use_8254; |
| 588 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 589 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 590 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 591 | static void fill_fsps_pm_timer_params(FSP_S_CONFIG *s_cfg, |
| 592 | const struct soc_intel_alderlake_config *config) |
| 593 | { |
| 594 | /* |
| 595 | * Legacy PM ACPI Timer (and TCO Timer) |
| 596 | * This *must* be 1 in any case to keep FSP from |
| 597 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 598 | * 2) disabling the PM ACPI Timer. |
| 599 | * We handle both by ourself! |
| 600 | */ |
| 601 | s_cfg->EnableTcoTimer = 1; |
| 602 | } |
| 603 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 604 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 605 | const struct soc_intel_alderlake_config *config) |
| 606 | { |
Krishna Prasad Bhat | a6d642f | 2022-01-16 23:16:24 +0530 | [diff] [blame] | 607 | #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) |
| 608 | /* eMMC Configuration */ |
| 609 | s_cfg->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
| 610 | if (s_cfg->ScsEmmcEnabled) |
| 611 | s_cfg->ScsEmmcHs400Enabled = config->emmc_enable_hs400_mode; |
| 612 | #endif |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 613 | /* Enable Hybrid storage auto detection */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 614 | s_cfg->HybridStorageMode = config->HybridStorageMode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 615 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 616 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 617 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 618 | const struct soc_intel_alderlake_config *config) |
| 619 | { |
| 620 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 621 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 622 | if (!(enable_mask & BIT(i))) |
| 623 | continue; |
| 624 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 625 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 626 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 627 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 628 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 629 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 630 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 631 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 632 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 633 | |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 634 | static void fill_fsps_cpu_pcie_params(FSP_S_CONFIG *s_cfg, |
| 635 | const struct soc_intel_alderlake_config *config) |
| 636 | { |
| 637 | if (!CONFIG_MAX_CPU_ROOT_PORTS) |
| 638 | return; |
| 639 | |
| 640 | const uint32_t enable_mask = pcie_rp_enable_mask(get_cpu_pcie_rp_table()); |
| 641 | for (int i = 0; i < CONFIG_MAX_CPU_ROOT_PORTS; i++) { |
| 642 | if (!(enable_mask & BIT(i))) |
| 643 | continue; |
| 644 | |
| 645 | const struct pcie_rp_config *rp_cfg = &config->cpu_pcie_rp[i]; |
| 646 | s_cfg->CpuPcieRpL1Substates[i] = |
| 647 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
| 648 | s_cfg->CpuPcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 649 | s_cfg->CpuPcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 650 | s_cfg->CpuPcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 651 | s_cfg->PtmEnabled[i] = 0; |
| 652 | } |
| 653 | } |
| 654 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 655 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 656 | const struct soc_intel_alderlake_config *config) |
| 657 | { |
Subrata Banik | d6da4ef | 2021-10-07 00:39:31 +0530 | [diff] [blame] | 658 | /* Skip setting D0I3 bit for all HECI devices */ |
| 659 | s_cfg->DisableD0I3SettingForHeci = 1; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 660 | /* |
| 661 | * Power Optimizer for DMI |
| 662 | * DmiPwrOptimizeDisable is default to 0. |
| 663 | * Boards not needing the optimizers explicitly disables them by setting |
| 664 | * these disable variables to 1 in devicetree overrides. |
| 665 | */ |
| 666 | s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 667 | s_cfg->PmSupport = 1; |
| 668 | s_cfg->Hwp = 1; |
| 669 | s_cfg->Cx = 1; |
| 670 | s_cfg->PsOnEnable = 1; |
V Sowmya | 844dcb3 | 2021-06-21 10:03:53 +0530 | [diff] [blame] | 671 | /* Enable the energy efficient turbo mode */ |
| 672 | s_cfg->EnergyEfficientTurbo = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 673 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 674 | |
| 675 | /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ |
| 676 | s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 677 | |
| 678 | /* VrConfig Settings for IA and GT domains */ |
| 679 | for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 680 | fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 681 | |
Nick Vaccaro | 577afe6 | 2022-01-12 12:03:41 -0800 | [diff] [blame] | 682 | s_cfg->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(); |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 683 | |
| 684 | /* Apply minimum assertion width settings */ |
| 685 | if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) |
| 686 | s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; |
| 687 | else |
| 688 | s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; |
| 689 | |
| 690 | if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) |
| 691 | s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; |
| 692 | else |
| 693 | s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; |
| 694 | |
| 695 | if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) |
| 696 | s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; |
| 697 | else |
| 698 | s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; |
| 699 | |
| 700 | if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) |
| 701 | s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; |
| 702 | else |
| 703 | s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; |
| 704 | |
| 705 | unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; |
| 706 | if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) |
| 707 | power_cycle_duration = POWER_CYCLE_DURATION_4S; |
| 708 | |
| 709 | s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, |
| 710 | s_cfg->PchPmSlpS3MinAssert, |
| 711 | s_cfg->PchPmSlpAMinAssert, |
| 712 | power_cycle_duration); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 713 | |
| 714 | /* Set PsysPmax if it is available from DT */ |
| 715 | if (config->PsysPmax) { |
| 716 | printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax); |
| 717 | /* PsysPmax is in unit of 1/8 Watt */ |
| 718 | s_cfg->PsysPmax = config->PsysPmax * 8; |
| 719 | } |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 720 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 721 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 722 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 723 | const struct soc_intel_alderlake_config *config) |
| 724 | { |
| 725 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 726 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 727 | |
| 728 | size_t pch_count = 0; |
| 729 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 730 | |
| 731 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 732 | s_cfg->NumOfDevIntConfig = pch_count; |
| 733 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 734 | } |
| 735 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 736 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 737 | const struct soc_intel_alderlake_config *config) |
| 738 | { |
| 739 | /* PCH FIVR settings override */ |
| 740 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 741 | return; |
| 742 | |
| 743 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 744 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 745 | |
| 746 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 747 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 748 | |
| 749 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 750 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 751 | |
| 752 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 753 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 754 | |
| 755 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
Bora Guvendik | fbf874f | 2021-10-18 14:17:41 -0700 | [diff] [blame] | 756 | config->ext_fivr_settings.vnn_sx_enable_bitmap; |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 757 | |
| 758 | /* Convert the voltages to increments of 2.5mv */ |
| 759 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 760 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 761 | |
| 762 | s_cfg->PchFivrExtVnnRailVoltage = |
| 763 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 764 | |
| 765 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 766 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 767 | |
| 768 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 769 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 770 | |
| 771 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 772 | config->ext_fivr_settings.vnn_icc_max_ma; |
| 773 | } |
| 774 | |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 775 | static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, |
| 776 | const struct soc_intel_alderlake_config *config) |
| 777 | { |
| 778 | /* transform from Hz to 100 KHz */ |
| 779 | s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz); |
| 780 | s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum; |
| 781 | } |
| 782 | |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 783 | static void fill_fsps_acoustic_params(FSP_S_CONFIG *s_cfg, |
| 784 | const struct soc_intel_alderlake_config *config) |
| 785 | { |
| 786 | s_cfg->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
| 787 | |
| 788 | if (s_cfg->AcousticNoiseMitigation) { |
| 789 | for (int i = 0; i < NUM_VR_DOMAINS; i++) { |
| 790 | s_cfg->FastPkgCRampDisable[i] = config->FastPkgCRampDisable[i]; |
| 791 | s_cfg->SlowSlewRate[i] = config->SlowSlewRate[i]; |
| 792 | } |
| 793 | } |
| 794 | } |
| 795 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 796 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 797 | struct soc_intel_alderlake_config *config) |
| 798 | { |
| 799 | /* Override settings per board if required. */ |
| 800 | mainboard_update_soc_chip_config(config); |
| 801 | |
Arthur Heymans | 02967e6 | 2022-02-18 13:22:25 +0100 | [diff] [blame] | 802 | void (*const fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 803 | const struct soc_intel_alderlake_config *config) = { |
| 804 | fill_fsps_lpss_params, |
| 805 | fill_fsps_cpu_params, |
| 806 | fill_fsps_igd_params, |
| 807 | fill_fsps_tcss_params, |
| 808 | fill_fsps_chipset_lockdown_params, |
| 809 | fill_fsps_xhci_params, |
| 810 | fill_fsps_xdci_params, |
| 811 | fill_fsps_uart_params, |
| 812 | fill_fsps_sata_params, |
| 813 | fill_fsps_thermal_params, |
| 814 | fill_fsps_lan_params, |
| 815 | fill_fsps_cnvi_params, |
| 816 | fill_fsps_vmd_params, |
| 817 | fill_fsps_thc_params, |
| 818 | fill_fsps_tbt_params, |
| 819 | fill_fsps_8254_params, |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 820 | fill_fsps_pm_timer_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 821 | fill_fsps_storage_params, |
| 822 | fill_fsps_pcie_params, |
Tim Wawrzynczak | f944052 | 2021-12-16 15:07:15 -0700 | [diff] [blame] | 823 | fill_fsps_cpu_pcie_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 824 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 825 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 826 | fill_fsps_fivr_params, |
Wisley Chen | d0cef2a | 2021-11-01 16:13:55 +0600 | [diff] [blame] | 827 | fill_fsps_fivr_rfi_params, |
Wisley Chen | c510346 | 2021-11-04 18:12:58 +0600 | [diff] [blame] | 828 | fill_fsps_acoustic_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 829 | }; |
| 830 | |
| 831 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 832 | fill_fsps_params[i](s_cfg, config); |
| 833 | } |
| 834 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 835 | /* UPD parameters to be initialized before SiliconInit */ |
| 836 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 837 | { |
| 838 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 839 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 840 | |
| 841 | config = config_of_soc(); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 842 | soc_silicon_init_params(s_cfg, config); |
| 843 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 844 | } |
| 845 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 846 | /* |
| 847 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 848 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 849 | * Phase | FSP return point | Purpose |
| 850 | * ------- + ------------------------------------------------ + ------------------------------- |
| 851 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 852 | */ |
| 853 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 854 | { |
| 855 | switch (phase_index) { |
| 856 | case 1: |
| 857 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 858 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 859 | __FILE__, __func__); |
| 860 | |
| 861 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 862 | const config_t *config = config_of_soc(); |
| 863 | tcss_configure(config->typec_aux_bias_pads); |
| 864 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 865 | break; |
| 866 | default: |
| 867 | break; |
| 868 | } |
| 869 | } |
| 870 | |
| 871 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 872 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 873 | { |
| 874 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 875 | } |