Angel Pons | 3bd1e3d | 2020-04-05 15:47:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 2 | |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 3 | #include <bootsplash.h> |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 4 | #include <fsp/api.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 5 | #include <acpi/acpi.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
| 7 | #include <device/device.h> |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 8 | #include <device/pci_ids.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 9 | #include <fsp/util.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 10 | #include <gpio.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 11 | #include <option.h> |
Michael Niewöhner | f6611a2 | 2020-08-03 16:53:41 +0200 | [diff] [blame] | 12 | #include <intelblocks/acpi.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 13 | #include <intelblocks/cfg.h> |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 14 | #include <intelblocks/itss.h> |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 15 | #include <intelblocks/lpc_lib.h> |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 16 | #include <intelblocks/pcie_rp.h> |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 17 | #include <intelblocks/power_limit.h> |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 18 | #include <intelblocks/xdci.h> |
Patrick Rudolph | 5199e82 | 2019-09-26 14:00:14 +0200 | [diff] [blame] | 19 | #include <intelblocks/p2sb.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 20 | #include <intelblocks/systemagent.h> |
Subrata Banik | 9cd99a1 | 2018-05-28 16:12:03 +0530 | [diff] [blame] | 21 | #include <intelpch/lockdown.h> |
Patrick Georgi | c6a0050 | 2017-10-05 18:19:29 +0200 | [diff] [blame] | 22 | #include <soc/intel/common/vbt.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 23 | #include <soc/interrupt.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 24 | #include <soc/iomap.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 25 | #include <soc/irq.h> |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 26 | #include <soc/itss.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 27 | #include <soc/pci_devs.h> |
| 28 | #include <soc/ramstage.h> |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 29 | #include <soc/systemagent.h> |
Michael Niewöhner | 84fde76 | 2020-11-25 16:36:18 +0100 | [diff] [blame] | 30 | #include <soc/usb.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 31 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 32 | #include <types.h> |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 33 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 34 | #include "chip.h" |
| 35 | |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 36 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 37 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 38 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 4, .lcap_port_base = 1 }, |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 39 | { 0 } |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 40 | }; |
| 41 | |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 42 | static const struct pcie_rp_group pch_h_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 43 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 44 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 45 | /* Sunrise Point PCH-H actually only has 4 ports in the |
| 46 | third group. But that would require a runtime check |
| 47 | and probing 4 non-existent ports shouldn't hurt. */ |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 48 | { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 49 | { 0 } |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 50 | }; |
| 51 | |
Angel Pons | 6edbaa2 | 2021-02-19 19:49:38 +0100 | [diff] [blame] | 52 | #if CONFIG(HAVE_ACPI_TABLES) |
| 53 | const char *soc_acpi_name(const struct device *dev) |
| 54 | { |
| 55 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 56 | return "PCI0"; |
| 57 | |
| 58 | if (dev->path.type == DEVICE_PATH_USB) { |
| 59 | switch (dev->path.usb.port_type) { |
| 60 | case 0: |
| 61 | /* Root Hub */ |
| 62 | return "RHUB"; |
| 63 | case 2: |
| 64 | /* USB2 ports */ |
| 65 | switch (dev->path.usb.port_id) { |
| 66 | case 0: return "HS01"; |
| 67 | case 1: return "HS02"; |
| 68 | case 2: return "HS03"; |
| 69 | case 3: return "HS04"; |
| 70 | case 4: return "HS05"; |
| 71 | case 5: return "HS06"; |
| 72 | case 6: return "HS07"; |
| 73 | case 7: return "HS08"; |
| 74 | case 8: return "HS09"; |
| 75 | case 9: return "HS10"; |
| 76 | } |
| 77 | break; |
| 78 | case 3: |
| 79 | /* USB3 ports */ |
| 80 | switch (dev->path.usb.port_id) { |
| 81 | case 0: return "SS01"; |
| 82 | case 1: return "SS02"; |
| 83 | case 2: return "SS03"; |
| 84 | case 3: return "SS04"; |
| 85 | case 4: return "SS05"; |
| 86 | case 5: return "SS06"; |
| 87 | } |
| 88 | break; |
| 89 | } |
| 90 | return NULL; |
| 91 | } |
| 92 | |
| 93 | if (dev->path.type != DEVICE_PATH_PCI) |
| 94 | return NULL; |
| 95 | |
| 96 | /* Match functions 0 and 1 for possible GPUs on a secondary bus */ |
| 97 | if (dev->bus && dev->bus->secondary > 0) { |
| 98 | switch (PCI_FUNC(dev->path.pci.devfn)) { |
| 99 | case 0: return "DEV0"; |
| 100 | case 1: return "DEV1"; |
| 101 | } |
| 102 | return NULL; |
| 103 | } |
| 104 | |
| 105 | switch (dev->path.pci.devfn) { |
| 106 | case SA_DEVFN_ROOT: return "MCHC"; |
| 107 | case SA_DEVFN_PEG0: return "PEGP"; |
| 108 | case SA_DEVFN_IGD: return "GFX0"; |
| 109 | case PCH_DEVFN_ISH: return "ISHB"; |
| 110 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 111 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 112 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 113 | case PCH_DEVFN_CIO: return "ICIO"; |
| 114 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 115 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 116 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 117 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 118 | case PCH_DEVFN_CSE: return "CSE1"; |
| 119 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 120 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 121 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 122 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 123 | case PCH_DEVFN_SATA: return "SATA"; |
| 124 | case PCH_DEVFN_UART2: return "UAR2"; |
| 125 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 126 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 127 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 128 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 129 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 130 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 131 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 132 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 133 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 134 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 135 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 136 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 137 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 138 | case PCH_DEVFN_PCIE12: return "RP12"; |
| 139 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 140 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 141 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 142 | case PCH_DEVFN_PCIE16: return "RP16"; |
| 143 | case PCH_DEVFN_UART0: return "UAR0"; |
| 144 | case PCH_DEVFN_UART1: return "UAR1"; |
| 145 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 146 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 147 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 148 | case PCH_DEVFN_SDIO: return "SDIO"; |
| 149 | case PCH_DEVFN_SDCARD: return "SDXC"; |
| 150 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 151 | case PCH_DEVFN_PMC: return "PMC_"; |
| 152 | case PCH_DEVFN_HDA: return "HDAS"; |
| 153 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 154 | case PCH_DEVFN_SPI: return "FSPI"; |
| 155 | case PCH_DEVFN_GBE: return "IGBE"; |
| 156 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 157 | } |
| 158 | |
| 159 | return NULL; |
| 160 | } |
| 161 | #endif |
| 162 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 163 | void soc_init_pre_device(void *chip_info) |
| 164 | { |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 165 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 166 | * default policy that doesn't honor boards' requirements. */ |
| 167 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 168 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 169 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 170 | fsp_silicon_init(); |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 171 | |
Patrick Rudolph | 5199e82 | 2019-09-26 14:00:14 +0200 | [diff] [blame] | 172 | /* |
| 173 | * Keep the P2SB device visible so it and the other devices are |
| 174 | * visible in coreboot for driver support and PCI resource allocation. |
| 175 | * There is no UPD setting for this. |
| 176 | */ |
| 177 | p2sb_unhide(); |
| 178 | |
Subrata Banik | 46caf09 | 2018-09-28 19:54:30 +0530 | [diff] [blame] | 179 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 180 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 181 | |
Gaggery Tsai | 711fb81 | 2018-05-22 12:32:48 -0700 | [diff] [blame] | 182 | /* swap enabled PCI ports in device tree if needed */ |
Nico Huber | ad91b18 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 183 | if (CONFIG(SKYLAKE_SOC_PCH_H)) |
| 184 | pcie_rp_update_devicetree(pch_h_rp_groups); |
| 185 | else |
| 186 | pcie_rp_update_devicetree(pch_lp_rp_groups); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 187 | } |
| 188 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 189 | struct device_operations pci_domain_ops = { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 190 | .read_resources = &pci_domain_read_resources, |
| 191 | .set_resources = &pci_domain_set_resources, |
| 192 | .scan_bus = &pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 193 | #if CONFIG(HAVE_ACPI_TABLES) |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 194 | .acpi_name = &soc_acpi_name, |
| 195 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 196 | #endif |
| 197 | }; |
| 198 | |
| 199 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 200 | .read_resources = noop_read_resources, |
| 201 | .set_resources = noop_set_resources, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 202 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 203 | .acpi_fill_ssdt = generate_cpu_entries, |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 204 | #endif |
| 205 | }; |
| 206 | |
Elyes HAOUAS | 143fb46 | 2018-05-25 12:56:45 +0200 | [diff] [blame] | 207 | static void soc_enable(struct device *dev) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 208 | { |
| 209 | /* Set the operations if it is a special bus type */ |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 210 | if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 211 | dev->ops = &cpu_bus_ops; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 212 | } |
| 213 | |
| 214 | struct chip_operations soc_intel_skylake_ops = { |
| 215 | CHIP_NAME("Intel 6th Gen") |
| 216 | .enable_dev = &soc_enable, |
| 217 | .init = &soc_init_pre_device, |
| 218 | }; |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 219 | |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 220 | /* UPD parameters to be initialized before SiliconInit */ |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 221 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 222 | { |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 223 | FSP_S_CONFIG *params = &supd->FspsConfig; |
| 224 | FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; |
Kyösti Mälkki | 4af4e7f | 2019-07-14 05:50:20 +0300 | [diff] [blame] | 225 | struct soc_intel_skylake_config *config; |
Patrick Georgi | d2990ff | 2018-05-03 18:06:15 +0200 | [diff] [blame] | 226 | uintptr_t vbt_data = (uintptr_t)vbt_get(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 227 | int i; |
| 228 | |
Kyösti Mälkki | d5f645c | 2019-09-28 00:20:27 +0300 | [diff] [blame] | 229 | config = config_of_soc(); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 230 | |
| 231 | mainboard_silicon_init_params(params); |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 232 | |
| 233 | struct soc_power_limits_config *soc_confg; |
| 234 | config_t *confg = config_of_soc(); |
| 235 | soc_confg = &confg->power_limits_config; |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 236 | /* Set PsysPmax if it is available from DT */ |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 237 | if (soc_confg->psys_pmax) { |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 238 | /* PsysPmax is in unit of 1/8 Watt */ |
Sumeet R Pawnikar | 97c5464 | 2020-05-10 01:24:11 +0530 | [diff] [blame] | 239 | tconfig->PsysPmax = soc_confg->psys_pmax * 8; |
Gaggery Tsai | da6f4ae | 2018-01-15 15:03:01 +0800 | [diff] [blame] | 240 | printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); |
| 241 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 242 | |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 243 | params->GraphicsConfigPtr = (u32)vbt_data; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 244 | |
| 245 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
| 246 | params->PortUsb20Enable[i] = |
| 247 | config->usb2_ports[i].enable; |
| 248 | params->Usb2AfePetxiset[i] = |
| 249 | config->usb2_ports[i].pre_emp_bias; |
| 250 | params->Usb2AfeTxiset[i] = |
| 251 | config->usb2_ports[i].tx_bias; |
| 252 | params->Usb2AfePredeemp[i] = |
| 253 | config->usb2_ports[i].tx_emp_enable; |
| 254 | params->Usb2AfePehalfbit[i] = |
| 255 | config->usb2_ports[i].pre_emp_bit; |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 256 | |
| 257 | if (config->usb2_ports[i].enable) |
| 258 | params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
| 259 | else |
Michael Niewöhner | 84fde76 | 2020-11-25 16:36:18 +0100 | [diff] [blame] | 260 | params->Usb2OverCurrentPin[i] = OC_SKIP; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
| 264 | params->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Michael Niewöhner | 84fde76 | 2020-11-25 16:36:18 +0100 | [diff] [blame] | 265 | if (config->usb3_ports[i].enable) |
Michael Niewöhner | 056d552 | 2020-09-04 15:40:35 +0200 | [diff] [blame] | 266 | params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Michael Niewöhner | 84fde76 | 2020-11-25 16:36:18 +0100 | [diff] [blame] | 267 | else |
| 268 | params->Usb3OverCurrentPin[i] = OC_SKIP; |
| 269 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 270 | if (config->usb3_ports[i].tx_de_emp) { |
| 271 | params->Usb3HsioTxDeEmphEnable[i] = 1; |
| 272 | params->Usb3HsioTxDeEmph[i] = |
| 273 | config->usb3_ports[i].tx_de_emp; |
| 274 | } |
| 275 | if (config->usb3_ports[i].tx_downscale_amp) { |
| 276 | params->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 277 | params->Usb3HsioTxDownscaleAmp[i] = |
| 278 | config->usb3_ports[i].tx_downscale_amp; |
| 279 | } |
| 280 | } |
| 281 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 282 | params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
Felix Singer | 0901d03 | 2020-07-29 19:57:25 +0200 | [diff] [blame] | 283 | if (params->SataEnable) { |
Felix Singer | 4e58ce1 | 2020-07-25 04:39:52 +0200 | [diff] [blame] | 284 | memcpy(params->SataPortsEnable, config->SataPortsEnable, |
| 285 | sizeof(params->SataPortsEnable)); |
| 286 | memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, |
| 287 | sizeof(params->SataPortsDevSlp)); |
| 288 | memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, |
| 289 | sizeof(params->SataPortsHotPlug)); |
| 290 | memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, |
| 291 | sizeof(params->SataPortsSpinUp)); |
| 292 | |
| 293 | params->SataSalpSupport = config->SataSalpSupport; |
| 294 | params->SataMode = config->SataMode; |
| 295 | params->SataSpeedLimit = config->SataSpeedLimit; |
| 296 | /* |
| 297 | * For unknown reasons FSP skips writing some essential SATA init registers |
| 298 | * (SIR) when SataPwrOptEnable=0. This results in link errors, "unaligned |
| 299 | * write" errors and others. Enabling this option solves these problems. |
| 300 | */ |
| 301 | params->SataPwrOptEnable = 1; |
Angel Pons | 8f3e119 | 2021-04-04 16:20:54 +0200 | [diff] [blame] | 302 | tconfig->SataTestMode = CONFIG(ENABLE_SATA_TEST_MODE); |
Felix Singer | 4e58ce1 | 2020-07-25 04:39:52 +0200 | [diff] [blame] | 303 | } |
| 304 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 305 | memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, |
| 306 | sizeof(params->PcieRpClkReqSupport)); |
| 307 | memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, |
| 308 | sizeof(params->PcieRpClkReqNumber)); |
Rizwan Qureshi | 6ab4ed4 | 2017-09-05 14:18:25 +0530 | [diff] [blame] | 309 | memcpy(params->PcieRpAdvancedErrorReporting, |
| 310 | config->PcieRpAdvancedErrorReporting, |
| 311 | sizeof(params->PcieRpAdvancedErrorReporting)); |
Rizwan Qureshi | 0393739 | 2017-09-16 01:54:20 +0530 | [diff] [blame] | 312 | memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, |
| 313 | sizeof(params->PcieRpLtrEnable)); |
Duncan Laurie | 74ea48e | 2018-01-29 12:00:47 -0800 | [diff] [blame] | 314 | memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, |
| 315 | sizeof(params->PcieRpHotPlug)); |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 316 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
Wim Vervoorn | d6b682c | 2020-05-07 12:41:13 +0200 | [diff] [blame] | 317 | params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; |
Benjamin Doron | b53858b | 2020-10-12 04:19:42 +0000 | [diff] [blame] | 318 | if (config->pcie_rp_aspm[i]) |
| 319 | params->PcieRpAspm[i] = config->pcie_rp_aspm[i] - 1; |
Benjamin Doron | adcb870 | 2020-03-14 01:53:25 +0000 | [diff] [blame] | 320 | if (config->pcie_rp_l1substates[i]) |
| 321 | params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1; |
Wim Vervoorn | 5819eab | 2020-05-07 13:16:32 +0200 | [diff] [blame] | 322 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 323 | |
Divya Chellap | e7fb7ce | 2017-12-19 20:16:50 +0530 | [diff] [blame] | 324 | /* |
| 325 | * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for |
| 326 | * all the enabled PCIe root ports, invalid(0x1F) is set for |
| 327 | * disabled PCIe root ports. |
| 328 | */ |
| 329 | for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { |
| 330 | if (config->PcieRpClkReqSupport[i]) |
| 331 | params->PcieRpClkSrcNumber[i] = |
| 332 | config->PcieRpClkSrcNumber[i]; |
| 333 | else |
| 334 | params->PcieRpClkSrcNumber[i] = 0x1F; |
| 335 | } |
| 336 | |
Naresh G Solanki | eedf6d8 | 2016-11-16 21:27:38 +0530 | [diff] [blame] | 337 | /* disable Legacy PME */ |
| 338 | memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); |
| 339 | |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 340 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 341 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 342 | params->Early8254ClockGatingEnable = !use_8254; |
Subrata Banik | 10a9432 | 2019-07-08 14:49:22 +0530 | [diff] [blame] | 343 | |
Michael Niewöhner | 0e90580 | 2021-09-25 00:10:30 +0200 | [diff] [blame] | 344 | /* |
| 345 | * Legacy PM ACPI Timer (and TCO Timer) |
| 346 | * This *must* be 1 in any case to keep FSP from |
| 347 | * 1) enabling PM ACPI Timer emulation in uCode. |
| 348 | * 2) disabling the PM ACPI Timer. |
| 349 | * We handle both by ourself! |
| 350 | */ |
| 351 | params->EnableTcoTimer = 1; |
Michael Niewöhner | a1843d8 | 2020-10-02 18:28:22 +0200 | [diff] [blame] | 352 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 353 | memcpy(params->SerialIoDevMode, config->SerialIoDevMode, |
| 354 | sizeof(params->SerialIoDevMode)); |
| 355 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 356 | params->PchCio2Enable = is_devfn_enabled(PCH_DEVFN_CIO); |
Felix Singer | 4d5c4e0 | 2020-07-29 22:28:37 +0200 | [diff] [blame] | 357 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 358 | params->SaImguEnable = is_devfn_enabled(SA_DEVFN_IMGU); |
Felix Singer | 91dfb92 | 2020-07-25 14:01:52 +0200 | [diff] [blame] | 359 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 360 | tconfig->ChapDeviceEnable = is_devfn_enabled(SA_DEVFN_CHAP); |
Benjamin Doron | d0701c9 | 2020-12-07 22:56:47 +0000 | [diff] [blame] | 361 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 362 | params->Heci3Enabled = is_devfn_enabled(PCH_DEVFN_CSE_3); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 363 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 364 | params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 365 | |
| 366 | params->PchPmWoWlanEnable = config->PchPmWoWlanEnable; |
| 367 | params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable; |
| 368 | params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 369 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 370 | params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Felix Singer | 57c8143 | 2020-07-25 07:50:51 +0200 | [diff] [blame] | 371 | if (params->PchLanEnable) { |
Duncan Laurie | 14485ef | 2017-12-13 13:58:35 -0800 | [diff] [blame] | 372 | params->PchLanLtrEnable = config->EnableLanLtr; |
| 373 | params->PchLanK1OffEnable = config->EnableLanK1Off; |
| 374 | params->PchLanClkReqSupported = config->LanClkReqSupported; |
| 375 | params->PchLanClkReqNumber = config->LanClkReqNumber; |
| 376 | } |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 377 | params->SsicPortEnable = config->SsicPortEnable; |
Felix Singer | aff69be | 2020-07-25 13:37:17 +0200 | [diff] [blame] | 378 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 379 | params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 380 | params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; |
Felix Singer | 5291952 | 2020-07-29 21:44:36 +0200 | [diff] [blame] | 381 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 382 | params->ScsSdCardEnabled = is_devfn_enabled(PCH_DEVFN_SDCARD); |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 383 | |
Pratik Prajapati | e072247 | 2018-08-22 18:58:38 -0700 | [diff] [blame] | 384 | if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { |
| 385 | params->PchScsEmmcHs400DllDataValid = |
| 386 | !!config->EmmcHs400DllNeed; |
| 387 | params->PchScsEmmcHs400RxStrobeDll1 = |
| 388 | config->ScsEmmcHs400RxStrobeDll1; |
| 389 | params->PchScsEmmcHs400TxDataDll = |
| 390 | config->ScsEmmcHs400TxDataDll; |
| 391 | } |
| 392 | |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 393 | /* If ISH is enabled, enable ISH elements */ |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 394 | params->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH); |
li feng | 2106638 | 2018-05-22 12:49:53 -0700 | [diff] [blame] | 395 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 396 | params->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA); |
Felix Singer | 048d9b5 | 2020-07-25 14:31:58 +0200 | [diff] [blame] | 397 | |
Michael Niewöhner | 6238563 | 2019-09-23 14:38:41 +0200 | [diff] [blame] | 398 | params->PchHdaVcType = config->PchHdaVcType; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 399 | params->PchHdaIoBufferOwnership = config->IoBufferOwnership; |
| 400 | params->PchHdaDspEnable = config->DspEnable; |
Felix Singer | 9c1c009 | 2020-07-29 20:48:08 +0200 | [diff] [blame] | 401 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 402 | params->Device4Enable = is_devfn_enabled(SA_DEVFN_TS); |
| 403 | params->PchThermalDeviceEnable = is_devfn_enabled(PCH_DEVFN_THERMAL); |
Matt DeVillier | 9e0d69b | 2017-10-10 14:03:36 -0500 | [diff] [blame] | 404 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 405 | tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 406 | tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; |
Angel Pons | 950cdbc | 2020-12-11 17:00:42 +0100 | [diff] [blame] | 407 | tconfig->PowerLimit4 = 0; |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 408 | /* |
| 409 | * To disable HECI, the Psf needs to be left unlocked |
Subrata Banik | a0d9ad3 | 2022-01-03 18:07:13 +0000 | [diff] [blame] | 410 | * by FSP till end of post sequence. Based on the config |
Barnali Sarkar | fbf1018 | 2017-08-11 18:38:38 +0530 | [diff] [blame] | 411 | * setting, we set the appropriate PsfUnlock policy in FSP, |
| 412 | * do the changes and then lock it back in coreboot during finalize. |
| 413 | */ |
Subrata Banik | a0d9ad3 | 2022-01-03 18:07:13 +0000 | [diff] [blame] | 414 | tconfig->PchSbAccessUnlock = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); |
Felix Singer | 5385b4d | 2021-05-03 02:25:08 +0200 | [diff] [blame] | 415 | |
| 416 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 417 | tconfig->PchLockDownBiosInterface = lockdown_by_fsp; |
| 418 | params->PchLockDownBiosLock = lockdown_by_fsp; |
| 419 | params->PchLockDownSpiEiss = lockdown_by_fsp; |
| 420 | /* |
| 421 | * Making this config "0" means FSP won't set the FLOCKDN bit |
| 422 | * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). |
| 423 | * So, it becomes coreboot's responsibility to set this bit |
| 424 | * before end of POST for security concerns. |
| 425 | */ |
| 426 | params->SpiFlashCfgLockDown = lockdown_by_fsp; |
| 427 | |
Benjamin Doron | dc66798 | 2020-10-16 18:07:13 +0000 | [diff] [blame] | 428 | /* FSP should let coreboot set subsystem IDs, which are read/write-once */ |
| 429 | params->DefaultSvid = 0; |
| 430 | params->PchSubSystemVendorId = 0; |
| 431 | params->DefaultSid = 0; |
| 432 | params->PchSubSystemId = 0; |
Elyes HAOUAS | b58e99d | 2019-01-23 12:04:43 +0100 | [diff] [blame] | 433 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 434 | params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; |
| 435 | params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; |
| 436 | params->PchPmDeepSxPol = config->PmConfigDeepSxPol; |
Duncan Laurie | 25c7d93 | 2017-02-17 17:16:43 -0800 | [diff] [blame] | 437 | params->PchPmSlpS0Enable = config->s0ix_enable; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 438 | params->PchPmSlpS3MinAssert = config->PmConfigSlpS3MinAssert; |
| 439 | params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert; |
| 440 | params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert; |
| 441 | params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 442 | params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp; |
| 443 | params->PchPmPwrBtnOverridePeriod = |
| 444 | config->PmConfigPwrBtnOverridePeriod; |
| 445 | params->PchPmPwrCycDur = config->PmConfigPwrCycDur; |
Rizwan Qureshi | 0da186c | 2017-02-23 14:43:39 +0530 | [diff] [blame] | 446 | |
| 447 | /* Indicate whether platform supports Voltage Margining */ |
| 448 | params->PchPmSlpS0VmEnable = config->PchPmSlpS0VmEnable; |
| 449 | |
Nico Huber | 44e89af | 2019-02-23 19:24:51 +0100 | [diff] [blame] | 450 | params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF; |
| 451 | params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 452 | |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 453 | params->CpuConfig.Bits.SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 454 | |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 455 | for (i = 0; i < ARRAY_SIZE(config->i2c_voltage); i++) |
Aaron Durbin | ed14a4e | 2016-11-09 17:04:15 -0600 | [diff] [blame] | 456 | params->SerialIoI2cVoltage[i] = config->i2c_voltage[i]; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 457 | |
| 458 | for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 459 | fill_vr_domain_config(params, i, &config->domain_vr_config[i]); |
| 460 | |
| 461 | /* Show SPI controller if enabled in devicetree.cb */ |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 462 | params->ShowSpiController = is_devfn_enabled(PCH_DEVFN_SPI); |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 463 | |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 464 | params->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Duncan Laurie | f511695 | 2018-03-26 02:24:18 -0700 | [diff] [blame] | 465 | |
Maxim Polyakov | 03ddd19 | 2019-08-30 18:04:02 +0300 | [diff] [blame] | 466 | /* Enable or disable Gaussian Mixture Model in devicetree */ |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 467 | params->GmmEnable = is_devfn_enabled(SA_DEVFN_GMM); |
Maxim Polyakov | 03ddd19 | 2019-08-30 18:04:02 +0300 | [diff] [blame] | 468 | |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 469 | /* |
| 470 | * Send VR specific mailbox commands: |
| 471 | * 000b - no VR specific command sent |
| 472 | * 001b - VR mailbox command specifically for the MPS IMPV8 VR |
Lee Leahy | f4c4ab9 | 2017-03-16 17:08:03 -0700 | [diff] [blame] | 473 | * will be sent |
Rizwan Qureshi | 6467014 | 2016-11-23 15:25:19 +0530 | [diff] [blame] | 474 | * 010b - VR specific command sent for PS4 exit issue |
| 475 | * 100b - VR specific command sent for MPS VR decay issue |
| 476 | */ |
| 477 | params->SendVrMbxCmd1 = config->SendVrMbxCmd; |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 478 | |
Rizwan Qureshi | b3e18c7 | 2017-09-25 17:35:15 +0530 | [diff] [blame] | 479 | /* |
| 480 | * Activates VR mailbox command for Intersil VR C-state issues. |
| 481 | * 0 - no mailbox command sent. |
| 482 | * 1 - VR mailbox command sent for IA/GT rails only. |
| 483 | * 2 - VR mailbox command sent for IA/GT/SA rails. |
| 484 | */ |
| 485 | params->IslVrCmd = config->IslVrCmd; |
| 486 | |
Duncan Laurie | b2aac85 | 2017-03-07 19:12:02 -0800 | [diff] [blame] | 487 | /* Acoustic Noise Mitigation */ |
| 488 | params->AcousticNoiseMitigation = config->AcousticNoiseMitigation; |
| 489 | params->SlowSlewRateForIa = config->SlowSlewRateForIa; |
| 490 | params->SlowSlewRateForGt = config->SlowSlewRateForGt; |
| 491 | params->SlowSlewRateForSa = config->SlowSlewRateForSa; |
| 492 | params->FastPkgCRampDisableIa = config->FastPkgCRampDisableIa; |
| 493 | params->FastPkgCRampDisableGt = config->FastPkgCRampDisableGt; |
| 494 | params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; |
| 495 | |
Rizwan Qureshi | ffe5810 | 2017-02-10 15:58:24 +0530 | [diff] [blame] | 496 | /* Enable PMC XRAM read */ |
| 497 | tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; |
| 498 | |
Subrata Banik | 6b45ee4 | 2017-05-12 11:43:57 +0530 | [diff] [blame] | 499 | /* Enable/Disable EIST */ |
| 500 | tconfig->Eist = config->eist_enable; |
| 501 | |
marxwang | ec5a947 | 2017-12-11 14:57:49 +0800 | [diff] [blame] | 502 | /* Set TccActivationOffset */ |
| 503 | tconfig->TccActivationOffset = config->tcc_offset; |
| 504 | |
Angel Pons | 4ff63d3 | 2019-08-30 20:05:33 +0200 | [diff] [blame] | 505 | /* Already handled in coreboot code, so tell FSP to ignore UPDs */ |
| 506 | params->PchIoApicBdfValid = 0; |
| 507 | |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 508 | /* Enable VT-d and X2APIC */ |
Sean Rhodes | 66c8062 | 2021-07-13 07:23:22 +0100 | [diff] [blame] | 509 | if (soc_vtd_enabled()) { |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 510 | params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; |
| 511 | params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS; |
| 512 | params->X2ApicOptOut = 0; |
| 513 | tconfig->VtdDisable = 0; |
Nico Huber | 2afe4dc | 2017-09-19 09:36:03 +0200 | [diff] [blame] | 514 | } |
| 515 | |
Angel Pons | 7ff3f31 | 2021-06-23 12:13:57 +0200 | [diff] [blame] | 516 | params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
Michael Niewöhner | d60089b | 2019-10-26 10:44:33 +0200 | [diff] [blame] | 517 | |
Benjamin Doron | bbb8123 | 2020-06-28 02:43:53 +0000 | [diff] [blame] | 518 | params->PavpEnable = CONFIG(PAVP); |
| 519 | |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 520 | soc_irq_settings(params); |
Rizwan Qureshi | 1222a73 | 2016-08-23 14:31:23 +0530 | [diff] [blame] | 521 | } |
Lee Leahy | b000513 | 2015-05-12 18:19:47 -0700 | [diff] [blame] | 522 | |
Felix Singer | 3616e9c | 2020-11-25 20:10:49 +0000 | [diff] [blame] | 523 | /* Mainboard FSP Configuration */ |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 524 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) |
Naresh G Solanki | a2d4062 | 2016-08-30 20:47:13 +0530 | [diff] [blame] | 525 | { |
| 526 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 527 | } |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 528 | |
| 529 | /* Handle FSP logo params */ |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 530 | void soc_load_logo(FSPS_UPD *supd) |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 531 | { |
Kyösti Mälkki | 4949a3d | 2021-01-09 20:38:43 +0200 | [diff] [blame] | 532 | bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); |
Wim Vervoorn | d137150 | 2019-12-17 14:10:16 +0100 | [diff] [blame] | 533 | } |