soc/intel: transition full control over PM Timer from FSP to coreboot
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index c99067d..d706e12 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -345,7 +345,14 @@
bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER));
params->Early8254ClockGatingEnable = !use_8254;
- params->EnableTcoTimer = CONFIG(USE_PM_ACPI_TIMER);
+ /*
+ * Legacy PM ACPI Timer (and TCO Timer)
+ * This *must* be 1 in any case to keep FSP from
+ * 1) enabling PM ACPI Timer emulation in uCode.
+ * 2) disabling the PM ACPI Timer.
+ * We handle both by ourself!
+ */
+ params->EnableTcoTimer = 1;
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
sizeof(params->SerialIoDevMode));