soc/intel/skylake: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.
The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).
We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.
Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index b4fed26..4ac73b5 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -31,9 +31,11 @@
#include <soc/acpi.h>
#include <soc/intel/common/vbt.h>
#include <soc/interrupt.h>
+#include <soc/iomap.h>
#include <soc/irq.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
+#include <soc/systemagent.h>
#include <string.h>
void soc_init_pre_device(void *chip_info)
@@ -326,6 +328,19 @@
/* Set TccActivationOffset */
tconfig->TccActivationOffset = config->tcc_offset;
+ /* Enable VT-d and X2APIC */
+ if (!config->ignore_vtd && soc_is_vtd_capable()) {
+ params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
+ params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
+ params->X2ApicOptOut = 0;
+ tconfig->VtdDisable = 0;
+
+ params->PchIoApicBdfValid = 1;
+ params->PchIoApicBusNumber = 250;
+ params->PchIoApicDeviceNumber = 31;
+ params->PchIoApicFunctionNumber = 0;
+ }
+
soc_irq_settings(params);
}