commit 97c5464443306f26b61cec3a0f50108a5c06b7ef
author Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Sun May 10 01:24:11 2020 +0530
committer Patrick Georgi <pgeorgi@google.com> Mon May 18 07:13:23 2020 +0000
tree f085457907ad200a0d9d9be8a07c937e755fae91
parent 19c2ce7639d55908d210782ae5a0315396cc7eaf

skylake: update processor power limits configuration

Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on nami system

Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/skylake/chip.c

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index ce566cf..b14bb72 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -14,6 +14,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/mp_init.h>
 #include <intelblocks/pcie_rp.h>
+#include <intelblocks/power_limit.h>
 #include <intelblocks/xdci.h>
 #include <intelblocks/p2sb.h>
 #include <intelpch/lockdown.h>
@@ -124,10 +125,14 @@
 	config = config_of_soc();
 
 	mainboard_silicon_init_params(params);
+
+	struct soc_power_limits_config *soc_confg;
+	config_t *confg = config_of_soc();
+	soc_confg = &confg->power_limits_config;
 	/* Set PsysPmax if it is available from DT */
-	if (config->psys_pmax) {
+	if (soc_confg->psys_pmax) {
 		/* PsysPmax is in unit of 1/8 Watt */
-		tconfig->PsysPmax = config->psys_pmax * 8;
+		tconfig->PsysPmax = soc_confg->psys_pmax * 8;
 		printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax);
 	}