Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 2 | |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
John Zhao | eac84ca | 2018-08-13 09:45:37 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 5 | #include <bootmode.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 10 | #include <drivers/intel/gma/i915.h> |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 11 | #include <drivers/intel/gma/libgfxinit.h> |
| 12 | #include <drivers/intel/gma/opregion.h> |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 13 | #include <intelblocks/cfg.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 14 | #include <intelblocks/graphics.h> |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 15 | #include <fsp/graphics.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Nico Huber | bd4af10 | 2020-04-26 20:43:42 +0200 | [diff] [blame] | 17 | #include <types.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 18 | |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 19 | /* Display Type: |
| 20 | * 0 - only internal display aka eDP attached |
| 21 | * 1 - only external display aka HDMI/USB-C attached |
| 22 | * 2 - dual display aka both internal and external display attached |
| 23 | */ |
| 24 | enum display_type { |
| 25 | INTERNAL_DISPLAY_ONLY, |
| 26 | EXTERNAL_DISPLAY_ONLY, |
| 27 | DUAL_DISPLAY, |
| 28 | }; |
| 29 | |
Subrata Banik | 205f30b | 2023-08-04 22:52:24 +0530 | [diff] [blame] | 30 | #define GFX_MBUS_CTL 0x4438C |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 31 | #define GFX_MBUS_SEL(x) (GFX_MBUS_CTL + (x)) |
Subrata Banik | 205f30b | 2023-08-04 22:52:24 +0530 | [diff] [blame] | 32 | #define GFX_MBUS_JOIN BIT(31) |
| 33 | #define GFX_MBUS_HASHING_MODE BIT(30) |
| 34 | #define GFX_MBUS_JOIN_PIPE_SEL (BIT(28) | BIT(27) | BIT(26)) |
| 35 | |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 36 | /* SoC Overrides */ |
Matt DeVillier | 395ab9d | 2020-12-23 17:30:27 -0600 | [diff] [blame] | 37 | __weak void graphics_soc_panel_init(struct device *dev) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 38 | { |
| 39 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 40 | * User needs to implement SoC override in case wishes |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 41 | * to perform certain specific graphics initialization |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 42 | */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 43 | } |
| 44 | |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 45 | __weak const struct i915_gpu_controller_info * |
Furquan Shaikh | ec3dafd | 2020-04-24 21:53:42 -0700 | [diff] [blame] | 46 | intel_igd_get_controller_info(const struct device *device) |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 47 | { |
| 48 | return NULL; |
| 49 | } |
| 50 | |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 51 | static uint32_t graphics_get_ddi_func_ctrl(unsigned long reg) |
| 52 | { |
| 53 | uint32_t ddi_func_ctrl = graphics_gtt_read(reg); |
| 54 | ddi_func_ctrl &= TRANS_DDI_PORT_MASK; |
| 55 | |
| 56 | return ddi_func_ctrl; |
| 57 | } |
| 58 | |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame] | 59 | /* |
| 60 | * Transcoders contain the timing generators for eDP, DP, and HDMI interfaces. |
| 61 | * Intel transcoders are based on Quick Sync Video, which offloads video |
| 62 | * encoding and decoding tasks from the CPU to the GPU. |
| 63 | * |
| 64 | * On Intel silicon, there are four display pipes (DDI-A to DDI-D) that support |
| 65 | * blending, color adjustments, scaling, and dithering. |
| 66 | * |
| 67 | * From the display block diagram perspective, the front end of the display |
| 68 | * contains the pipes. The pipes connect to the transcoder. The transcoder |
| 69 | * (except for wireless) connects to the DDIs to drive the IO/PHY. |
| 70 | * |
| 71 | * This logic checks if the DDI-A port is attached to the transcoder and |
| 72 | * enabled (bit 27). Traditionally, the on-board display (eDP) is attached to DDI-A. |
| 73 | * If the above conditions is met, then the on-board display is present and enabled. |
| 74 | * |
| 75 | * On platforms without an on-board display (i.e., value at bits 27-30 is between 2-9), |
| 76 | * meaning that DDI-A (eDP) is not enabled. |
| 77 | * |
| 78 | * Additionally, if bits 27-30 are all set to 0, this means that no DDI ports |
| 79 | * are enabled, and there is no display. |
| 80 | * |
| 81 | * Consider external display is present and enabled, if eDP/DDI-A is not enabled |
| 82 | * and transcoder is attached to any DDI port (bits 27-30 are not zero). |
| 83 | */ |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 84 | static enum display_type get_external_display_status(void) |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame] | 85 | { |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 86 | /* Read the transcoder register for DDI-A (eDP) */ |
| 87 | uint32_t ddi_a_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_A); |
| 88 | /* Read the transcoder register for DDI-B (HDMI) */ |
| 89 | uint32_t ddi_b_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_B); |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame] | 90 | |
| 91 | /* |
| 92 | * Check if transcoder is none or connected to DDI-A port (aka eDP). |
| 93 | * Report no external display in both cases. |
| 94 | */ |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 95 | if (ddi_a_func_ctrl == TRANS_DDI_PORT_NONE) { |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 96 | return INTERNAL_DISPLAY_ONLY; |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame] | 97 | } else { |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 98 | if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A) && |
| 99 | (ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_B) |
| 100 | #if CONFIG(INTEL_GMA_VERSION_2) |
| 101 | || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C1) |
| 102 | || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C2) |
| 103 | || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C3) |
| 104 | || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C4) |
| 105 | #endif |
| 106 | )) { |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 107 | /* |
| 108 | * Dual display detected: both DDI-A(eDP) and |
| 109 | * DDI-B(HDMI) pipes are active |
| 110 | */ |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 111 | return DUAL_DISPLAY; |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 112 | } else { |
| 113 | if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A)) |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 114 | return INTERNAL_DISPLAY_ONLY; |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 115 | else |
Subrata Banik | 739f83e | 2023-10-27 16:39:02 +0530 | [diff] [blame] | 116 | return EXTERNAL_DISPLAY_ONLY; |
Subrata Banik | 8da57ba | 2023-10-15 17:33:59 +0530 | [diff] [blame] | 117 | } |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame] | 118 | } |
| 119 | } |
| 120 | |
| 121 | /* Check and report if an external display is attached */ |
| 122 | int fsp_soc_report_external_display(void) |
| 123 | { |
| 124 | return graphics_get_framebuffer_address() && get_external_display_status(); |
| 125 | } |
| 126 | |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 127 | static void gma_init(struct device *const dev) |
| 128 | { |
| 129 | intel_gma_init_igd_opregion(); |
| 130 | |
Matt DeVillier | 395ab9d | 2020-12-23 17:30:27 -0600 | [diff] [blame] | 131 | /* SoC specific panel init/configuration. |
| 132 | If FSP has already run/configured the IGD, we can assume the |
| 133 | panel/backlight control have already been set up sufficiently |
| 134 | and that we shouldn't attempt to reconfigure things. */ |
| 135 | if (!CONFIG(RUN_FSP_GOP)) |
| 136 | graphics_soc_panel_init(dev); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 137 | |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 138 | if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { |
| 139 | const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); |
| 140 | /* Only program if the buffer is not enabled yet. */ |
| 141 | if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) |
| 142 | graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); |
| 143 | } |
| 144 | |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 145 | /* |
| 146 | * GFX PEIM module inside FSP binary is taking care of graphics |
| 147 | * initialization based on RUN_FSP_GOP Kconfig option and input |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 148 | * VBT file. Need to report the framebuffer info after PCI enumeration. |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 149 | * |
| 150 | * In case of non-FSP solution, SoC need to select another |
| 151 | * Kconfig to perform GFX initialization. |
| 152 | */ |
Subrata Banik | be0590c | 2023-02-14 18:44:09 +0530 | [diff] [blame] | 153 | if (CONFIG(RUN_FSP_GOP) && display_init_required()) { |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 154 | const struct soc_intel_common_config *config = chip_get_common_soc_structure(); |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 155 | fsp_report_framebuffer_info(graphics_get_framebuffer_address(), |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 156 | config->panel_orientation); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 157 | return; |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 158 | } |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 159 | |
Nico Huber | dd59762 | 2020-04-26 19:46:35 +0200 | [diff] [blame] | 160 | if (!CONFIG(NO_GFX_INIT)) |
| 161 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 162 | |
| 163 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
| 164 | if (!acpi_is_wakeup_s3() && display_init_required()) { |
| 165 | int lightup_ok; |
| 166 | gma_gfxinit(&lightup_ok); |
| 167 | gfx_set_init_done(lightup_ok); |
| 168 | } |
| 169 | } else { |
| 170 | /* Initialize PCI device, load/execute BIOS Option ROM */ |
| 171 | pci_dev_init(dev); |
| 172 | } |
| 173 | } |
| 174 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 175 | static void gma_generate_ssdt(const struct device *device) |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 176 | { |
| 177 | const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); |
| 178 | |
| 179 | if (gfx) |
| 180 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 181 | } |
| 182 | |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 183 | static int is_graphics_disabled(struct device *dev) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 184 | { |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 185 | /* Check if Graphics PCI device is disabled */ |
John Zhao | eac84ca | 2018-08-13 09:45:37 -0700 | [diff] [blame] | 186 | if (!dev || !dev->enabled) |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 187 | return 1; |
| 188 | |
| 189 | return 0; |
| 190 | } |
| 191 | |
| 192 | static uintptr_t graphics_get_bar(struct device *dev, unsigned long index) |
| 193 | { |
| 194 | struct resource *gm_res; |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 195 | |
Angel Pons | c1bfbe0 | 2021-11-03 13:18:53 +0100 | [diff] [blame] | 196 | gm_res = probe_resource(dev, index); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 197 | if (!gm_res) |
| 198 | return 0; |
| 199 | |
| 200 | return gm_res->base; |
| 201 | } |
| 202 | |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 203 | uintptr_t graphics_get_framebuffer_address(void) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 204 | { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 205 | uintptr_t memory_base; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 206 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 207 | |
| 208 | if (is_graphics_disabled(dev)) |
| 209 | return 0; |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 210 | |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 211 | memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 212 | if (!memory_base) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 213 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 214 | "Graphic memory bar2 is not programmed!"); |
| 215 | |
| 216 | memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET; |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 217 | |
| 218 | return memory_base; |
| 219 | } |
| 220 | |
| 221 | static uintptr_t graphics_get_gtt_base(void) |
| 222 | { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 223 | static uintptr_t gtt_base; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 224 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 225 | |
| 226 | if (is_graphics_disabled(dev)) |
| 227 | die("IGD is disabled!"); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 228 | /* |
| 229 | * GFX PCI config space offset 0x10 know as Graphics |
| 230 | * Translation Table Memory Mapped Range Address |
| 231 | * (GTTMMADR) |
| 232 | */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 233 | if (!gtt_base) { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 234 | gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 235 | if (!gtt_base) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 236 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 237 | "GTTMMADR is not programmed!"); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 238 | } |
| 239 | return gtt_base; |
| 240 | } |
| 241 | |
| 242 | uint32_t graphics_gtt_read(unsigned long reg) |
| 243 | { |
Elyes Haouas | c4fbeac | 2022-12-04 16:06:02 +0100 | [diff] [blame] | 244 | return read32p(graphics_get_gtt_base() + reg); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 245 | } |
| 246 | |
| 247 | void graphics_gtt_write(unsigned long reg, uint32_t data) |
| 248 | { |
Elyes Haouas | c4fbeac | 2022-12-04 16:06:02 +0100 | [diff] [blame] | 249 | write32p(graphics_get_gtt_base() + reg, data); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 250 | } |
| 251 | |
| 252 | void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) |
| 253 | { |
| 254 | uint32_t val = graphics_gtt_read(reg); |
| 255 | val &= andmask; |
| 256 | val |= ormask; |
| 257 | graphics_gtt_write(reg, val); |
| 258 | } |
| 259 | |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 260 | static void graphics_dev_read_resources(struct device *dev) |
| 261 | { |
| 262 | pci_dev_read_resources(dev); |
| 263 | |
| 264 | if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) { |
| 265 | struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 266 | if (res_bar0->flags & IORESOURCE_PREFETCH) |
| 267 | res_bar0->flags &= ~IORESOURCE_PREFETCH; |
| 268 | } |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 269 | |
| 270 | /* |
| 271 | * If libhwbase static MMIO driver is used, IGD BAR 0 has to be set to |
| 272 | * CONFIG_GFX_GMA_DEFAULT_MMIO for the libgfxinit to operate properly. |
| 273 | */ |
| 274 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && CONFIG(HWBASE_STATIC_MMIO)) { |
| 275 | struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 276 | res_bar0->base = CONFIG_GFX_GMA_DEFAULT_MMIO; |
| 277 | res_bar0->flags |= IORESOURCE_ASSIGNED; |
| 278 | pci_dev_set_resources(dev); |
| 279 | res_bar0->flags |= IORESOURCE_FIXED; |
| 280 | } |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 281 | } |
| 282 | |
Subrata Banik | 370b233 | 2023-11-02 00:31:45 +0530 | [diff] [blame^] | 283 | static void graphics_join_mbus(void) |
| 284 | { |
| 285 | enum display_type type = get_external_display_status(); |
| 286 | uint32_t hashing_mode = 0; /* 2x2 */ |
| 287 | if (type == INTERNAL_DISPLAY_ONLY) { |
| 288 | hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */ |
| 289 | /* Only eDP pipes is joining the MBUS */ |
| 290 | graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode); |
| 291 | } else if (type == DUAL_DISPLAY) { |
| 292 | /* All pipes are joining the MBUS */ |
| 293 | graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode); |
| 294 | graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode); |
| 295 | graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode); |
| 296 | #if CONFIG(INTEL_GMA_VERSION_2) |
| 297 | graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode); |
| 298 | #endif |
| 299 | } else { |
| 300 | /* No pipe joins the MBUS */ |
| 301 | graphics_gtt_rmw(GFX_MBUS_CTL, GFX_MBUS_JOIN_PIPE_SEL, |
| 302 | GFX_MBUS_JOIN | hashing_mode); |
| 303 | } |
| 304 | } |
| 305 | |
Subrata Banik | 205f30b | 2023-08-04 22:52:24 +0530 | [diff] [blame] | 306 | static void graphics_dev_final(struct device *dev) |
| 307 | { |
| 308 | pci_dev_request_bus_master(dev); |
| 309 | |
Subrata Banik | 370b233 | 2023-11-02 00:31:45 +0530 | [diff] [blame^] | 310 | /* |
| 311 | * Call function to join the MBUS if GFX PEIM module inside FSP |
| 312 | * binary is taking care of graphics initialization based on |
| 313 | * RUN_FSP_GOP config option. |
| 314 | * |
| 315 | * Skip FW joining the MBUS in case of non-FSP solution. |
| 316 | */ |
| 317 | if (CONFIG(RUN_FSP_GOP) && CONFIG(SOC_INTEL_GFX_MBUS_JOIN) && display_init_required()) |
| 318 | graphics_join_mbus(); |
Subrata Banik | 205f30b | 2023-08-04 22:52:24 +0530 | [diff] [blame] | 319 | } |
| 320 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 321 | const struct device_operations graphics_ops = { |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 322 | .read_resources = graphics_dev_read_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 323 | .set_resources = pci_dev_set_resources, |
| 324 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 325 | .init = gma_init, |
Subrata Banik | 205f30b | 2023-08-04 22:52:24 +0530 | [diff] [blame] | 326 | .final = graphics_dev_final, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 327 | .ops_pci = &pci_dev_ops_pci, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 328 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 329 | .acpi_fill_ssdt = gma_generate_ssdt, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 330 | #endif |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 331 | .scan_bus = scan_generic_bus, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 332 | }; |
| 333 | |
| 334 | static const unsigned short pci_device_ids[] = { |
Bora Guvendik | 2eb7c43 | 2023-09-14 11:57:42 -0700 | [diff] [blame] | 335 | PCI_DID_INTEL_RPL_U_GT1, |
| 336 | PCI_DID_INTEL_RPL_U_GT2, |
| 337 | PCI_DID_INTEL_RPL_U_GT3, |
| 338 | PCI_DID_INTEL_RPL_U_GT4, |
| 339 | PCI_DID_INTEL_RPL_U_GT5, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 340 | PCI_DID_INTEL_RPL_P_GT1, |
| 341 | PCI_DID_INTEL_RPL_P_GT2, |
| 342 | PCI_DID_INTEL_RPL_P_GT3, |
zhixingma | 529a64b | 2022-06-13 15:06:27 -0700 | [diff] [blame] | 343 | PCI_DID_INTEL_RPL_P_GT4, |
| 344 | PCI_DID_INTEL_RPL_P_GT5, |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 345 | PCI_DID_INTEL_MTL_M_GT2, |
| 346 | PCI_DID_INTEL_MTL_P_GT2_1, |
| 347 | PCI_DID_INTEL_MTL_P_GT2_2, |
Wonkyu Kim | 25c2075 | 2022-07-04 20:43:47 -0700 | [diff] [blame] | 348 | PCI_DID_INTEL_MTL_P_GT2_3, |
Ravi Sarawadi | 33005df | 2022-10-11 23:54:55 -0700 | [diff] [blame] | 349 | PCI_DID_INTEL_MTL_P_GT2_4, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 350 | PCI_DID_INTEL_APL_IGD_HD_505, |
| 351 | PCI_DID_INTEL_APL_IGD_HD_500, |
| 352 | PCI_DID_INTEL_CNL_GT2_ULX_1, |
| 353 | PCI_DID_INTEL_CNL_GT2_ULX_2, |
| 354 | PCI_DID_INTEL_CNL_GT2_ULX_3, |
| 355 | PCI_DID_INTEL_CNL_GT2_ULX_4, |
| 356 | PCI_DID_INTEL_CNL_GT2_ULT_1, |
| 357 | PCI_DID_INTEL_CNL_GT2_ULT_2, |
| 358 | PCI_DID_INTEL_CNL_GT2_ULT_3, |
| 359 | PCI_DID_INTEL_CNL_GT2_ULT_4, |
| 360 | PCI_DID_INTEL_GLK_IGD, |
| 361 | PCI_DID_INTEL_GLK_IGD_EU12, |
| 362 | PCI_DID_INTEL_WHL_GT1_ULT_1, |
| 363 | PCI_DID_INTEL_WHL_GT2_ULT_1, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 364 | PCI_DID_INTEL_AML_GT2_ULX, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 365 | PCI_DID_INTEL_CFL_H_GT2, |
| 366 | PCI_DID_INTEL_CFL_H_XEON_GT2, |
| 367 | PCI_DID_INTEL_CFL_S_GT1_1, |
| 368 | PCI_DID_INTEL_CFL_S_GT1_2, |
| 369 | PCI_DID_INTEL_CFL_S_GT2_1, |
| 370 | PCI_DID_INTEL_CFL_S_GT2_2, |
| 371 | PCI_DID_INTEL_CFL_S_GT2_3, |
| 372 | PCI_DID_INTEL_CFL_S_GT2_4, |
| 373 | PCI_DID_INTEL_CFL_S_GT2_5, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 374 | PCI_DID_INTEL_CML_GT1_ULT_1, |
| 375 | PCI_DID_INTEL_CML_GT1_ULT_2, |
| 376 | PCI_DID_INTEL_CML_GT2_ULT_1, |
| 377 | PCI_DID_INTEL_CML_GT2_ULT_2, |
| 378 | PCI_DID_INTEL_CML_GT1_ULT_3, |
| 379 | PCI_DID_INTEL_CML_GT1_ULT_4, |
| 380 | PCI_DID_INTEL_CML_GT2_ULT_5, |
| 381 | PCI_DID_INTEL_CML_GT2_ULT_6, |
Michał Żygowski | 9baffae | 2022-09-29 13:29:02 +0200 | [diff] [blame] | 382 | PCI_DID_INTEL_CML_GT2_ULT_7, |
| 383 | PCI_DID_INTEL_CML_GT2_ULT_8, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 384 | PCI_DID_INTEL_CML_GT2_ULT_3, |
| 385 | PCI_DID_INTEL_CML_GT2_ULT_4, |
| 386 | PCI_DID_INTEL_CML_GT1_ULX_1, |
| 387 | PCI_DID_INTEL_CML_GT2_ULX_1, |
| 388 | PCI_DID_INTEL_CML_GT1_S_1, |
| 389 | PCI_DID_INTEL_CML_GT1_S_2, |
| 390 | PCI_DID_INTEL_CML_GT2_S_1, |
| 391 | PCI_DID_INTEL_CML_GT2_S_2, |
| 392 | PCI_DID_INTEL_CML_GT1_H_1, |
| 393 | PCI_DID_INTEL_CML_GT1_H_2, |
| 394 | PCI_DID_INTEL_CML_GT2_H_1, |
| 395 | PCI_DID_INTEL_CML_GT2_H_2, |
| 396 | PCI_DID_INTEL_CML_GT2_S_G0, |
| 397 | PCI_DID_INTEL_CML_GT2_S_P0, |
| 398 | PCI_DID_INTEL_CML_GT2_H_R0, |
| 399 | PCI_DID_INTEL_CML_GT2_H_R1, |
| 400 | PCI_DID_INTEL_TGL_GT0, |
| 401 | PCI_DID_INTEL_TGL_GT1_H_32, |
| 402 | PCI_DID_INTEL_TGL_GT1_H_16, |
| 403 | PCI_DID_INTEL_TGL_GT2_ULT, |
| 404 | PCI_DID_INTEL_TGL_GT2_ULX, |
| 405 | PCI_DID_INTEL_TGL_GT3_ULT, |
| 406 | PCI_DID_INTEL_TGL_GT2_ULT_1, |
| 407 | PCI_DID_INTEL_EHL_GT1_1, |
| 408 | PCI_DID_INTEL_EHL_GT2_1, |
| 409 | PCI_DID_INTEL_EHL_GT1_2, |
| 410 | PCI_DID_INTEL_EHL_GT2_2, |
| 411 | PCI_DID_INTEL_EHL_GT1_2_1, |
| 412 | PCI_DID_INTEL_EHL_GT1_3, |
| 413 | PCI_DID_INTEL_EHL_GT2_3, |
| 414 | PCI_DID_INTEL_JSL_GT1, |
| 415 | PCI_DID_INTEL_JSL_GT2, |
| 416 | PCI_DID_INTEL_JSL_GT3, |
| 417 | PCI_DID_INTEL_JSL_GT4, |
| 418 | PCI_DID_INTEL_ADL_GT0, |
| 419 | PCI_DID_INTEL_ADL_GT1, |
| 420 | PCI_DID_INTEL_ADL_GT1_1, |
| 421 | PCI_DID_INTEL_ADL_GT1_2, |
| 422 | PCI_DID_INTEL_ADL_GT1_3, |
| 423 | PCI_DID_INTEL_ADL_GT1_4, |
| 424 | PCI_DID_INTEL_ADL_GT1_5, |
| 425 | PCI_DID_INTEL_ADL_GT1_6, |
| 426 | PCI_DID_INTEL_ADL_GT1_7, |
| 427 | PCI_DID_INTEL_ADL_GT1_8, |
| 428 | PCI_DID_INTEL_ADL_GT1_9, |
| 429 | PCI_DID_INTEL_ADL_P_GT2, |
| 430 | PCI_DID_INTEL_ADL_P_GT2_1, |
| 431 | PCI_DID_INTEL_ADL_P_GT2_2, |
| 432 | PCI_DID_INTEL_ADL_P_GT2_3, |
| 433 | PCI_DID_INTEL_ADL_P_GT2_4, |
| 434 | PCI_DID_INTEL_ADL_P_GT2_5, |
| 435 | PCI_DID_INTEL_ADL_P_GT2_6, |
| 436 | PCI_DID_INTEL_ADL_P_GT2_7, |
| 437 | PCI_DID_INTEL_ADL_P_GT2_8, |
| 438 | PCI_DID_INTEL_ADL_P_GT2_9, |
| 439 | PCI_DID_INTEL_ADL_S_GT1, |
Michał Żygowski | 84ceee9 | 2022-11-29 10:47:05 +0100 | [diff] [blame] | 440 | PCI_DID_INTEL_ADL_S_GT1_1, |
| 441 | PCI_DID_INTEL_ADL_S_GT2, |
| 442 | PCI_DID_INTEL_ADL_S_GT2_1, |
| 443 | PCI_DID_INTEL_ADL_S_GT2_2, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 444 | PCI_DID_INTEL_ADL_M_GT1, |
| 445 | PCI_DID_INTEL_ADL_M_GT2, |
| 446 | PCI_DID_INTEL_ADL_M_GT3, |
| 447 | PCI_DID_INTEL_ADL_N_GT1, |
| 448 | PCI_DID_INTEL_ADL_N_GT2, |
| 449 | PCI_DID_INTEL_ADL_N_GT3, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 450 | PCI_DID_INTEL_RPL_S_GT0, |
| 451 | PCI_DID_INTEL_RPL_S_GT1_1, |
| 452 | PCI_DID_INTEL_RPL_S_GT1_2, |
| 453 | PCI_DID_INTEL_RPL_S_GT1_3, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 454 | PCI_DID_INTEL_RPL_HX_GT1, |
| 455 | PCI_DID_INTEL_RPL_HX_GT2, |
| 456 | PCI_DID_INTEL_RPL_HX_GT3, |
| 457 | PCI_DID_INTEL_RPL_HX_GT4, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 458 | 0, |
| 459 | }; |
| 460 | |
| 461 | static const struct pci_driver graphics_driver __pci_driver = { |
| 462 | .ops = &graphics_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 463 | .vendor = PCI_VID_INTEL, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 464 | .devices = pci_device_ids, |
| 465 | }; |