soc/intel/gma: Move DDI-A 4-lane config to common code
Change-Id: I0572dbbfb61e5e0129fe6a3a1b5894145d74fd0d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40728
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index ba4bc85..e2c9060 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi.h>
#include <assert.h>
#include <bootmode.h>
#include <console/console.h>
@@ -34,6 +35,13 @@
/* SoC specific configuration. */
graphics_soc_init(dev);
+ if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) {
+ const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
+ /* Only program if the buffer is not enabled yet. */
+ if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE))
+ graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES);
+ }
+
/*
* GFX PEIM module inside FSP binary is taking care of graphics
* initialization based on RUN_FSP_GOP Kconfig option and input