soc/intel/skylake: Assign device ops in chipset devicetree

Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.

In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
    device pci 00.0 alias system_agent on
            ops systemagent_ops
    end

Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.

Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 6b5770c..30fc2c2 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -175,7 +175,7 @@
 	}
 }
 
-static const struct device_operations graphics_ops = {
+const struct device_operations graphics_ops = {
 	.read_resources		= graphics_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
@@ -213,36 +213,7 @@
 	PCI_DID_INTEL_GLK_IGD_EU12,
 	PCI_DID_INTEL_WHL_GT1_ULT_1,
 	PCI_DID_INTEL_WHL_GT2_ULT_1,
-	PCI_DID_INTEL_KBL_GT1_SULTM,
-	PCI_DID_INTEL_KBL_GT1_SHALM_1,
-	PCI_DID_INTEL_KBL_GT1_SHALM_2,
-	PCI_DID_INTEL_KBL_GT1_SSRVM,
-	PCI_DID_INTEL_KBL_GT1F_DT2,
-	PCI_DID_INTEL_KBL_GT2_SULXM,
-	PCI_DID_INTEL_KBL_GT2_SULTM,
-	PCI_DID_INTEL_KBL_GT2_SULTMR,
-	PCI_DID_INTEL_KBL_GT2_SSRVM,
-	PCI_DID_INTEL_KBL_GT2_SWSTM,
-	PCI_DID_INTEL_KBL_GT2_SHALM,
-	PCI_DID_INTEL_KBL_GT2_DT2P2,
-	PCI_DID_INTEL_KBL_GT2F_SULTM,
-	PCI_DID_INTEL_KBL_GT3E_SULTM_1,
-	PCI_DID_INTEL_KBL_GT3E_SULTM_2,
-	PCI_DID_INTEL_KBL_GT4_SHALM,
 	PCI_DID_INTEL_AML_GT2_ULX,
-	PCI_DID_INTEL_SKL_GT1F_DT2,
-	PCI_DID_INTEL_SKL_GT1_SULTM,
-	PCI_DID_INTEL_SKL_GT2_DT2P1,
-	PCI_DID_INTEL_SKL_GT2_SULXM,
-	PCI_DID_INTEL_SKL_GT2_SULTM,
-	PCI_DID_INTEL_SKL_GT2_SHALM,
-	PCI_DID_INTEL_SKL_GT2_SWKSM,
-	PCI_DID_INTEL_SKL_GT3_SULTM,
-	PCI_DID_INTEL_SKL_GT3E_SULTM_1,
-	PCI_DID_INTEL_SKL_GT3E_SULTM_2,
-	PCI_DID_INTEL_SKL_GT3FE_SSRVM,
-	PCI_DID_INTEL_SKL_GT4_SHALM,
-	PCI_DID_INTEL_SKL_GT4E_SWSTM,
 	PCI_DID_INTEL_CFL_H_GT2,
 	PCI_DID_INTEL_CFL_H_XEON_GT2,
 	PCI_DID_INTEL_CFL_S_GT1_1,