Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 2 | |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
John Zhao | eac84ca | 2018-08-13 09:45:37 -0700 | [diff] [blame] | 4 | #include <assert.h> |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 5 | #include <bootmode.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 6 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 8 | #include <device/pci.h> |
| 9 | #include <device/pci_ids.h> |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 10 | #include <drivers/intel/gma/i915.h> |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 11 | #include <drivers/intel/gma/libgfxinit.h> |
| 12 | #include <drivers/intel/gma/opregion.h> |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 13 | #include <intelblocks/cfg.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 14 | #include <intelblocks/graphics.h> |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 15 | #include <fsp/graphics.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Nico Huber | bd4af10 | 2020-04-26 20:43:42 +0200 | [diff] [blame] | 17 | #include <types.h> |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 18 | |
| 19 | /* SoC Overrides */ |
Matt DeVillier | 395ab9d | 2020-12-23 17:30:27 -0600 | [diff] [blame] | 20 | __weak void graphics_soc_panel_init(struct device *dev) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 21 | { |
| 22 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 23 | * User needs to implement SoC override in case wishes |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 24 | * to perform certain specific graphics initialization |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 25 | */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 26 | } |
| 27 | |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 28 | __weak const struct i915_gpu_controller_info * |
Furquan Shaikh | ec3dafd | 2020-04-24 21:53:42 -0700 | [diff] [blame] | 29 | intel_igd_get_controller_info(const struct device *device) |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 30 | { |
| 31 | return NULL; |
| 32 | } |
| 33 | |
Subrata Banik | 1e58a16 | 2023-09-22 15:49:04 +0000 | [diff] [blame^] | 34 | /* |
| 35 | * Transcoders contain the timing generators for eDP, DP, and HDMI interfaces. |
| 36 | * Intel transcoders are based on Quick Sync Video, which offloads video |
| 37 | * encoding and decoding tasks from the CPU to the GPU. |
| 38 | * |
| 39 | * On Intel silicon, there are four display pipes (DDI-A to DDI-D) that support |
| 40 | * blending, color adjustments, scaling, and dithering. |
| 41 | * |
| 42 | * From the display block diagram perspective, the front end of the display |
| 43 | * contains the pipes. The pipes connect to the transcoder. The transcoder |
| 44 | * (except for wireless) connects to the DDIs to drive the IO/PHY. |
| 45 | * |
| 46 | * This logic checks if the DDI-A port is attached to the transcoder and |
| 47 | * enabled (bit 27). Traditionally, the on-board display (eDP) is attached to DDI-A. |
| 48 | * If the above conditions is met, then the on-board display is present and enabled. |
| 49 | * |
| 50 | * On platforms without an on-board display (i.e., value at bits 27-30 is between 2-9), |
| 51 | * meaning that DDI-A (eDP) is not enabled. |
| 52 | * |
| 53 | * Additionally, if bits 27-30 are all set to 0, this means that no DDI ports |
| 54 | * are enabled, and there is no display. |
| 55 | * |
| 56 | * Consider external display is present and enabled, if eDP/DDI-A is not enabled |
| 57 | * and transcoder is attached to any DDI port (bits 27-30 are not zero). |
| 58 | */ |
| 59 | static int get_external_display_status(void) |
| 60 | { |
| 61 | uint32_t ddi_func_ctrl = graphics_gtt_read(TRANS_DDI_FUNC_CTL_A); |
| 62 | ddi_func_ctrl &= TRANS_DDI_PORT_MASK; |
| 63 | |
| 64 | /* |
| 65 | * Check if transcoder is none or connected to DDI-A port (aka eDP). |
| 66 | * Report no external display in both cases. |
| 67 | */ |
| 68 | if (ddi_func_ctrl == TRANS_DDI_PORT_NONE) { |
| 69 | return 0; |
| 70 | } else { |
| 71 | if (ddi_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A)) |
| 72 | return 0; |
| 73 | else |
| 74 | return 1; |
| 75 | } |
| 76 | } |
| 77 | |
| 78 | /* Check and report if an external display is attached */ |
| 79 | int fsp_soc_report_external_display(void) |
| 80 | { |
| 81 | return graphics_get_framebuffer_address() && get_external_display_status(); |
| 82 | } |
| 83 | |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 84 | static void gma_init(struct device *const dev) |
| 85 | { |
| 86 | intel_gma_init_igd_opregion(); |
| 87 | |
Matt DeVillier | 395ab9d | 2020-12-23 17:30:27 -0600 | [diff] [blame] | 88 | /* SoC specific panel init/configuration. |
| 89 | If FSP has already run/configured the IGD, we can assume the |
| 90 | panel/backlight control have already been set up sufficiently |
| 91 | and that we shouldn't attempt to reconfigure things. */ |
| 92 | if (!CONFIG(RUN_FSP_GOP)) |
| 93 | graphics_soc_panel_init(dev); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 94 | |
Nico Huber | dd274e2 | 2020-04-26 20:37:32 +0200 | [diff] [blame] | 95 | if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) { |
| 96 | const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A); |
| 97 | /* Only program if the buffer is not enabled yet. */ |
| 98 | if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE)) |
| 99 | graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES); |
| 100 | } |
| 101 | |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 102 | /* |
| 103 | * GFX PEIM module inside FSP binary is taking care of graphics |
| 104 | * initialization based on RUN_FSP_GOP Kconfig option and input |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 105 | * VBT file. Need to report the framebuffer info after PCI enumeration. |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 106 | * |
| 107 | * In case of non-FSP solution, SoC need to select another |
| 108 | * Kconfig to perform GFX initialization. |
| 109 | */ |
Subrata Banik | be0590c | 2023-02-14 18:44:09 +0530 | [diff] [blame] | 110 | if (CONFIG(RUN_FSP_GOP) && display_init_required()) { |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 111 | const struct soc_intel_common_config *config = chip_get_common_soc_structure(); |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 112 | fsp_report_framebuffer_info(graphics_get_framebuffer_address(), |
Tim Wawrzynczak | 84428f7 | 2021-09-14 13:59:33 -0600 | [diff] [blame] | 113 | config->panel_orientation); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 114 | return; |
Patrick Rudolph | 92106b1 | 2020-02-19 12:54:06 +0100 | [diff] [blame] | 115 | } |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 116 | |
Nico Huber | dd59762 | 2020-04-26 19:46:35 +0200 | [diff] [blame] | 117 | if (!CONFIG(NO_GFX_INIT)) |
| 118 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 119 | |
| 120 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) { |
| 121 | if (!acpi_is_wakeup_s3() && display_init_required()) { |
| 122 | int lightup_ok; |
| 123 | gma_gfxinit(&lightup_ok); |
| 124 | gfx_set_init_done(lightup_ok); |
| 125 | } |
| 126 | } else { |
| 127 | /* Initialize PCI device, load/execute BIOS Option ROM */ |
| 128 | pci_dev_init(dev); |
| 129 | } |
| 130 | } |
| 131 | |
Furquan Shaikh | 7536a39 | 2020-04-24 21:59:21 -0700 | [diff] [blame] | 132 | static void gma_generate_ssdt(const struct device *device) |
Matt DeVillier | 1eea1dd | 2019-05-02 13:30:11 -0700 | [diff] [blame] | 133 | { |
| 134 | const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device); |
| 135 | |
| 136 | if (gfx) |
| 137 | drivers_intel_gma_displays_ssdt_generate(gfx); |
| 138 | } |
| 139 | |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 140 | static int is_graphics_disabled(struct device *dev) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 141 | { |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 142 | /* Check if Graphics PCI device is disabled */ |
John Zhao | eac84ca | 2018-08-13 09:45:37 -0700 | [diff] [blame] | 143 | if (!dev || !dev->enabled) |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 144 | return 1; |
| 145 | |
| 146 | return 0; |
| 147 | } |
| 148 | |
| 149 | static uintptr_t graphics_get_bar(struct device *dev, unsigned long index) |
| 150 | { |
| 151 | struct resource *gm_res; |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 152 | |
Angel Pons | c1bfbe0 | 2021-11-03 13:18:53 +0100 | [diff] [blame] | 153 | gm_res = probe_resource(dev, index); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 154 | if (!gm_res) |
| 155 | return 0; |
| 156 | |
| 157 | return gm_res->base; |
| 158 | } |
| 159 | |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 160 | uintptr_t graphics_get_framebuffer_address(void) |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 161 | { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 162 | uintptr_t memory_base; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 163 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 164 | |
| 165 | if (is_graphics_disabled(dev)) |
| 166 | return 0; |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 167 | |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 168 | memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 169 | if (!memory_base) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 170 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Ethan Tsao | 646b6a0 | 2022-01-25 15:14:38 -0800 | [diff] [blame] | 171 | "Graphic memory bar2 is not programmed!"); |
| 172 | |
| 173 | memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET; |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 174 | |
| 175 | return memory_base; |
| 176 | } |
| 177 | |
| 178 | static uintptr_t graphics_get_gtt_base(void) |
| 179 | { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 180 | static uintptr_t gtt_base; |
Kyösti Mälkki | 71756c21 | 2019-07-12 13:10:19 +0300 | [diff] [blame] | 181 | struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 182 | |
| 183 | if (is_graphics_disabled(dev)) |
| 184 | die("IGD is disabled!"); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 185 | /* |
| 186 | * GFX PCI config space offset 0x10 know as Graphics |
| 187 | * Translation Table Memory Mapped Range Address |
| 188 | * (GTTMMADR) |
| 189 | */ |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 190 | if (!gtt_base) { |
Subrata Banik | 64e6680 | 2019-06-13 22:11:46 +0530 | [diff] [blame] | 191 | gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 192 | if (!gtt_base) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 193 | die_with_post_code(POSTCODE_HW_INIT_FAILURE, |
Keith Short | 15588b0 | 2019-05-09 11:40:34 -0600 | [diff] [blame] | 194 | "GTTMMADR is not programmed!"); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 195 | } |
| 196 | return gtt_base; |
| 197 | } |
| 198 | |
| 199 | uint32_t graphics_gtt_read(unsigned long reg) |
| 200 | { |
Elyes Haouas | c4fbeac | 2022-12-04 16:06:02 +0100 | [diff] [blame] | 201 | return read32p(graphics_get_gtt_base() + reg); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 202 | } |
| 203 | |
| 204 | void graphics_gtt_write(unsigned long reg, uint32_t data) |
| 205 | { |
Elyes Haouas | c4fbeac | 2022-12-04 16:06:02 +0100 | [diff] [blame] | 206 | write32p(graphics_get_gtt_base() + reg, data); |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask) |
| 210 | { |
| 211 | uint32_t val = graphics_gtt_read(reg); |
| 212 | val &= andmask; |
| 213 | val |= ormask; |
| 214 | graphics_gtt_write(reg, val); |
| 215 | } |
| 216 | |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 217 | static void graphics_dev_read_resources(struct device *dev) |
| 218 | { |
| 219 | pci_dev_read_resources(dev); |
| 220 | |
| 221 | if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) { |
| 222 | struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 223 | if (res_bar0->flags & IORESOURCE_PREFETCH) |
| 224 | res_bar0->flags &= ~IORESOURCE_PREFETCH; |
| 225 | } |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 226 | |
| 227 | /* |
| 228 | * If libhwbase static MMIO driver is used, IGD BAR 0 has to be set to |
| 229 | * CONFIG_GFX_GMA_DEFAULT_MMIO for the libgfxinit to operate properly. |
| 230 | */ |
| 231 | if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && CONFIG(HWBASE_STATIC_MMIO)) { |
| 232 | struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 233 | res_bar0->base = CONFIG_GFX_GMA_DEFAULT_MMIO; |
| 234 | res_bar0->flags |= IORESOURCE_ASSIGNED; |
| 235 | pci_dev_set_resources(dev); |
| 236 | res_bar0->flags |= IORESOURCE_FIXED; |
| 237 | } |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 238 | } |
| 239 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 240 | const struct device_operations graphics_ops = { |
Wonkyu Kim | 91bd6e1 | 2022-08-03 12:47:06 -0700 | [diff] [blame] | 241 | .read_resources = graphics_dev_read_resources, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 242 | .set_resources = pci_dev_set_resources, |
| 243 | .enable_resources = pci_dev_enable_resources, |
Nico Huber | 826094f | 2020-04-26 19:24:00 +0200 | [diff] [blame] | 244 | .init = gma_init, |
Subrata Banik | 25d01be | 2022-09-01 16:39:36 +0530 | [diff] [blame] | 245 | .final = pci_dev_request_bus_master, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 246 | .ops_pci = &pci_dev_ops_pci, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 247 | #if CONFIG(HAVE_ACPI_TABLES) |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 248 | .acpi_fill_ssdt = gma_generate_ssdt, |
Karthikeyan Ramasubramanian | 0e971e1 | 2020-01-09 11:32:16 -0700 | [diff] [blame] | 249 | #endif |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 250 | .scan_bus = scan_generic_bus, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 251 | }; |
| 252 | |
| 253 | static const unsigned short pci_device_ids[] = { |
Bora Guvendik | 2eb7c43 | 2023-09-14 11:57:42 -0700 | [diff] [blame] | 254 | PCI_DID_INTEL_RPL_U_GT1, |
| 255 | PCI_DID_INTEL_RPL_U_GT2, |
| 256 | PCI_DID_INTEL_RPL_U_GT3, |
| 257 | PCI_DID_INTEL_RPL_U_GT4, |
| 258 | PCI_DID_INTEL_RPL_U_GT5, |
Bora Guvendik | a15b25f | 2022-02-28 14:43:49 -0800 | [diff] [blame] | 259 | PCI_DID_INTEL_RPL_P_GT1, |
| 260 | PCI_DID_INTEL_RPL_P_GT2, |
| 261 | PCI_DID_INTEL_RPL_P_GT3, |
zhixingma | 529a64b | 2022-06-13 15:06:27 -0700 | [diff] [blame] | 262 | PCI_DID_INTEL_RPL_P_GT4, |
| 263 | PCI_DID_INTEL_RPL_P_GT5, |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 264 | PCI_DID_INTEL_MTL_M_GT2, |
| 265 | PCI_DID_INTEL_MTL_P_GT2_1, |
| 266 | PCI_DID_INTEL_MTL_P_GT2_2, |
Wonkyu Kim | 25c2075 | 2022-07-04 20:43:47 -0700 | [diff] [blame] | 267 | PCI_DID_INTEL_MTL_P_GT2_3, |
Ravi Sarawadi | 33005df | 2022-10-11 23:54:55 -0700 | [diff] [blame] | 268 | PCI_DID_INTEL_MTL_P_GT2_4, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 269 | PCI_DID_INTEL_APL_IGD_HD_505, |
| 270 | PCI_DID_INTEL_APL_IGD_HD_500, |
| 271 | PCI_DID_INTEL_CNL_GT2_ULX_1, |
| 272 | PCI_DID_INTEL_CNL_GT2_ULX_2, |
| 273 | PCI_DID_INTEL_CNL_GT2_ULX_3, |
| 274 | PCI_DID_INTEL_CNL_GT2_ULX_4, |
| 275 | PCI_DID_INTEL_CNL_GT2_ULT_1, |
| 276 | PCI_DID_INTEL_CNL_GT2_ULT_2, |
| 277 | PCI_DID_INTEL_CNL_GT2_ULT_3, |
| 278 | PCI_DID_INTEL_CNL_GT2_ULT_4, |
| 279 | PCI_DID_INTEL_GLK_IGD, |
| 280 | PCI_DID_INTEL_GLK_IGD_EU12, |
| 281 | PCI_DID_INTEL_WHL_GT1_ULT_1, |
| 282 | PCI_DID_INTEL_WHL_GT2_ULT_1, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 283 | PCI_DID_INTEL_AML_GT2_ULX, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 284 | PCI_DID_INTEL_CFL_H_GT2, |
| 285 | PCI_DID_INTEL_CFL_H_XEON_GT2, |
| 286 | PCI_DID_INTEL_CFL_S_GT1_1, |
| 287 | PCI_DID_INTEL_CFL_S_GT1_2, |
| 288 | PCI_DID_INTEL_CFL_S_GT2_1, |
| 289 | PCI_DID_INTEL_CFL_S_GT2_2, |
| 290 | PCI_DID_INTEL_CFL_S_GT2_3, |
| 291 | PCI_DID_INTEL_CFL_S_GT2_4, |
| 292 | PCI_DID_INTEL_CFL_S_GT2_5, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 293 | PCI_DID_INTEL_CML_GT1_ULT_1, |
| 294 | PCI_DID_INTEL_CML_GT1_ULT_2, |
| 295 | PCI_DID_INTEL_CML_GT2_ULT_1, |
| 296 | PCI_DID_INTEL_CML_GT2_ULT_2, |
| 297 | PCI_DID_INTEL_CML_GT1_ULT_3, |
| 298 | PCI_DID_INTEL_CML_GT1_ULT_4, |
| 299 | PCI_DID_INTEL_CML_GT2_ULT_5, |
| 300 | PCI_DID_INTEL_CML_GT2_ULT_6, |
Michał Żygowski | 9baffae | 2022-09-29 13:29:02 +0200 | [diff] [blame] | 301 | PCI_DID_INTEL_CML_GT2_ULT_7, |
| 302 | PCI_DID_INTEL_CML_GT2_ULT_8, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 303 | PCI_DID_INTEL_CML_GT2_ULT_3, |
| 304 | PCI_DID_INTEL_CML_GT2_ULT_4, |
| 305 | PCI_DID_INTEL_CML_GT1_ULX_1, |
| 306 | PCI_DID_INTEL_CML_GT2_ULX_1, |
| 307 | PCI_DID_INTEL_CML_GT1_S_1, |
| 308 | PCI_DID_INTEL_CML_GT1_S_2, |
| 309 | PCI_DID_INTEL_CML_GT2_S_1, |
| 310 | PCI_DID_INTEL_CML_GT2_S_2, |
| 311 | PCI_DID_INTEL_CML_GT1_H_1, |
| 312 | PCI_DID_INTEL_CML_GT1_H_2, |
| 313 | PCI_DID_INTEL_CML_GT2_H_1, |
| 314 | PCI_DID_INTEL_CML_GT2_H_2, |
| 315 | PCI_DID_INTEL_CML_GT2_S_G0, |
| 316 | PCI_DID_INTEL_CML_GT2_S_P0, |
| 317 | PCI_DID_INTEL_CML_GT2_H_R0, |
| 318 | PCI_DID_INTEL_CML_GT2_H_R1, |
| 319 | PCI_DID_INTEL_TGL_GT0, |
| 320 | PCI_DID_INTEL_TGL_GT1_H_32, |
| 321 | PCI_DID_INTEL_TGL_GT1_H_16, |
| 322 | PCI_DID_INTEL_TGL_GT2_ULT, |
| 323 | PCI_DID_INTEL_TGL_GT2_ULX, |
| 324 | PCI_DID_INTEL_TGL_GT3_ULT, |
| 325 | PCI_DID_INTEL_TGL_GT2_ULT_1, |
| 326 | PCI_DID_INTEL_EHL_GT1_1, |
| 327 | PCI_DID_INTEL_EHL_GT2_1, |
| 328 | PCI_DID_INTEL_EHL_GT1_2, |
| 329 | PCI_DID_INTEL_EHL_GT2_2, |
| 330 | PCI_DID_INTEL_EHL_GT1_2_1, |
| 331 | PCI_DID_INTEL_EHL_GT1_3, |
| 332 | PCI_DID_INTEL_EHL_GT2_3, |
| 333 | PCI_DID_INTEL_JSL_GT1, |
| 334 | PCI_DID_INTEL_JSL_GT2, |
| 335 | PCI_DID_INTEL_JSL_GT3, |
| 336 | PCI_DID_INTEL_JSL_GT4, |
| 337 | PCI_DID_INTEL_ADL_GT0, |
| 338 | PCI_DID_INTEL_ADL_GT1, |
| 339 | PCI_DID_INTEL_ADL_GT1_1, |
| 340 | PCI_DID_INTEL_ADL_GT1_2, |
| 341 | PCI_DID_INTEL_ADL_GT1_3, |
| 342 | PCI_DID_INTEL_ADL_GT1_4, |
| 343 | PCI_DID_INTEL_ADL_GT1_5, |
| 344 | PCI_DID_INTEL_ADL_GT1_6, |
| 345 | PCI_DID_INTEL_ADL_GT1_7, |
| 346 | PCI_DID_INTEL_ADL_GT1_8, |
| 347 | PCI_DID_INTEL_ADL_GT1_9, |
| 348 | PCI_DID_INTEL_ADL_P_GT2, |
| 349 | PCI_DID_INTEL_ADL_P_GT2_1, |
| 350 | PCI_DID_INTEL_ADL_P_GT2_2, |
| 351 | PCI_DID_INTEL_ADL_P_GT2_3, |
| 352 | PCI_DID_INTEL_ADL_P_GT2_4, |
| 353 | PCI_DID_INTEL_ADL_P_GT2_5, |
| 354 | PCI_DID_INTEL_ADL_P_GT2_6, |
| 355 | PCI_DID_INTEL_ADL_P_GT2_7, |
| 356 | PCI_DID_INTEL_ADL_P_GT2_8, |
| 357 | PCI_DID_INTEL_ADL_P_GT2_9, |
| 358 | PCI_DID_INTEL_ADL_S_GT1, |
Michał Żygowski | 84ceee9 | 2022-11-29 10:47:05 +0100 | [diff] [blame] | 359 | PCI_DID_INTEL_ADL_S_GT1_1, |
| 360 | PCI_DID_INTEL_ADL_S_GT2, |
| 361 | PCI_DID_INTEL_ADL_S_GT2_1, |
| 362 | PCI_DID_INTEL_ADL_S_GT2_2, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 363 | PCI_DID_INTEL_ADL_M_GT1, |
| 364 | PCI_DID_INTEL_ADL_M_GT2, |
| 365 | PCI_DID_INTEL_ADL_M_GT3, |
| 366 | PCI_DID_INTEL_ADL_N_GT1, |
| 367 | PCI_DID_INTEL_ADL_N_GT2, |
| 368 | PCI_DID_INTEL_ADL_N_GT3, |
Max Fritz | 573e6de | 2022-11-19 01:54:44 +0100 | [diff] [blame] | 369 | PCI_DID_INTEL_RPL_S_GT0, |
| 370 | PCI_DID_INTEL_RPL_S_GT1_1, |
| 371 | PCI_DID_INTEL_RPL_S_GT1_2, |
| 372 | PCI_DID_INTEL_RPL_S_GT1_3, |
Tim Crawford | 53c6eea | 2023-07-07 09:59:56 -0600 | [diff] [blame] | 373 | PCI_DID_INTEL_RPL_HX_GT1, |
| 374 | PCI_DID_INTEL_RPL_HX_GT2, |
| 375 | PCI_DID_INTEL_RPL_HX_GT3, |
| 376 | PCI_DID_INTEL_RPL_HX_GT4, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 377 | 0, |
| 378 | }; |
| 379 | |
| 380 | static const struct pci_driver graphics_driver __pci_driver = { |
| 381 | .ops = &graphics_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 382 | .vendor = PCI_VID_INTEL, |
Subrata Banik | fa7cc78 | 2017-11-27 18:23:36 +0530 | [diff] [blame] | 383 | .devices = pci_device_ids, |
| 384 | }; |