soc/intel/graphics: Repurpose graphics_get_memory_base()
create SOC_INTEL_GFX_MEMBASE_OFFSET for platform to map graphic memory
base if required, because it may vary by platfrom.
BUG=b:216756721
TEST= Check default offset for existing platform and
update platform specific offset in Kconfig under SoC directory.
Change-Id: I6b1e34ada9b895dabcdc8116d2470e8831ed0a9e
Signed-off-by: Ethan Tsao <ethan.tsao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61389
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 4b0b4c4..6118f99 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -59,7 +59,7 @@
*/
if (CONFIG(RUN_FSP_GOP)) {
const struct soc_intel_common_config *config = chip_get_common_soc_structure();
- fsp_report_framebuffer_info(graphics_get_memory_base(),
+ fsp_report_framebuffer_info(graphics_get_framebuffer_address(),
config->panel_orientation);
return;
}
@@ -107,21 +107,20 @@
return gm_res->base;
}
-uintptr_t graphics_get_memory_base(void)
+uintptr_t graphics_get_framebuffer_address(void)
{
uintptr_t memory_base;
struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (is_graphics_disabled(dev))
return 0;
- /*
- * GFX PCI config space offset 0x18 know as Graphics
- * Memory Range Address (GMADR)
- */
+
memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
if (!memory_base)
die_with_post_code(POST_HW_INIT_FAILURE,
- "GMADR is not programmed!");
+ "Graphic memory bar2 is not programmed!");
+
+ memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
return memory_base;
}