Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 17 | #include <assert.h> |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 18 | #include <stdint.h> |
| 19 | #include <arch/io.h> |
| 20 | #include <arch/cpu.h> |
| 21 | #include <console/console.h> |
| 22 | #include <commonlib/helpers.h> |
| 23 | #include <delay.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 25 | #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX) |
| 26 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 27 | #else |
| 28 | #include <southbridge/intel/i82801jx/i82801jx.h> |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 29 | #endif |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 30 | #include <string.h> |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 31 | #include "iomap.h" |
| 32 | #include "x4x.h" |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 33 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 34 | #define ME_UMA_SIZEMB 0 |
| 35 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 36 | u32 fsb2mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 37 | { |
| 38 | return (speed * 267) + 800; |
| 39 | } |
| 40 | |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 41 | u32 ddr2mhz(u32 speed) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 42 | { |
| 43 | static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; |
| 44 | |
| 45 | if (speed >= ARRAY_SIZE(mhz)) |
| 46 | return 0; |
| 47 | |
| 48 | return mhz[speed]; |
| 49 | } |
| 50 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 51 | static void clkcross_ddr2(struct sysinfo *s) |
| 52 | { |
| 53 | u8 i, j; |
| 54 | MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); |
| 55 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 56 | static const u32 clkxtab[6][3][13] = { |
Arthur Heymans | 8a3514d | 2016-10-27 23:56:08 +0200 | [diff] [blame] | 57 | /* MEMCLK 400 N/A */ |
| 58 | {{}, {}, {} }, |
| 59 | /* MEMCLK 533 N/A */ |
| 60 | {{}, {}, {} }, |
| 61 | /* MEMCLK 667 |
| 62 | * FSB 800 */ |
| 63 | {{0x1f1f1f1f, 0x1a07070b, 0x00000000, 0x10000000, |
| 64 | 0x20010208, 0x04080000, 0x10010002, 0x00000000, |
| 65 | 0x00000000, 0x02000000, 0x04000100, 0x08000000, |
| 66 | 0x10200204}, |
| 67 | /* FSB 1067 */ |
| 68 | {0x6d5b1f1f, 0x0f0f0f0f, 0x00000000, 0x20000000, |
| 69 | 0x80020410, 0x02040008, 0x10000100, 0x00000000, |
| 70 | 0x00000000, 0x04000000, 0x08000102, 0x20000000, |
| 71 | 0x40010208}, |
| 72 | /* FSB 1333 */ |
| 73 | {0x05050303, 0xffffffff, 0xffff0000, 0x00000000, |
| 74 | 0x08020000, 0x00000000, 0x00020001, 0x00000000, |
| 75 | 0x00000000, 0x00000000, 0x08010204, 0x00000000, |
| 76 | 0x04010000} }, |
| 77 | /* MEMCLK 800 |
| 78 | * FSB 800 */ |
| 79 | {{0xffffffff, 0x05030305, 0x0000ffff, 0x0000000, |
| 80 | 0x08010204, 0x00000000, 0x08010204, 0x0000000, |
| 81 | 0x00000000, 0x00000000, 0x00020001, 0x0000000, |
| 82 | 0x04080102}, |
| 83 | /* FSB 1067 */ |
| 84 | {0x07070707, 0x06030303, 0x00000000, 0x00000000, |
| 85 | 0x08010200, 0x00000000, 0x04000102, 0x00000000, |
| 86 | 0x00000000, 0x00000000, 0x00020001, 0x00000000, |
| 87 | 0x02040801}, |
| 88 | /* FSB 1333 */ |
| 89 | {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x00000000, |
| 90 | 0x10020400, 0x02000000, 0x00040100, 0x00000000, |
| 91 | 0x00000000, 0x04080000, 0x00100102, 0x00000000, |
| 92 | 0x08100200} }, |
| 93 | /* MEMCLK 1067 */ |
| 94 | {{}, |
| 95 | /* FSB 1067 */ |
| 96 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 97 | 0x04080102, 0x00000000, 0x08010204, 0x00000000, |
| 98 | 0x00000000, 0x00000000, 0x00020001, 0x00000000, |
| 99 | 0x02040801}, |
| 100 | /* FSB 1333 */ |
| 101 | {0x0f0f0f0f, 0x5b1f1f6d, 0x00000000, 0x00000000, |
| 102 | 0x08010204, 0x04000000, 0x00080102, 0x00000000, |
| 103 | 0x00000000, 0x02000408, 0x00100001, 0x00000000, |
| 104 | 0x04080102} }, |
| 105 | /* MEMCLK 1333 */ |
| 106 | {{}, {}, |
| 107 | /* FSB 1333 */ |
| 108 | {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000, |
| 109 | 0x04080102, 0x00000000, 0x04080102, 0x00000000, |
| 110 | 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 111 | 0x02040801} } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 112 | }; |
| 113 | |
| 114 | i = (u8)s->selected_timings.mem_clk; |
| 115 | j = (u8)s->selected_timings.fsb_clk; |
| 116 | |
| 117 | MCHBAR32(0xc04) = clkxtab[i][j][0]; |
| 118 | MCHBAR32(0xc50) = clkxtab[i][j][1]; |
| 119 | MCHBAR32(0xc54) = clkxtab[i][j][2]; |
| 120 | MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7); |
| 121 | MCHBAR32(0x6d8) = clkxtab[i][j][3]; |
| 122 | MCHBAR32(0x6e0) = clkxtab[i][j][3]; |
| 123 | MCHBAR32(0x6dc) = clkxtab[i][j][4]; |
| 124 | MCHBAR32(0x6e4) = clkxtab[i][j][4]; |
| 125 | MCHBAR32(0x6e8) = clkxtab[i][j][5]; |
| 126 | MCHBAR32(0x6f0) = clkxtab[i][j][5]; |
| 127 | MCHBAR32(0x6ec) = clkxtab[i][j][6]; |
| 128 | MCHBAR32(0x6f4) = clkxtab[i][j][6]; |
| 129 | MCHBAR32(0x6f8) = clkxtab[i][j][7]; |
| 130 | MCHBAR32(0x6fc) = clkxtab[i][j][8]; |
| 131 | MCHBAR32(0x708) = clkxtab[i][j][11]; |
| 132 | MCHBAR32(0x70c) = clkxtab[i][j][12]; |
| 133 | } |
| 134 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 135 | static void setioclk_ddr2(struct sysinfo *s) |
| 136 | { |
| 137 | MCHBAR32(0x1bc) = 0x08060402; |
| 138 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200; |
| 139 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100; |
| 140 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20; |
| 141 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1; |
| 142 | switch (s->selected_timings.mem_clk) { |
| 143 | default: |
| 144 | case MEM_CLOCK_800MHz: |
| 145 | case MEM_CLOCK_1066MHz: |
| 146 | MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2; |
| 147 | MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2; |
| 148 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0; |
| 149 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0; |
| 150 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0; |
| 151 | break; |
| 152 | case MEM_CLOCK_667MHz: |
| 153 | case MEM_CLOCK_1333MHz: |
| 154 | MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; |
| 155 | MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2; |
| 156 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40; |
| 157 | break; |
| 158 | } |
| 159 | MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31); |
| 160 | MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31); |
| 161 | } |
| 162 | |
| 163 | static void launch_ddr2(struct sysinfo *s) |
| 164 | { |
| 165 | u8 i; |
| 166 | u32 launch1 = 0x58001117; |
| 167 | u32 launch2 = 0; |
| 168 | u32 launch3 = 0; |
| 169 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 170 | if (s->selected_timings.CAS == 5) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 171 | launch2 = 0x00220201; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 172 | else if (s->selected_timings.CAS == 6) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 173 | launch2 = 0x00230302; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 174 | else |
Damien Zammit | 7c2e539 | 2016-07-24 03:28:42 +1000 | [diff] [blame] | 175 | die("Unsupported CAS\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 176 | |
| 177 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 178 | MCHBAR32(0x400*i + 0x220) = launch1; |
| 179 | MCHBAR32(0x400*i + 0x224) = launch2; |
| 180 | MCHBAR32(0x400*i + 0x21c) = launch3; |
| 181 | MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23); |
| 182 | } |
| 183 | |
| 184 | MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000; |
| 185 | MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0; |
| 186 | MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc; |
| 187 | } |
| 188 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 189 | static void clkset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 190 | { |
| 191 | MCHBAR16(0x400*ch + 0x5a0) = (MCHBAR16(0x400*ch + 0x5a0) & ~0xc440) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 192 | (setting->clk_delay << 14) | |
| 193 | (setting->db_sel << 6) | |
| 194 | (setting->db_en << 10); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 195 | MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 196 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 197 | MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 198 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 199 | } |
| 200 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 201 | static void clkset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 202 | { |
| 203 | MCHBAR32(0x400*ch + 0x5a0) = (MCHBAR32(0x400*ch + 0x5a0) & ~0x30880) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 204 | (setting->clk_delay << 16) | |
| 205 | (setting->db_sel << 7) | |
| 206 | (setting->db_en << 11); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 207 | MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 208 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 209 | MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 210 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 211 | } |
| 212 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 213 | static void ctrlset0(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 214 | { |
| 215 | MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x3300000) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 216 | (setting->clk_delay << 24) | |
| 217 | (setting->db_sel << 20) | |
| 218 | (setting->db_en << 21); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 219 | MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 220 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 221 | MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 222 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 223 | } |
| 224 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 225 | static void ctrlset1(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 226 | { |
| 227 | MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x18c00000) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 228 | (setting->clk_delay << 27) | |
| 229 | (setting->db_sel << 22) | |
| 230 | (setting->db_en << 23); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 231 | MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 232 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 233 | MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 234 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 235 | } |
| 236 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 237 | static void ctrlset2(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 238 | { |
| 239 | MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 240 | (setting->clk_delay << 14) | |
| 241 | (setting->db_sel << 12) | |
| 242 | (setting->db_en << 13); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 243 | MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 244 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 245 | MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 246 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 247 | } |
| 248 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 249 | static void ctrlset3(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 250 | { |
| 251 | MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 252 | (setting->clk_delay << 10) | |
| 253 | (setting->db_sel << 8) | |
| 254 | (setting->db_en << 9); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 255 | MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 256 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 257 | MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 258 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 259 | } |
| 260 | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 261 | static void cmdset(u8 ch, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 262 | { |
| 263 | MCHBAR8(0x400*ch + 0x598) = (MCHBAR8(0x400*ch + 0x598) & ~0x30) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 264 | (setting->clk_delay << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 265 | MCHBAR8(0x400*ch + 0x594) = (MCHBAR8(0x400*ch + 0x594) & ~0x60) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 266 | (setting->db_sel << 5) | |
| 267 | (setting->db_en << 6); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 268 | MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0x70) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 269 | (setting->pi << 4); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 270 | MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0xf) | |
Arthur Heymans | 27f0ca1 | 2017-05-09 18:38:14 +0200 | [diff] [blame] | 271 | setting->tap; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 272 | } |
| 273 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 274 | /** |
| 275 | * All finer DQ and DQS DLL settings are set to the same value |
| 276 | * for each rank in a channel, while coarse is common. |
| 277 | */ |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 278 | void dqsset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 279 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 280 | int rank; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 281 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 282 | MCHBAR32(0x400 * ch + 0x5fc) = (MCHBAR32(0x400 * ch + 0x5fc) |
| 283 | & ~(1 << (lane * 4 + 1))) |
| 284 | | (setting->coarse << (lane * 4 + 1)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 285 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 286 | for (rank = 0; rank < 4; rank++) { |
| 287 | MCHBAR32(0x400 * ch + 0x5b4 + rank * 4) = |
| 288 | (MCHBAR32(0x400 * ch + 0x5b4 + rank * 4) |
| 289 | & ~(0x201 << lane)) |
| 290 | | (setting->db_en << (9 + lane)) |
| 291 | | (setting->db_sel << lane); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 292 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 293 | MCHBAR32(0x400*ch + 0x5c8 + rank * 4) = |
| 294 | (MCHBAR32(0x400 * ch + 0x5c8 + rank * 4) |
| 295 | & ~(0x3 << (16 + lane * 2))) |
| 296 | | (setting->clk_delay << (16+lane * 2)); |
| 297 | |
| 298 | MCHBAR8(0x400*ch + 0x520 + lane * 4 + rank) = |
| 299 | (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0x7f) |
| 300 | | (setting->pi << 4) |
| 301 | | setting->tap; |
| 302 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 303 | } |
| 304 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 305 | void dqset(u8 ch, u8 lane, const struct dll_setting *setting) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 306 | { |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 307 | int rank; |
| 308 | MCHBAR32(0x400 * ch + 0x5fc) = (MCHBAR32(0x400 * ch + 0x5fc) |
| 309 | & ~(1 << (lane * 4))) |
| 310 | | (setting->coarse << (lane * 4)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 311 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 312 | for (rank = 0; rank < 4; rank++) { |
| 313 | MCHBAR32(0x400 * ch + 0x5a4 + rank * 4) = |
| 314 | (MCHBAR32(0x400 * ch + 0x5a4 + rank * 4) |
| 315 | & ~(0x201 << lane)) |
| 316 | | (setting->db_en << (9 + lane)) |
| 317 | | (setting->db_sel << lane); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 318 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 319 | MCHBAR32(0x400 * ch + 0x5c8 + rank * 4) = |
| 320 | (MCHBAR32(0x400 * ch + 0x5c8 + rank * 4) |
| 321 | & ~(0x3 << (lane * 2))) |
| 322 | | (setting->clk_delay << (2 * lane)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 323 | |
Arthur Heymans | 3876f24 | 2017-06-09 22:55:22 +0200 | [diff] [blame] | 324 | MCHBAR8(0x400*ch + 0x500 + lane * 4 + rank) = |
| 325 | (MCHBAR8(0x400 * ch + 0x500 + lane * 4 + rank) & ~0x7f) |
| 326 | | (setting->pi << 4) |
| 327 | | setting->tap; |
| 328 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 329 | } |
| 330 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 331 | void rt_set_dqs(u8 channel, u8 lane, u8 rank, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 332 | struct rt_dqs_setting *dqs_setting) |
| 333 | { |
| 334 | u16 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); |
| 335 | u16 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 336 | printk(RAM_SPEW, "RT DQS: ch%d, r%d, L%d: %d.%d\n", channel, rank, lane, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 337 | dqs_setting->tap, |
| 338 | dqs_setting->pi); |
| 339 | |
| 340 | saved_tap &= ~(0xf << (rank * 4)); |
| 341 | saved_tap |= dqs_setting->tap << (rank * 4); |
| 342 | MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; |
| 343 | |
| 344 | saved_pi &= ~(0x7 << (rank * 3)); |
| 345 | saved_pi |= dqs_setting->pi << (rank * 3); |
| 346 | MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; |
| 347 | } |
| 348 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 349 | static void timings_ddr2(struct sysinfo *s) |
| 350 | { |
| 351 | u8 i; |
| 352 | u8 twl, ta1, ta2, ta3, ta4; |
| 353 | u8 reg8; |
| 354 | u8 flag1 = 0; |
| 355 | u8 flag2 = 0; |
| 356 | u16 reg16; |
| 357 | u32 reg32; |
| 358 | u16 ddr, fsb; |
| 359 | u8 trpmod = 0; |
| 360 | u8 bankmod = 1; |
| 361 | u8 pagemod = 0; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 362 | u8 adjusted_cas; |
| 363 | |
| 364 | adjusted_cas = s->selected_timings.CAS - 3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 365 | |
| 366 | u16 fsb2ps[3] = { |
| 367 | 5000, // 800 |
| 368 | 3750, // 1067 |
| 369 | 3000 // 1333 |
| 370 | }; |
| 371 | |
| 372 | u16 ddr2ps[6] = { |
| 373 | 5000, // 400 |
| 374 | 3750, // 533 |
| 375 | 3000, // 667 |
| 376 | 2500, // 800 |
| 377 | 1875, // 1067 |
| 378 | 1500 // 1333 |
| 379 | }; |
| 380 | |
| 381 | u16 lut1[6] = { |
| 382 | 0, |
| 383 | 0, |
| 384 | 2600, |
| 385 | 3120, |
| 386 | 4171, |
| 387 | 5200 |
| 388 | }; |
| 389 | |
| 390 | ta1 = 6; |
| 391 | ta2 = 6; |
| 392 | ta3 = 5; |
| 393 | ta4 = 8; |
| 394 | |
| 395 | twl = s->selected_timings.CAS - 1; |
| 396 | |
| 397 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 398 | if (s->dimms[i].n_banks == N_BANKS_8) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 399 | trpmod = 1; |
| 400 | bankmod = 0; |
| 401 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 402 | if (s->dimms[i].page_size == 2048) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 403 | pagemod = 1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 407 | MCHBAR8(0x400*i + 0x26f) = MCHBAR8(0x400*i + 0x26f) | 0x3; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 408 | MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 409 | MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) |
| 410 | | (0 << 4); /* tWL - x ?? */ |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 411 | MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) | |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 412 | adjusted_cas; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 413 | MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) | |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 414 | ((adjusted_cas + 9) << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 415 | |
| 416 | reg16 = (s->selected_timings.tRAS << 11) | |
| 417 | ((twl + 4 + s->selected_timings.tWR) << 6) | |
| 418 | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; |
| 419 | MCHBAR16(0x400*i + 0x250) = reg16; |
| 420 | |
| 421 | reg32 = (bankmod << 21) | |
| 422 | (s->selected_timings.tRRD << 17) | |
| 423 | (s->selected_timings.tRP << 13) | |
| 424 | ((s->selected_timings.tRP + trpmod) << 9) | |
| 425 | s->selected_timings.tRFC; |
| 426 | reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; |
| 427 | if (bankmod) { |
| 428 | switch (s->selected_timings.mem_clk) { |
| 429 | default: |
| 430 | case MEM_CLOCK_667MHz: |
| 431 | if (reg8) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 432 | if (pagemod) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 433 | reg32 |= 16 << 22; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 434 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 435 | reg32 |= 12 << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 436 | } else { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 437 | if (pagemod) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 438 | reg32 |= 18 << 22; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 439 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 440 | reg32 |= 14 << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 441 | } |
| 442 | break; |
| 443 | case MEM_CLOCK_800MHz: |
| 444 | if (reg8) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 445 | if (pagemod) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 446 | reg32 |= 18 << 22; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 447 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 448 | reg32 |= 14 << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 449 | } else { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 450 | if (pagemod) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 451 | reg32 |= 20 << 22; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 452 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 453 | reg32 |= 16 << 22; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 454 | } |
| 455 | break; |
| 456 | } |
| 457 | } |
| 458 | MCHBAR32(0x400*i + 0x252) = reg32; |
| 459 | |
| 460 | MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | |
| 461 | (0x4 << 8) | (ta2 << 4) | ta4; |
| 462 | |
| 463 | MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | |
| 464 | ((twl + 4 + s->selected_timings.tWTR) << 12) | |
| 465 | (ta3 << 8) | (4 << 4) | ta1; |
| 466 | |
| 467 | MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | |
| 468 | s->selected_timings.tRFC; |
| 469 | |
| 470 | MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1); |
| 471 | MCHBAR8(0x400*i + 0x264) = 0xff; |
| 472 | MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) | |
| 473 | s->selected_timings.tRAS; |
| 474 | MCHBAR16(0x400*i + 0x244) = 0x2310; |
| 475 | |
| 476 | switch (s->selected_timings.mem_clk) { |
| 477 | case MEM_CLOCK_667MHz: |
| 478 | reg8 = 0; |
| 479 | break; |
| 480 | default: |
| 481 | reg8 = 1; |
| 482 | break; |
| 483 | } |
| 484 | |
| 485 | MCHBAR8(0x400*i + 0x246) = (MCHBAR8(0x400*i + 0x246) & ~0x1f) | |
| 486 | (reg8 << 2) | 1; |
| 487 | |
| 488 | fsb = fsb2ps[s->selected_timings.fsb_clk]; |
| 489 | ddr = ddr2ps[s->selected_timings.mem_clk]; |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 490 | reg32 = (u32)((adjusted_cas + 7 + reg8) * ddr); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 491 | reg32 = (u32)((reg32 / fsb) << 8); |
| 492 | reg32 |= 0x0e000000; |
| 493 | if ((fsb2mhz(s->selected_timings.fsb_clk) / |
| 494 | ddr2mhz(s->selected_timings.mem_clk)) > 2) { |
| 495 | reg32 |= 1 << 24; |
| 496 | } |
| 497 | MCHBAR32(0x400*i + 0x248) = (MCHBAR32(0x400*i + 0x248) & ~0x0f001f00) | |
| 498 | reg32; |
| 499 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 500 | if (twl > 2) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 501 | flag1 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 502 | |
| 503 | if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 504 | flag2 = 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 505 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 506 | reg16 = (u8)(twl - 1 - flag1 - flag2); |
| 507 | reg16 |= reg16 << 4; |
| 508 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 509 | if (reg16) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 510 | reg16--; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 511 | } |
| 512 | reg16 |= flag1 << 8; |
| 513 | reg16 |= flag2 << 9; |
| 514 | MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16; |
| 515 | MCHBAR16(0x400*i + 0x25e) = 0x15a5; |
| 516 | MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f; |
| 517 | MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) | |
| 518 | (0x3f << 14) | lut1[s->selected_timings.mem_clk]; |
| 519 | MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1; |
| 520 | MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3; |
| 521 | |
| 522 | reg16 = 0; |
| 523 | switch (s->selected_timings.mem_clk) { |
| 524 | default: |
| 525 | case MEM_CLOCK_667MHz: |
| 526 | reg16 = 0x99; |
| 527 | break; |
| 528 | case MEM_CLOCK_800MHz: |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 529 | if (s->selected_timings.CAS == 5) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 530 | reg16 = 0x19a; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 531 | else if (s->selected_timings.CAS == 6) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 532 | reg16 = 0x9a; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 533 | break; |
| 534 | } |
| 535 | reg16 &= 0x7; |
| 536 | reg16 += twl + 9; |
| 537 | reg16 <<= 10; |
| 538 | MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16; |
| 539 | MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13; |
| 540 | MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a; |
| 541 | |
| 542 | reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; |
| 543 | reg16 += 2 << 12; |
| 544 | reg16 |= (0x15 << 6) | 0x1f; |
| 545 | MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16; |
| 546 | |
| 547 | reg32 = (1 << 25) | (6 << 27); |
| 548 | MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32; |
| 549 | MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80; |
| 550 | MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6; |
| 551 | } // END EACH POPULATED CHANNEL |
| 552 | |
| 553 | reg16 = 0x1f << 5; |
| 554 | reg16 |= 0xe << 10; |
| 555 | MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16; |
| 556 | MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540; |
| 557 | MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f; |
| 558 | MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0; |
| 559 | MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11; |
| 560 | MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11; |
| 561 | MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10; |
| 562 | MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10; |
| 563 | MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; |
| 564 | reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); |
| 565 | MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); |
Arthur Heymans | eee4f6b | 2017-01-03 00:49:45 +0100 | [diff] [blame] | 566 | reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 567 | MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; |
| 568 | MCHBAR8(0x12f) = 0x4c; |
| 569 | reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); |
| 570 | MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32; |
| 571 | MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; |
| 572 | } |
| 573 | |
| 574 | static void dll_ddr2(struct sysinfo *s) |
| 575 | { |
Arthur Heymans | 37689fa | 2017-05-17 14:07:10 +0200 | [diff] [blame] | 576 | u8 i, j, r, reg8, clk, async = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 577 | u16 reg16 = 0; |
| 578 | u32 reg32 = 0; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 579 | |
| 580 | MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; |
| 581 | MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; |
| 582 | MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f; |
| 583 | MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100; |
| 584 | MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33; |
| 585 | switch (s->selected_timings.mem_clk) { |
| 586 | default: |
| 587 | case MEM_CLOCK_667MHz: |
| 588 | reg16 = (0xa << 9) | 0xa; |
| 589 | break; |
| 590 | case MEM_CLOCK_800MHz: |
| 591 | reg16 = (0x9 << 9) | 0x9; |
| 592 | break; |
| 593 | } |
| 594 | MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16; |
| 595 | MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010; |
| 596 | udelay(1); |
| 597 | MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100; |
| 598 | |
| 599 | MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd; |
| 600 | |
| 601 | udelay(1); |
| 602 | MCHBAR8(0x190) = MCHBAR8(0x190) & ~1; |
| 603 | udelay(1); // 533ns |
| 604 | MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000; |
| 605 | udelay(1); |
| 606 | MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455; |
| 607 | udelay(1); |
| 608 | MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c; |
| 609 | MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c; |
| 610 | udelay(1); // 533ns |
| 611 | MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3; |
| 612 | MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3; |
| 613 | udelay(1); // 533ns |
| 614 | |
| 615 | // ME related |
| 616 | MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803; |
| 617 | |
| 618 | MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800; |
| 619 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; |
| 620 | |
| 621 | FOR_EACH_CHANNEL(i) { |
| 622 | reg16 = 0; |
| 623 | MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000; |
| 624 | |
| 625 | reg32 = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 626 | FOR_EACH_RANK_IN_CHANNEL(r) { |
| 627 | if (!RANK_IS_POPULATED(s->dimms, i, r)) |
| 628 | reg32 |= 0x111 << r; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 629 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 630 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 631 | MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32; |
| 632 | MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1; |
| 633 | |
| 634 | if (!CHANNEL_IS_POPULATED(s->dimms, i)) { |
| 635 | printk(BIOS_DEBUG, "No dimms in channel %d\n", i); |
| 636 | reg8 = 0x3f; |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 637 | } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 638 | printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); |
| 639 | reg8 = 0x38; |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 640 | } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 641 | printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); |
| 642 | reg8 = 0x7; |
Elyes HAOUAS | 12df950 | 2016-08-23 21:29:48 +0200 | [diff] [blame] | 643 | } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 644 | printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); |
| 645 | reg8 = 0; |
| 646 | } else { |
| 647 | die("Unhandled case\n"); |
| 648 | } |
| 649 | |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 650 | //reg8 = 0x00; // FIXME don't switch on all clocks anyway |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 651 | |
| 652 | MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) | |
| 653 | ((u32)(reg8 << 24)); |
| 654 | } // END EACH CHANNEL |
| 655 | |
| 656 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; |
| 657 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; |
| 658 | |
| 659 | // Update DLL timing |
| 660 | MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80; |
| 661 | MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40; |
| 662 | MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400; |
| 663 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 664 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 665 | MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; |
| 666 | MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; |
| 667 | MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70; |
| 668 | MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555; |
| 669 | } |
| 670 | |
| 671 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 672 | const struct dll_setting *setting; |
| 673 | |
| 674 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 675 | setting = default_ddr2_667_ctrl; |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 676 | else |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 677 | setting = default_ddr2_800_ctrl; |
Jonathan Neuschäfer | 7be74db | 2018-02-12 12:00:40 +0100 | [diff] [blame] | 678 | |
| 679 | clkset0(i, &setting[CLKSET0]); |
| 680 | clkset1(i, &setting[CLKSET1]); |
| 681 | ctrlset0(i, &setting[CTRL0]); |
| 682 | ctrlset1(i, &setting[CTRL1]); |
| 683 | ctrlset2(i, &setting[CTRL2]); |
| 684 | ctrlset3(i, &setting[CTRL3]); |
| 685 | cmdset(i, &setting[CMD]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 686 | } |
| 687 | |
| 688 | // XXX if not async mode |
| 689 | MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200; |
| 690 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; |
| 691 | j = 0; |
| 692 | for (i = 0; i < 16; i++) { |
| 693 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 694 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 695 | while (MCHBAR8(0x180) & 0x10) |
| 696 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 697 | if (MCHBAR32(0x184) == 0xffffffff) { |
| 698 | j++; |
| 699 | if (j >= 2) |
| 700 | break; |
| 701 | |
| 702 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 703 | j = 2; |
| 704 | break; |
| 705 | } |
| 706 | } else { |
| 707 | j = 0; |
| 708 | } |
| 709 | } |
| 710 | if (i == 1 || ((i == 0) && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
| 711 | j = 0; |
| 712 | i++; |
| 713 | for (; i < 16; i++) { |
| 714 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 715 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 716 | while (MCHBAR8(0x180) & 0x10) |
| 717 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 718 | if (MCHBAR32(0x184) == 0) { |
| 719 | i++; |
| 720 | break; |
| 721 | } |
| 722 | } |
| 723 | for (; i < 16; i++) { |
| 724 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 725 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 726 | while (MCHBAR8(0x180) & 0x10) |
| 727 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 728 | if (MCHBAR32(0x184) == 0xffffffff) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 729 | j++; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 730 | if (j >= 2) |
| 731 | break; |
| 732 | } else { |
| 733 | j = 0; |
| 734 | } |
| 735 | } |
| 736 | if (j < 2) { |
| 737 | MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; |
| 738 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 739 | while (MCHBAR8(0x180) & 0x10) |
| 740 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 741 | j = 2; |
| 742 | } |
| 743 | } |
| 744 | |
| 745 | if (j < 2) { |
| 746 | MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; |
| 747 | async = 1; |
| 748 | } |
| 749 | |
| 750 | clk = 0x1a; |
| 751 | if (async != 1) { |
| 752 | reg8 = MCHBAR8(0x188) & 0x1e; |
| 753 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 754 | s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 755 | clk = 0x10; |
| 756 | } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 757 | clk = 0x10; |
| 758 | } else { |
| 759 | clk = 0x1a; |
| 760 | } |
| 761 | } |
| 762 | MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80; |
| 763 | |
| 764 | if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && |
| 765 | (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
Arthur Heymans | 24798a1 | 2017-08-13 16:02:09 +0200 | [diff] [blame] | 766 | i = MCHBAR8(0x1c8) & 0xf; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 767 | i = (i + 10) % 14; |
| 768 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 769 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 770 | while (MCHBAR8(0x180) & 0x10) |
| 771 | ; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | reg8 = MCHBAR8(0x188) & ~1; |
| 775 | MCHBAR8(0x188) = reg8; |
| 776 | reg8 &= ~0x3e; |
| 777 | reg8 |= clk; |
| 778 | MCHBAR8(0x188) = reg8; |
| 779 | reg8 |= 1; |
| 780 | MCHBAR8(0x188) = reg8; |
| 781 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 782 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 783 | MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 784 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 785 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 786 | static void select_default_dq_dqs_settings(struct sysinfo *s) |
| 787 | { |
| 788 | int ch, lane; |
| 789 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 790 | FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) { |
| 791 | switch (s->selected_timings.mem_clk) { |
| 792 | case MEM_CLOCK_667MHz: |
| 793 | memcpy(s->dqs_settings[ch], |
| 794 | default_ddr2_667_dqs, |
| 795 | sizeof(s->dqs_settings[ch])); |
| 796 | memcpy(s->dq_settings[ch], |
| 797 | default_ddr2_667_dq, |
| 798 | sizeof(s->dq_settings[ch])); |
| 799 | s->rt_dqs[ch][lane].tap = 7; |
| 800 | s->rt_dqs[ch][lane].pi = 2; |
| 801 | break; |
| 802 | case MEM_CLOCK_800MHz: |
| 803 | if (s->spd_type == DDR2) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 804 | memcpy(s->dqs_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 805 | default_ddr2_800_dqs, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 806 | sizeof(s->dqs_settings[ch])); |
| 807 | memcpy(s->dq_settings[ch], |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 808 | default_ddr2_800_dq, |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 809 | sizeof(s->dq_settings[ch])); |
| 810 | s->rt_dqs[ch][lane].tap = 7; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 811 | s->rt_dqs[ch][lane].pi = 0; |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 812 | } else { /* DDR3 */ |
| 813 | /* TODO: DDR3 write DQ-DQS */ |
| 814 | s->rt_dqs[ch][lane].tap = 6; |
| 815 | s->rt_dqs[ch][lane].pi = 2; |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 816 | } |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 817 | break; |
| 818 | case MEM_CLOCK_1066MHz: |
| 819 | /* TODO: DDR3 write DQ-DQS */ |
| 820 | s->rt_dqs[ch][lane].tap = 5; |
| 821 | s->rt_dqs[ch][lane].pi = 2; |
| 822 | break; |
| 823 | case MEM_CLOCK_1333MHz: |
| 824 | /* TODO: DDR3 write DQ-DQS */ |
| 825 | s->rt_dqs[ch][lane].tap = 7; |
| 826 | s->rt_dqs[ch][lane].pi = 0; |
| 827 | break; |
| 828 | default: /* not supported */ |
| 829 | break; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 830 | } |
| 831 | } |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 832 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 833 | |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 834 | /* |
| 835 | * It looks like only the RT DQS register for the first rank |
| 836 | * is used for all ranks. Just set all the 'unused' RT DQS registers |
| 837 | * to the same as rank 0, out of precaution. |
| 838 | */ |
| 839 | static void set_all_dq_dqs_dll_settings(struct sysinfo *s) |
| 840 | { |
| 841 | // Program DQ/DQS dll settings |
| 842 | int ch, lane, rank; |
| 843 | |
| 844 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 845 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 846 | FOR_EACH_RANK_IN_CHANNEL(rank) { |
| 847 | rt_set_dqs(ch, lane, rank, |
| 848 | &s->rt_dqs[ch][lane]); |
| 849 | } |
| 850 | dqsset(ch, lane, &s->dqs_settings[ch][lane]); |
| 851 | dqset(ch, lane, &s->dq_settings[ch][lane]); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 852 | } |
| 853 | } |
| 854 | } |
| 855 | |
| 856 | static void rcomp_ddr2(struct sysinfo *s) |
| 857 | { |
| 858 | u8 i, j, k; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 859 | u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, |
| 860 | 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 861 | u16 x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; |
| 862 | u32 x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; |
| 863 | u32 x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; |
| 864 | u32 x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; |
| 865 | u32 x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; |
| 866 | u32 x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; |
| 867 | u32 x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; |
| 868 | u32 x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; |
| 869 | u32 x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; |
| 870 | u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; |
| 871 | u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; |
| 872 | |
| 873 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 874 | for (j = 0; j < 6; j++) { |
| 875 | if (j == 0) { |
| 876 | MCHBAR32(0x400*i + addr[j]) = |
| 877 | (MCHBAR32(0x400*i + addr[j]) & ~0xff000) | 0xaa000; |
| 878 | MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320) & ~0xffff) | 0x6666; |
| 879 | for (k = 0; k < 8; k++) { |
| 880 | MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) = |
| 881 | (MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; |
| 882 | MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) = |
| 883 | (MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; |
| 884 | } |
| 885 | } else { |
| 886 | MCHBAR16(0x400*i + addr[j]) = (MCHBAR16(0x400*i + addr[j]) & ~0xf000) | 0xa000; |
| 887 | MCHBAR16(0x400*i + addr[j] + 4) = (MCHBAR16(0x400*i + addr[j] + 4) & ~0xffff) | |
| 888 | x378[j]; |
| 889 | MCHBAR32(0x400*i + addr[j] + 0xe) = |
| 890 | (MCHBAR32(0x400*i + addr[j] + 0xe) & ~0x3f3f3f3f) | x382[j]; |
| 891 | MCHBAR32(0x400*i + addr[j] + 0x12) = |
| 892 | (MCHBAR32(0x400*i + addr[j] + 0x12) & ~0x3f3f3f3f) | x386[j]; |
| 893 | MCHBAR32(0x400*i + addr[j] + 0x16) = |
| 894 | (MCHBAR32(0x400*i + addr[j] + 0x16) & ~0x3f3f3f3f) | x38a[j]; |
| 895 | MCHBAR32(0x400*i + addr[j] + 0x1a) = |
| 896 | (MCHBAR32(0x400*i + addr[j] + 0x1a) & ~0x3f3f3f3f) | x38e[j]; |
| 897 | MCHBAR32(0x400*i + addr[j] + 0x1e) = |
| 898 | (MCHBAR32(0x400*i + addr[j] + 0x1e) & ~0x3f3f3f3f) | x392[j]; |
| 899 | MCHBAR32(0x400*i + addr[j] + 0x22) = |
| 900 | (MCHBAR32(0x400*i + addr[j] + 0x22) & ~0x3f3f3f3f) | x396[j]; |
| 901 | MCHBAR32(0x400*i + addr[j] + 0x26) = |
| 902 | (MCHBAR32(0x400*i + addr[j] + 0x26) & ~0x3f3f3f3f) | x39a[j]; |
| 903 | MCHBAR32(0x400*i + addr[j] + 0x2a) = |
| 904 | (MCHBAR32(0x400*i + addr[j] + 0x2a) & ~0x3f3f3f3f) | x39e[j]; |
| 905 | } |
| 906 | MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j]; |
| 907 | } |
| 908 | MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | 0x12; |
| 909 | MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | 0x12; |
| 910 | MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | 0x12; |
| 911 | MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | 0x12; |
| 912 | } // END EACH POPULATED CHANNEL |
| 913 | |
| 914 | MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00; |
| 915 | MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff; |
| 916 | MCHBAR16(0x178) = 0x0135; |
| 917 | MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0; |
| 918 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 919 | if (!CHANNEL_IS_POPULATED(s->dimms, 0)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 920 | MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 921 | if (!CHANNEL_IS_POPULATED(s->dimms, 1)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 922 | MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 923 | |
| 924 | MCHBAR8(0x130) = MCHBAR8(0x130) | 1; |
| 925 | } |
| 926 | |
| 927 | static void odt_ddr2(struct sysinfo *s) |
| 928 | { |
| 929 | u8 i; |
| 930 | u16 odt[16][2] = { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 931 | { 0x0000, 0x0000 }, // NC_NC |
| 932 | { 0x0000, 0x0001 }, // x8SS_NC |
| 933 | { 0x0000, 0x0011 }, // x8DS_NC |
| 934 | { 0x0000, 0x0001 }, // x16SS_NC |
| 935 | { 0x0004, 0x0000 }, // NC_x8SS |
| 936 | { 0x0101, 0x0404 }, // x8SS_x8SS |
| 937 | { 0x0101, 0x4444 }, // x8DS_x8SS |
| 938 | { 0x0101, 0x0404 }, // x16SS_x8SS |
| 939 | { 0x0044, 0x0000 }, // NC_x8DS |
| 940 | { 0x1111, 0x0404 }, // x8SS_x8DS |
| 941 | { 0x1111, 0x4444 }, // x8DS_x8DS |
| 942 | { 0x1111, 0x0404 }, // x16SS_x8DS |
| 943 | { 0x0004, 0x0000 }, // NC_x16SS |
| 944 | { 0x0101, 0x0404 }, // x8SS_x16SS |
| 945 | { 0x0101, 0x4444 }, // x8DS_x16SS |
| 946 | { 0x0101, 0x0404 }, // x16SS_x16SS |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 947 | }; |
| 948 | |
| 949 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 950 | MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; |
| 951 | MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; |
| 952 | MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; |
| 953 | MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; |
| 954 | } |
| 955 | } |
| 956 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 957 | static void pre_jedec_memory_map(void) |
| 958 | { |
| 959 | /* |
| 960 | * Configure the memory mapping in stacked mode (channel 1 being mapped |
| 961 | * above channel 0) and with 128M per rank. |
| 962 | * This simplifies dram trainings a lot since those need a test address. |
| 963 | * |
| 964 | * +-------------+ => 0 |
| 965 | * | ch 0, rank 0| |
| 966 | * +-------------+ => 0x8000000 (128M) |
| 967 | * | ch 0, rank 1| |
| 968 | * +-------------+ => 0x10000000 (256M) |
| 969 | * | ch 0, rank 2| |
| 970 | * +-------------+ => 0x18000000 (384M) |
| 971 | * | ch 0, rank 3| |
| 972 | * +-------------+ => 0x20000000 (512M) |
| 973 | * | ch 1, rank 0| |
| 974 | * +-------------+ => 0x28000000 (640M) |
| 975 | * | ch 1, rank 1| |
| 976 | * +-------------+ => 0x30000000 (768M) |
| 977 | * | ch 1, rank 2| |
| 978 | * +-------------+ => 0x38000000 (896M) |
| 979 | * | ch 1, rank 3| |
| 980 | * +-------------+ |
| 981 | * |
| 982 | * After all trainings are done this is set to the real values specified |
| 983 | * by the SPD. |
| 984 | */ |
| 985 | /* Set rank 0-3 populated */ |
| 986 | MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000; |
| 987 | MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000; |
| 988 | /* Set size of each rank to 128M */ |
| 989 | MCHBAR16(C0DRA01) = 0x0101; |
| 990 | MCHBAR16(C0DRA23) = 0x0101; |
| 991 | MCHBAR16(C1DRA01) = 0x0101; |
| 992 | MCHBAR16(C1DRA23) = 0x0101; |
| 993 | MCHBAR16(C0DRB0) = 0x0002; |
| 994 | MCHBAR16(C0DRB1) = 0x0004; |
| 995 | MCHBAR16(C0DRB2) = 0x0006; |
| 996 | MCHBAR16(C0DRB3) = 0x0008; |
| 997 | MCHBAR16(C1DRB0) = 0x0002; |
| 998 | MCHBAR16(C1DRB1) = 0x0004; |
| 999 | MCHBAR16(C1DRB2) = 0x0006; |
| 1000 | /* |
| 1001 | * For some reason the boundary needs to be 0x10 instead of 0x8 here. |
| 1002 | * Vendor does this too... |
| 1003 | */ |
| 1004 | MCHBAR16(C1DRB3) = 0x0010; |
| 1005 | MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM; |
| 1006 | MCHBAR32(0x104) = 0; |
| 1007 | MCHBAR16(0x102) = 0x400; |
| 1008 | MCHBAR8(0x110) = (2 << 5) | (3 << 3); |
| 1009 | MCHBAR16(0x10e) = 0; |
| 1010 | MCHBAR32(0x108) = 0; |
| 1011 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOLUD, 0x4000); |
| 1012 | /* TOM(64M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
| 1013 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOM, 0x10); |
| 1014 | /* TOUUD(1M unit) = 1G = TOTAL_CHANNELS * RANKS_PER_CHANNEL * 128M */ |
| 1015 | pci_write_config16(PCI_DEV(0, 0, 0), D0F0_TOUUD, 0x0400); |
| 1016 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_GBSM, 0x40000000); |
| 1017 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_BGSM, 0x40000000); |
| 1018 | pci_write_config32(PCI_DEV(0, 0, 0), D0F0_TSEG, 0x40000000); |
| 1019 | } |
| 1020 | |
| 1021 | u32 test_address(int channel, int rank) |
| 1022 | { |
| 1023 | ASSERT(channel <= 1 && rank < 4); |
| 1024 | return channel * 512 * MiB + rank * 128 * MiB; |
| 1025 | } |
| 1026 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1027 | static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val) |
| 1028 | { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1029 | u32 addr = test_address(ch, r); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1030 | volatile u32 rubbish; |
| 1031 | |
| 1032 | MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; |
| 1033 | MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1034 | rubbish = read32((void *)((val<<3) | addr)); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1035 | udelay(10); |
| 1036 | MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; |
| 1037 | MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; |
| 1038 | } |
| 1039 | |
| 1040 | static void jedec_ddr2(struct sysinfo *s) |
| 1041 | { |
| 1042 | u8 i; |
| 1043 | u16 mrsval, ch, r, v; |
| 1044 | |
| 1045 | u8 odt[16][4] = { |
| 1046 | {0x00, 0x00, 0x00, 0x00}, |
| 1047 | {0x01, 0x00, 0x00, 0x00}, |
| 1048 | {0x01, 0x01, 0x00, 0x00}, |
| 1049 | {0x01, 0x00, 0x00, 0x00}, |
| 1050 | {0x00, 0x00, 0x01, 0x00}, |
| 1051 | {0x11, 0x00, 0x11, 0x00}, |
| 1052 | {0x11, 0x11, 0x11, 0x00}, |
| 1053 | {0x11, 0x00, 0x11, 0x00}, |
| 1054 | {0x00, 0x00, 0x01, 0x01}, |
| 1055 | {0x11, 0x00, 0x11, 0x11}, |
| 1056 | {0x11, 0x11, 0x11, 0x11}, |
| 1057 | {0x11, 0x00, 0x11, 0x11}, |
| 1058 | {0x00, 0x00, 0x01, 0x00}, |
| 1059 | {0x11, 0x00, 0x11, 0x00}, |
| 1060 | {0x11, 0x11, 0x11, 0x00}, |
| 1061 | {0x11, 0x00, 0x11, 0x00} |
| 1062 | }; |
| 1063 | |
| 1064 | u16 jedec[12][2] = { |
| 1065 | {NOP_CMD, 0x0}, |
| 1066 | {PRECHARGE_CMD, 0x0}, |
| 1067 | {EMRS2_CMD, 0x0}, |
| 1068 | {EMRS3_CMD, 0x0}, |
| 1069 | {EMRS1_CMD, 0x0}, |
| 1070 | {MRS_CMD, 0x100}, // DLL Reset |
| 1071 | {PRECHARGE_CMD, 0x0}, |
| 1072 | {CBR_CMD, 0x0}, |
| 1073 | {CBR_CMD, 0x0}, |
| 1074 | {MRS_CMD, 0x0}, // DLL out of reset |
| 1075 | {EMRS1_CMD, 0x380}, // OCD calib default |
| 1076 | {EMRS1_CMD, 0x0} |
| 1077 | }; |
| 1078 | |
| 1079 | mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; |
| 1080 | |
| 1081 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1082 | |
| 1083 | udelay(200); |
| 1084 | |
| 1085 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1086 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1087 | for (i = 0; i < 12; i++) { |
| 1088 | v = jedec[i][1]; |
| 1089 | switch (jedec[i][0]) { |
| 1090 | case EMRS1_CMD: |
| 1091 | v |= (odt[s->dimm_config[ch]][r] << 2); |
| 1092 | break; |
| 1093 | case MRS_CMD: |
| 1094 | v |= mrsval; |
| 1095 | break; |
| 1096 | default: |
| 1097 | break; |
| 1098 | } |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1099 | dojedec_ddr2(r, ch, jedec[i][0], v); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1100 | udelay(1); |
Arthur Heymans | cfa2eaa | 2017-03-20 16:32:07 +0100 | [diff] [blame] | 1101 | printk(RAM_SPEW, "Jedec step %d\n", i); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1102 | } |
| 1103 | } |
| 1104 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1105 | } |
| 1106 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1107 | static void sdram_recover_receive_enable(const struct sysinfo *s) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1108 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1109 | u32 reg32; |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1110 | u16 medium, coarse_offset; |
| 1111 | u8 pi_tap; |
| 1112 | int lane, channel; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1113 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1114 | FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) { |
| 1115 | medium = 0; |
| 1116 | coarse_offset = 0; |
| 1117 | reg32 = MCHBAR32(0x400 * channel + 0x248); |
| 1118 | reg32 &= ~0xf0000; |
| 1119 | reg32 |= s->rcven_t[channel].min_common_coarse << 16; |
| 1120 | MCHBAR32(0x400 * channel + 0x248) = reg32; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1121 | |
Arthur Heymans | 276049f | 2017-11-05 05:56:34 +0100 | [diff] [blame] | 1122 | FOR_EACH_BYTELANE(lane) { |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1123 | medium |= s->rcven_t[channel].medium[lane] |
| 1124 | << (lane * 2); |
| 1125 | coarse_offset |= |
| 1126 | (s->rcven_t[channel].coarse_offset[lane] & 0x3) |
| 1127 | << (lane * 2); |
| 1128 | |
| 1129 | pi_tap = MCHBAR8(0x400 * channel + 0x560 + lane * 4); |
| 1130 | pi_tap &= ~0x7f; |
| 1131 | pi_tap |= s->rcven_t[channel].tap[lane]; |
| 1132 | pi_tap |= s->rcven_t[channel].pi[lane] << 4; |
| 1133 | MCHBAR8(0x400 * channel + 0x560 + lane * 4) = pi_tap; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1134 | } |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1135 | MCHBAR16(0x400 * channel + 0x58c) = medium; |
| 1136 | MCHBAR16(0x400 * channel + 0x5fa) = coarse_offset; |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1137 | } |
| 1138 | } |
| 1139 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1140 | static void sdram_program_receive_enable(struct sysinfo *s, int fast_boot) |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1141 | { |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1142 | /* Program Receive Enable Timings */ |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1143 | if (fast_boot) |
| 1144 | sdram_recover_receive_enable(s); |
| 1145 | else |
Arthur Heymans | 6d7a8c1 | 2017-03-07 20:48:14 +0100 | [diff] [blame] | 1146 | rcven(s); |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1147 | } |
| 1148 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1149 | static void dradrb_ddr2(struct sysinfo *s) |
| 1150 | { |
| 1151 | u8 map, i, ch, r, rankpop0, rankpop1; |
| 1152 | u32 c0dra = 0; |
| 1153 | u32 c1dra = 0; |
| 1154 | u32 c0drb = 0; |
| 1155 | u32 c1drb = 0; |
| 1156 | u32 dra; |
| 1157 | u32 dra0; |
| 1158 | u32 dra1; |
| 1159 | u16 totalmemorymb; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1160 | u32 size, offset; |
| 1161 | u32 size0, size1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1162 | u8 dratab[2][2][2][4] = { |
| 1163 | { |
| 1164 | { |
| 1165 | {0xff, 0xff, 0xff, 0xff}, |
| 1166 | {0xff, 0x00, 0x02, 0xff} |
| 1167 | }, |
| 1168 | { |
| 1169 | {0xff, 0x01, 0xff, 0xff}, |
| 1170 | {0xff, 0x03, 0xff, 0xff} |
| 1171 | } |
| 1172 | }, |
| 1173 | { |
| 1174 | { |
| 1175 | {0xff, 0xff, 0xff, 0xff}, |
| 1176 | {0xff, 0x04, 0x06, 0x08} |
| 1177 | }, |
| 1178 | { |
| 1179 | {0xff, 0xff, 0xff, 0xff}, |
| 1180 | {0x05, 0x07, 0x09, 0xff} |
| 1181 | } |
| 1182 | } |
| 1183 | }; |
| 1184 | |
| 1185 | u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; |
| 1186 | |
| 1187 | // DRA |
| 1188 | rankpop0 = 0; |
| 1189 | rankpop1 = 0; |
| 1190 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1191 | if (s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED |
| 1192 | && (r) < s->dimms[ch<<1].ranks) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1193 | i = ch << 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1194 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1195 | i = (ch << 1) + 1; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1196 | |
| 1197 | dra = dratab[s->dimms[i].n_banks] |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1198 | [s->dimms[i].width] |
| 1199 | [s->dimms[i].cols-9] |
| 1200 | [s->dimms[i].rows-12]; |
Arthur Heymans | 3cf9403 | 2017-04-05 16:17:26 +0200 | [diff] [blame] | 1201 | if (s->dimms[i].n_banks == N_BANKS_8) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1202 | dra |= 0x80; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1203 | if (ch == 0) { |
| 1204 | c0dra |= dra << (r*8); |
| 1205 | rankpop0 |= 1 << r; |
| 1206 | } else { |
| 1207 | c1dra |= dra << (r*8); |
| 1208 | rankpop1 |= 1 << r; |
| 1209 | } |
| 1210 | } |
| 1211 | MCHBAR32(0x208) = c0dra; |
| 1212 | MCHBAR32(0x608) = c1dra; |
| 1213 | |
| 1214 | MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); |
| 1215 | MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); |
| 1216 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1217 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || |
| 1218 | ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1219 | MCHBAR8(0x260) = MCHBAR8(0x260) | 1; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1220 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || |
| 1221 | ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1222 | MCHBAR8(0x660) = MCHBAR8(0x660) | 1; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1223 | |
| 1224 | // DRB |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame^] | 1225 | FOR_EACH_RANK(ch, r) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1226 | if (ch == 0) { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame^] | 1227 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
| 1228 | dra0 = (c0dra >> (8*r)) & 0x7f; |
| 1229 | c0drb = (u16)(c0drb + drbtab[dra0]); |
| 1230 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1231 | MCHBAR16(0x200 + 2*r) = c0drb; |
| 1232 | } else { |
Arthur Heymans | dfce932 | 2017-12-16 19:48:00 +0100 | [diff] [blame^] | 1233 | if (RANK_IS_POPULATED(s->dimms, ch, r)) { |
| 1234 | dra1 = (c1dra >> (8*r)) & 0x7f; |
| 1235 | c1drb = (u16)(c1drb + drbtab[dra1]); |
| 1236 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1237 | MCHBAR16(0x600 + 2*r) = c1drb; |
| 1238 | } |
| 1239 | } |
| 1240 | |
| 1241 | s->channel_capacity[0] = c0drb << 6; |
| 1242 | s->channel_capacity[1] = c1drb << 6; |
| 1243 | totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1244 | printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", |
| 1245 | s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); |
| 1246 | |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1247 | /* Populated channel sizes in MiB */ |
| 1248 | size0 = s->channel_capacity[0]; |
| 1249 | size1 = s->channel_capacity[1]; |
| 1250 | |
| 1251 | MCHBAR8(0x111) = MCHBAR8(0x111) & ~0x2; |
| 1252 | MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4); |
| 1253 | |
| 1254 | /* Set ME UMA size in MiB */ |
| 1255 | MCHBAR16(0x100) = ME_UMA_SIZEMB; |
| 1256 | |
| 1257 | /* Set ME UMA Present bit */ |
| 1258 | MCHBAR32(0x111) = MCHBAR32(0x111) | 1; |
| 1259 | |
| 1260 | size = MIN(size0 - ME_UMA_SIZEMB, size1) * 2; |
| 1261 | |
| 1262 | MCHBAR16(0x104) = size; |
| 1263 | MCHBAR16(0x102) = size0 + size1 - size; |
| 1264 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1265 | map = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1266 | if (size0 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1267 | map = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1268 | else if (size1 == 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1269 | map |= 0x20; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1270 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1271 | map |= 0x40; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1272 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1273 | if (size == 0) |
| 1274 | map |= 0x18; |
| 1275 | |
| 1276 | if (size0 - ME_UMA_SIZEMB >= size1) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1277 | map |= 0x4; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1278 | MCHBAR8(0x110) = map; |
| 1279 | MCHBAR16(0x10e) = 0; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1280 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1281 | if (size1 != 0) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1282 | offset = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1283 | else if ((size0 > size1) && ((map & 0x7) == 0x4)) |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1284 | offset = size/2 + (size0 + size1 - size); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1285 | else |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1286 | offset = size/2 + ME_UMA_SIZEMB; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1287 | MCHBAR16(0x108) = offset; |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1288 | MCHBAR16(0x10a) = size/2; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1289 | } |
| 1290 | |
| 1291 | static void mmap_ddr2(struct sysinfo *s) |
| 1292 | { |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1293 | bool reclaim; |
| 1294 | u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; |
| 1295 | u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1296 | u16 ggc; |
Arthur Heymans | 27f94ee | 2016-06-18 21:08:58 +0200 | [diff] [blame] | 1297 | u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, |
| 1298 | 160, 224, 352 }; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1299 | u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 1300 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1301 | ggc = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1302 | gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; |
| 1303 | gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; |
| 1304 | tsegsize = 1; // 1MB TSEG |
Damien Zammit | 523e90f | 2016-09-05 02:32:40 +1000 | [diff] [blame] | 1305 | mmiosize = 0x800; // 2GB MMIO |
Damien Zammit | 9fb08f5 | 2016-01-22 18:56:23 +1100 | [diff] [blame] | 1306 | tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1307 | tolud = MIN(0x1000 - mmiosize, tom); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1308 | |
| 1309 | reclaim = false; |
| 1310 | if ((tom - tolud) > 0x40) |
| 1311 | reclaim = true; |
| 1312 | |
| 1313 | if (reclaim) { |
| 1314 | tolud = tolud & ~0x3f; |
| 1315 | tom = tom & ~0x3f; |
| 1316 | reclaimbase = MAX(0x1000, tom); |
| 1317 | reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; |
| 1318 | } |
| 1319 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1320 | touud = tom; |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1321 | if (reclaim) |
| 1322 | touud = reclaimlimit + 0x40; |
| 1323 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1324 | gfxbase = tolud - gfxsize; |
| 1325 | gttbase = gfxbase - gttsize; |
| 1326 | tsegbase = gttbase - tsegsize; |
| 1327 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1328 | pci_write_config16(PCI_DEV(0, 0, 0), 0xb0, tolud << 4); |
| 1329 | pci_write_config16(PCI_DEV(0, 0, 0), 0xa0, tom >> 6); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1330 | if (reclaim) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1331 | pci_write_config16(PCI_DEV(0, 0, 0), 0x98, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1332 | (u16)(reclaimbase >> 6)); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1333 | pci_write_config16(PCI_DEV(0, 0, 0), 0x9a, |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1334 | (u16)(reclaimlimit >> 6)); |
| 1335 | } |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1336 | pci_write_config16(PCI_DEV(0, 0, 0), 0xa2, touud); |
| 1337 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa4, gfxbase << 20); |
| 1338 | pci_write_config32(PCI_DEV(0, 0, 0), 0xa8, gttbase << 20); |
| 1339 | pci_write_config32(PCI_DEV(0, 0, 0), 0xac, tsegbase << 20); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1340 | } |
| 1341 | |
| 1342 | static void enhanced_ddr2(struct sysinfo *s) |
| 1343 | { |
| 1344 | u8 ch, reg8; |
| 1345 | |
| 1346 | MCHBAR32(0xfb0) = 0x1000d024; |
| 1347 | MCHBAR32(0xfb4) = 0xc842; |
| 1348 | MCHBAR32(0xfbc) = 0xf; |
| 1349 | MCHBAR32(0xfc4) = 0xfe22244; |
| 1350 | MCHBAR8(0x12f) = 0x5c; |
| 1351 | MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1; |
| 1352 | MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2; |
| 1353 | MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0; |
| 1354 | MCHBAR32(0xfa8) = 0x30d400; |
| 1355 | |
| 1356 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1357 | MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; |
| 1358 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1359 | MCHBAR16(0x400*ch + 0x27c) = 0x0041; |
| 1360 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
| 1361 | MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100; |
| 1362 | MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1; |
| 1363 | MCHBAR32(0x400*ch + 0x288) = 0x8040200; |
| 1364 | MCHBAR32(0x400*ch + 0x28c) = 0xff402010; |
| 1365 | MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; |
| 1366 | } |
| 1367 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1368 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 1369 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | 1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1370 | MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2; |
| 1371 | MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2; |
| 1372 | MCHBAR32(0x2c) = 0x44a53; |
| 1373 | MCHBAR32(0x30) = 0x1f5a86; |
| 1374 | MCHBAR32(0x34) = 0x1902810; |
| 1375 | MCHBAR32(0x38) = 0xf7000000; |
| 1376 | MCHBAR32(0x3c) = 0x23014410; |
| 1377 | MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000; |
| 1378 | MCHBAR32(0x20) = 0x33001; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1379 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~1); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1380 | } |
| 1381 | |
| 1382 | static void power_ddr2(struct sysinfo *s) |
| 1383 | { |
| 1384 | u32 reg1, reg2, reg3, reg4, clkgate, x592; |
| 1385 | u8 lane, ch; |
| 1386 | u8 twl = 0; |
| 1387 | u16 x264, x23c; |
| 1388 | |
| 1389 | twl = s->selected_timings.CAS - 1; |
| 1390 | x264 = 0x78; |
| 1391 | switch (s->selected_timings.mem_clk) { |
| 1392 | default: |
| 1393 | case MEM_CLOCK_667MHz: |
| 1394 | reg1 = 0x99; |
| 1395 | reg2 = 0x1048a9; |
| 1396 | clkgate = 0x230000; |
| 1397 | x23c = 0x7a89; |
| 1398 | break; |
| 1399 | case MEM_CLOCK_800MHz: |
| 1400 | if (s->selected_timings.CAS == 5) { |
| 1401 | reg1 = 0x19a; |
| 1402 | reg2 = 0x1048aa; |
| 1403 | } else { |
| 1404 | reg1 = 0x9a; |
| 1405 | reg2 = 0x2158aa; |
| 1406 | x264 = 0x89; |
| 1407 | } |
| 1408 | clkgate = 0x280000; |
| 1409 | x23c = 0x7b89; |
| 1410 | break; |
| 1411 | } |
| 1412 | reg3 = 0x232; |
| 1413 | reg4 = 0x2864; |
| 1414 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1415 | if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1416 | MCHBAR32(0x14) = 0x0010461f; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1417 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1418 | MCHBAR32(0x14) = 0x0010691f; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1419 | MCHBAR32(0x18) = 0xdf6437f7; |
| 1420 | MCHBAR32(0x1c) = 0x0; |
| 1421 | MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000; |
| 1422 | MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000; |
| 1423 | MCHBAR16(0x115) = (u16) reg1; |
| 1424 | MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2; |
| 1425 | MCHBAR8(0x124) = 0x7; |
| 1426 | MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80; |
| 1427 | MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0; |
| 1428 | MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15); |
| 1429 | MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00; |
| 1430 | MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8; |
| 1431 | MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1; |
| 1432 | MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf; |
| 1433 | MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80; |
| 1434 | MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii |
| 1435 | MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate; |
| 1436 | MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f; |
| 1437 | MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0; |
| 1438 | MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70; |
| 1439 | MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi |
| 1440 | MCHBAR32(0x2d4) = 0x40453600; |
| 1441 | MCHBAR32(0x300) = 0xc0b0a08; |
| 1442 | MCHBAR32(0x304) = 0x6040201; |
| 1443 | MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405; |
| 1444 | MCHBAR16(0x610) = 0x232; |
| 1445 | MCHBAR16(0x612) = 0x2864; |
| 1446 | MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; |
| 1447 | MCHBAR32(0xae4) = 0; |
| 1448 | MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; |
| 1449 | MCHBAR32(0xf00) = 0x393a3b3c; |
| 1450 | MCHBAR32(0xf04) = 0x3d3e3f40; |
| 1451 | MCHBAR32(0xf08) = 0x393a3b3c; |
| 1452 | MCHBAR32(0xf0c) = 0x3d3e3f40; |
| 1453 | MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001; |
| 1454 | MCHBAR32(0xf48) = 0xfff0ffe0; |
| 1455 | MCHBAR32(0xf4c) = 0xffc0ff00; |
| 1456 | MCHBAR32(0xf50) = 0xfc00f000; |
| 1457 | MCHBAR32(0xf54) = 0xc0008000; |
| 1458 | MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000; |
| 1459 | MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000; |
| 1460 | MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000; |
| 1461 | MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000; |
| 1462 | MCHBAR32(0x1104) = 0x3003232; |
| 1463 | MCHBAR32(0x1108) = 0x74; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1464 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1465 | MCHBAR32(0x110c) = 0xaa; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1466 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1467 | MCHBAR32(0x110c) = 0x100; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1468 | MCHBAR32(0x1110) = 0x10810350 & ~0x78; |
| 1469 | MCHBAR32(0x1114) = 0; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1470 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1471 | twl = 5; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1472 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1473 | twl = 6; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1474 | x592 = 0xff; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1475 | if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 3) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1476 | x592 = ~0x4; |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1477 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1478 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1479 | MCHBAR8(0x400*ch + 0x239) = twl + 15; |
| 1480 | MCHBAR16(0x400*ch + 0x23c) = x23c; |
| 1481 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033; |
| 1482 | MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16); |
| 1483 | MCHBAR8(0x400*ch + 0x264) = x264; |
| 1484 | MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592); |
| 1485 | MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e; |
| 1486 | } |
| 1487 | |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1488 | for (lane = 0; lane < 8; lane++) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1489 | MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1490 | } |
| 1491 | |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1492 | void raminit_ddr2(struct sysinfo *s, int fast_boot) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1493 | { |
| 1494 | u8 ch; |
| 1495 | u8 r, bank; |
| 1496 | u32 reg32; |
| 1497 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1498 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
| 1499 | // Clear self refresh |
| 1500 | MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) |
| 1501 | | PMSTS_BOTH_SELFREFRESH; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1502 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1503 | // Clear host clk gate reg |
| 1504 | MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1505 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1506 | // Select DDR2 |
| 1507 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1508 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1509 | // Set freq |
| 1510 | MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | |
| 1511 | (s->selected_timings.mem_clk << 4) | (1 << 10); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1512 | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1513 | // Overwrite freq if chipset rejects it |
| 1514 | s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; |
| 1515 | if (s->selected_timings.mem_clk > (s->max_fsb + 3)) |
| 1516 | die("Error: DDR is faster than FSB, halt\n"); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1517 | } |
| 1518 | |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1519 | // Program clock crossing |
| 1520 | clkcross_ddr2(s); |
| 1521 | printk(BIOS_DEBUG, "Done clk crossing\n"); |
| 1522 | |
| 1523 | // DDR2 IO |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1524 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
| 1525 | setioclk_ddr2(s); |
| 1526 | printk(BIOS_DEBUG, "Done I/O clk\n"); |
| 1527 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1528 | |
| 1529 | // Grant to launch |
| 1530 | launch_ddr2(s); |
| 1531 | printk(BIOS_DEBUG, "Done launch\n"); |
| 1532 | |
| 1533 | // Program DDR2 timings |
| 1534 | timings_ddr2(s); |
| 1535 | printk(BIOS_DEBUG, "Done timings\n"); |
| 1536 | |
| 1537 | // Program DLL |
| 1538 | dll_ddr2(s); |
Arthur Heymans | 0bf87de | 2017-11-04 06:15:05 +0100 | [diff] [blame] | 1539 | if (!fast_boot) |
| 1540 | select_default_dq_dqs_settings(s); |
| 1541 | set_all_dq_dqs_dll_settings(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1542 | |
| 1543 | // RCOMP |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1544 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
| 1545 | rcomp_ddr2(s); |
| 1546 | printk(BIOS_DEBUG, "RCOMP\n"); |
| 1547 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1548 | |
| 1549 | // ODT |
| 1550 | odt_ddr2(s); |
| 1551 | printk(BIOS_DEBUG, "Done ODT\n"); |
| 1552 | |
| 1553 | // RCOMP update |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1554 | if (s->boot_path != BOOT_PATH_WARM_RESET) { |
| 1555 | while ((MCHBAR8(0x130) & 1) != 0) |
| 1556 | ; |
| 1557 | printk(BIOS_DEBUG, "Done RCOMP update\n"); |
| 1558 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1559 | |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1560 | pre_jedec_memory_map(); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1561 | |
| 1562 | // IOBUFACT |
| 1563 | if (CHANNEL_IS_POPULATED(s->dimms, 0)) { |
| 1564 | MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; |
| 1565 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7; |
| 1566 | } |
| 1567 | if (CHANNEL_IS_POPULATED(s->dimms, 1)) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1568 | if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) { |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1569 | MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; |
| 1570 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1; |
| 1571 | } |
| 1572 | MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f; |
| 1573 | MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; |
| 1574 | } |
| 1575 | |
| 1576 | // Pre jedec |
| 1577 | MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; |
| 1578 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1579 | MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27); |
| 1580 | } |
| 1581 | MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000; |
| 1582 | MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00; |
| 1583 | printk(BIOS_DEBUG, "Done pre-jedec\n"); |
| 1584 | |
| 1585 | // JEDEC reset |
Arthur Heymans | ef7e98a | 2016-12-30 21:07:18 +0100 | [diff] [blame] | 1586 | if (s->boot_path != BOOT_PATH_RESUME) |
| 1587 | jedec_ddr2(s); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1588 | |
| 1589 | printk(BIOS_DEBUG, "Done jedec steps\n"); |
| 1590 | |
| 1591 | // After JEDEC reset |
| 1592 | MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; |
| 1593 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1594 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1595 | reg32 = (2 << 18) | (3 << 13) | (5 << 8); |
Arthur Heymans | 70a1dda | 2017-03-09 01:58:24 +0100 | [diff] [blame] | 1596 | else |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1597 | reg32 = (2 << 18) | (3 << 13) | (4 << 8); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1598 | MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32; |
| 1599 | MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80; |
| 1600 | MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; |
| 1601 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1602 | MCHBAR16(0x400*ch + 0x27c) = 0x41; |
| 1603 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
| 1604 | MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe; |
| 1605 | } |
| 1606 | MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8; |
| 1607 | MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40; |
| 1608 | MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4; |
| 1609 | |
| 1610 | printk(BIOS_DEBUG, "Done post-jedec\n"); |
| 1611 | |
| 1612 | // Set DDR2 init complete |
| 1613 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1614 | MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000; |
| 1615 | } |
| 1616 | |
| 1617 | // Receive enable |
Arthur Heymans | adc571a | 2017-09-25 09:40:54 +0200 | [diff] [blame] | 1618 | sdram_program_receive_enable(s, fast_boot); |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1619 | printk(BIOS_DEBUG, "Done rcven\n"); |
| 1620 | |
| 1621 | // Finish rcven |
| 1622 | FOR_EACH_CHANNEL(ch) { |
| 1623 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe; |
| 1624 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2; |
| 1625 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4; |
| 1626 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8; |
| 1627 | } |
| 1628 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; |
| 1629 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; |
| 1630 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; |
| 1631 | |
| 1632 | // Dummy writes / reads |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1633 | if (s->boot_path == BOOT_PATH_NORMAL) { |
| 1634 | volatile u32 data; |
| 1635 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1636 | for (bank = 0; bank < 4; bank++) { |
Arthur Heymans | 1994e448 | 2017-11-04 07:52:23 +0100 | [diff] [blame] | 1637 | reg32 = test_address(ch, r) | |
Arthur Heymans | 97e13d8 | 2016-11-30 18:40:38 +0100 | [diff] [blame] | 1638 | (bank << 12); |
| 1639 | write32((u32 *)reg32, 0xffffffff); |
| 1640 | data = read32((u32 *)reg32); |
| 1641 | printk(BIOS_DEBUG, "Wrote ones,"); |
| 1642 | printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", |
| 1643 | reg32, data); |
| 1644 | write32((u32 *)reg32, 0x00000000); |
| 1645 | data = read32((u32 *)reg32); |
| 1646 | printk(BIOS_DEBUG, "Wrote zeros,"); |
| 1647 | printk(BIOS_DEBUG, " Read: [0x%08x]=0x%08x\n", |
| 1648 | reg32, data); |
| 1649 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1650 | } |
| 1651 | } |
| 1652 | printk(BIOS_DEBUG, "Done dummy reads\n"); |
| 1653 | |
| 1654 | // XXX tRD |
| 1655 | |
Arthur Heymans | 95c48cb | 2017-11-04 08:07:06 +0100 | [diff] [blame] | 1656 | if (!fast_boot) { |
| 1657 | if (s->selected_timings.mem_clk > MEM_CLOCK_667MHz) { |
| 1658 | if(do_write_training(s)) |
| 1659 | die("DQ write training failed!"); |
| 1660 | } |
| 1661 | if (do_read_training(s)) |
| 1662 | die("DQS read training failed!"); |
| 1663 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1664 | |
| 1665 | // DRADRB |
| 1666 | dradrb_ddr2(s); |
| 1667 | printk(BIOS_DEBUG, "Done DRADRB\n"); |
| 1668 | |
| 1669 | // Memory map |
| 1670 | mmap_ddr2(s); |
| 1671 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 1672 | |
| 1673 | // Enhanced mode |
| 1674 | enhanced_ddr2(s); |
| 1675 | printk(BIOS_DEBUG, "Done enhanced mode\n"); |
| 1676 | |
| 1677 | // Periodic RCOMP |
| 1678 | MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999; |
| 1679 | MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000; |
| 1680 | MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82; |
| 1681 | printk(BIOS_DEBUG, "Done PRCOMP\n"); |
| 1682 | |
| 1683 | // Power settings |
| 1684 | power_ddr2(s); |
| 1685 | printk(BIOS_DEBUG, "Done power settings\n"); |
| 1686 | |
| 1687 | // ME related |
Arthur Heymans | ddc8828 | 2017-02-27 16:27:21 +0100 | [diff] [blame] | 1688 | /* |
| 1689 | * FIXME: This locks some registers like bit1 of GGC |
| 1690 | * and is only needed in case of ME being used. |
| 1691 | */ |
| 1692 | if (ME_UMA_SIZEMB != 0) { |
| 1693 | if (RANK_IS_POPULATED(s->dimms, 0, 0) |
| 1694 | || RANK_IS_POPULATED(s->dimms, 1, 0)) |
| 1695 | MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); |
| 1696 | if (RANK_IS_POPULATED(s->dimms, 0, 1) |
| 1697 | || RANK_IS_POPULATED(s->dimms, 1, 1)) |
| 1698 | MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); |
| 1699 | MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); |
Damien Zammit | d63115d | 2016-01-22 19:11:44 +1100 | [diff] [blame] | 1700 | } |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1701 | |
| 1702 | printk(BIOS_DEBUG, "Done ddr2\n"); |
| 1703 | } |