Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_TIGERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Tigerlake support |
| 5 | |
Jeremy Soller | 6b1b9ad | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 6 | config SOC_INTEL_TIGERLAKE_PCH_H |
| 7 | bool |
| 8 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 9 | if SOC_INTEL_TIGERLAKE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 10 | |
| 11 | config CPU_SPECIFIC_OPTIONS |
| 12 | def_bool y |
| 13 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | 8e035e3 | 2021-06-22 12:58:20 +0200 | [diff] [blame] | 14 | select ARCH_X86 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 15 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 16 | select CACHE_MRC_SETTINGS |
Alex Levin | f3668fc | 2020-06-11 20:09:45 -0700 | [diff] [blame] | 17 | select CPU_INTEL_COMMON |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 18 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | 5307f12 | 2021-09-19 00:32:37 +0200 | [diff] [blame] | 19 | select CPU_SUPPORTS_INTEL_TME |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 20 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 21 | select DRIVERS_USB_ACPI |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 22 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Karthikeyan Ramasubramanian | 6abee84 | 2020-06-16 23:29:28 -0600 | [diff] [blame] | 23 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 24 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 25 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 26 | select GENERIC_GPIO_LIB |
| 27 | select HAVE_FSP_GOP |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 28 | select HAVE_INTEL_FSP_REPO |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 29 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 30 | select HAVE_SMI_HANDLER |
| 31 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 32 | select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM |
Shreesh Chhabbi | 860c684 | 2020-12-03 15:06:20 -0800 | [diff] [blame] | 33 | select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED |
Shreesh Chhabbi | 42b1d3f | 2020-11-05 12:06:29 -0800 | [diff] [blame] | 34 | select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED |
Subrata Banik | ad08265 | 2021-07-23 16:15:57 +0530 | [diff] [blame] | 35 | select SF_MASK_2WAYS_PER_BIT if INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 36 | select INTEL_GMA_ACPI |
| 37 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 38 | select MP_SERVICES_PPI_V1 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 39 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 40 | select PARALLEL_MP_AP_WORK |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 41 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 42 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
| 43 | select SOC_INTEL_COMMON |
| 44 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 45 | select SOC_INTEL_COMMON_BLOCK |
| 46 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Tim Wawrzynczak | 72d9402 | 2021-07-01 08:25:11 -0600 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP |
| 50 | select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 52 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 55 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Tim Wawrzynczak | c5316ec | 2020-05-29 15:20:56 -0600 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_DTT |
Nick Vaccaro | ef8258a | 2019-12-09 22:11:33 -0800 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Duncan Laurie | 7d97136 | 2020-11-05 10:09:58 -0800 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 61 | select SOC_INTEL_COMMON_BLOCK_HDA |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Furquan Shaikh | f06d046 | 2020-12-31 21:15:34 -0800 | [diff] [blame] | 63 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Duncan Laurie | e997d85 | 2020-10-10 00:18:08 +0000 | [diff] [blame] | 64 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Lean Sheng Tan | 7502000 | 2021-06-30 01:47:48 -0700 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_PMC_EPOC |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 66 | select SOC_INTEL_COMMON_BLOCK_SA |
| 67 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 68 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Duncan Laurie | 6f58b99 | 2020-08-28 19:44:42 +0000 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 70 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 71 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Karthikeyan Ramasubramanian | fa9e8f9 | 2020-11-04 22:22:46 -0700 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 73 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 74 | select SOC_INTEL_COMMON_PCH_BASE |
| 75 | select SOC_INTEL_COMMON_RESET |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 76 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Tim Wawrzynczak | 25d2452 | 2021-06-17 12:44:06 -0600 | [diff] [blame] | 77 | select SOC_INTEL_CSE_SET_EOP |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 78 | select SSE2 |
| 79 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 80 | select TSC_MONOTONIC_TIMER |
| 81 | select UDELAY_TSC |
| 82 | select UDK_2017_BINDING |
| 83 | select DISPLAY_FSP_VERSION_INFO |
| 84 | select HECI_DISABLE_USING_SMM |
| 85 | |
Andy Pont | d2f52ff | 2021-06-08 10:30:35 +0100 | [diff] [blame] | 86 | config MAX_CPUS |
| 87 | int |
Tim Crawford | f496286 | 2021-08-30 13:08:36 -0600 | [diff] [blame] | 88 | default 16 if SOC_INTEL_TIGERLAKE_PCH_H |
Andy Pont | d2f52ff | 2021-06-08 10:30:35 +0100 | [diff] [blame] | 89 | default 8 |
| 90 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 91 | config DCACHE_RAM_BASE |
| 92 | default 0xfef00000 |
| 93 | |
| 94 | config DCACHE_RAM_SIZE |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 95 | default 0x80000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 96 | help |
| 97 | The size of the cache-as-ram region required during bootblock |
| 98 | and/or romstage. |
| 99 | |
| 100 | config DCACHE_BSP_STACK_SIZE |
| 101 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 102 | default 0x40400 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 103 | help |
| 104 | The amount of anticipated stack usage in CAR by bootblock and |
| 105 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 106 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 107 | (~1KiB). |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 108 | |
| 109 | config FSP_TEMP_RAM_SIZE |
| 110 | hex |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 111 | default 0x20000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 112 | help |
| 113 | The amount of anticipated heap usage in CAR by FSP. |
| 114 | Refer to Platform FSP integration guide document to know |
| 115 | the exact FSP requirement for Heap setup. |
| 116 | |
Duncan Laurie | a5bb31f | 2020-07-29 16:31:18 -0700 | [diff] [blame] | 117 | config CHIPSET_DEVICETREE |
| 118 | string |
Jeremy Soller | 6b1b9ad | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 119 | default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H |
Duncan Laurie | a5bb31f | 2020-07-29 16:31:18 -0700 | [diff] [blame] | 120 | default "soc/intel/tigerlake/chipset.cb" |
| 121 | |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 122 | config EXT_BIOS_WIN_BASE |
| 123 | default 0xf8000000 |
| 124 | |
| 125 | config EXT_BIOS_WIN_SIZE |
| 126 | default 0x2000000 |
| 127 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 128 | config IFD_CHIPSET |
| 129 | string |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 130 | default "tgl" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 131 | |
| 132 | config IED_REGION_SIZE |
| 133 | hex |
| 134 | default 0x400000 |
| 135 | |
| 136 | config HEAP_SIZE |
| 137 | hex |
Duncan Laurie | aab226c | 2020-06-08 17:36:21 -0700 | [diff] [blame] | 138 | default 0x10000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 139 | |
| 140 | config MAX_ROOT_PORTS |
| 141 | int |
Jeremy Soller | 6b1b9ad | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 142 | default 24 if SOC_INTEL_TIGERLAKE_PCH_H |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 143 | default 12 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 144 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 145 | config MAX_PCIE_CLOCK_SRC |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 146 | int |
Jeremy Soller | 6b1b9ad | 2021-08-12 10:49:58 -0600 | [diff] [blame] | 147 | default 16 if SOC_INTEL_TIGERLAKE_PCH_H |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 148 | default 7 |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 149 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 150 | config SMM_TSEG_SIZE |
| 151 | hex |
| 152 | default 0x800000 |
| 153 | |
| 154 | config SMM_RESERVED_SIZE |
| 155 | hex |
| 156 | default 0x200000 |
| 157 | |
| 158 | config PCR_BASE_ADDRESS |
| 159 | hex |
| 160 | default 0xfd000000 |
| 161 | help |
| 162 | This option allows you to select MMIO Base Address of sideband bus. |
| 163 | |
Shelley Chen | 4e9bb33 | 2021-10-20 15:43:45 -0700 | [diff] [blame] | 164 | config ECAM_MMCONF_BASE_ADDRESS |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 165 | default 0xc0000000 |
| 166 | |
| 167 | config CPU_BCLK_MHZ |
| 168 | int |
| 169 | default 100 |
| 170 | |
| 171 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 172 | int |
| 173 | default 120 |
| 174 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 175 | config CPU_XTAL_HZ |
| 176 | default 38400000 |
| 177 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 178 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 179 | int |
| 180 | default 133 |
| 181 | |
| 182 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 183 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 184 | default 4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 185 | |
| 186 | config SOC_INTEL_I2C_DEV_MAX |
| 187 | int |
| 188 | default 6 |
| 189 | |
Sean Rhodes | 5622666 | 2021-11-08 21:34:34 +0000 | [diff] [blame] | 190 | config SOC_INTEL_TIGERLAKE_S3 |
| 191 | bool |
| 192 | default n |
| 193 | help |
| 194 | Select if using S3 instead of S0ix to disable D3Cold |
| 195 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 196 | config SOC_INTEL_UART_DEV_MAX |
| 197 | int |
| 198 | default 3 |
| 199 | |
| 200 | config CONSOLE_UART_BASE_ADDRESS |
| 201 | hex |
Bora Guvendik | c3c3e45 | 2020-11-13 21:35:19 -0800 | [diff] [blame] | 202 | default 0xfe03e000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 203 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 204 | |
| 205 | # Clock divider parameters for 115200 baud rate |
Ravi Sarawadi | 3838701 | 2019-12-19 15:04:58 -0800 | [diff] [blame] | 206 | # Baudrate = (UART source clcok * M) /(N *16) |
| 207 | # TGL UART source clock: 120MHz |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 208 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 209 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 210 | default 0x25a |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 211 | |
| 212 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 213 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 214 | default 0x7fff |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 215 | |
Jes Klinke | e046b71 | 2020-08-19 14:01:30 -0700 | [diff] [blame] | 216 | # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection |
| 217 | # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. |
| 218 | config TPM_CR50 |
| 219 | select CR50_USE_LONG_INTERRUPT_PULSES |
| 220 | |
Srinidhi N Kaushik | 74c16d0 | 2020-11-04 11:29:33 -0800 | [diff] [blame] | 221 | config VBT_DATA_SIZE_KB |
| 222 | int |
| 223 | default 9 |
| 224 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 225 | config VBOOT |
| 226 | select VBOOT_SEPARATE_VERSTAGE |
| 227 | select VBOOT_MUST_REQUEST_DISPLAY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 228 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 229 | select VBOOT_VBNV_CMOS |
| 230 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 231 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 232 | config CBFS_SIZE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 233 | default 0x200000 |
| 234 | |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 235 | config FSP_TYPE_IOT |
| 236 | bool |
| 237 | default n |
| 238 | help |
| 239 | This option allows to select FSP IOT type from 3rdparty/fsp repo |
| 240 | |
| 241 | config FSP_TYPE_CLIENT |
| 242 | bool |
| 243 | default !FSP_TYPE_IOT |
| 244 | help |
| 245 | This option allows to select FSP CLIENT type from 3rdparty/fsp repo |
| 246 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 247 | config FSP_HEADER_PATH |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 248 | default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT |
| 249 | default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 250 | |
| 251 | config FSP_FD_PATH |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 252 | default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT |
| 253 | default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 254 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 255 | config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT |
| 256 | int "Debug Consent for TGL" |
| 257 | # USB DBC is more common for developers so make this default to 3 if |
| 258 | # SOC_INTEL_DEBUG_CONSENT=y |
| 259 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 260 | default 0 |
| 261 | help |
| 262 | This is to control debug interface on SOC. |
| 263 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 264 | PlatformDebugConsent in FspmUpd.h has the details. |
| 265 | |
| 266 | Desired platform debug type are |
| 267 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 268 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 269 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 270 | |
| 271 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 272 | hex |
Anil Kumar | 033038f | 2020-09-08 16:18:45 -0700 | [diff] [blame] | 273 | default 0x2000 |
Brandon Breitenstein | 99b38a9 | 2019-12-19 23:12:58 -0800 | [diff] [blame] | 274 | |
Furquan Shaikh | f06d046 | 2020-12-31 21:15:34 -0800 | [diff] [blame] | 275 | config DATA_BUS_WIDTH |
| 276 | int |
| 277 | default 128 |
| 278 | |
| 279 | config DIMMS_PER_CHANNEL |
| 280 | int |
| 281 | default 2 |
| 282 | |
| 283 | config MRC_CHANNEL_WIDTH |
| 284 | int |
| 285 | default 16 |
| 286 | |
Furquan Shaikh | bee831e | 2021-08-24 13:42:05 -0700 | [diff] [blame] | 287 | # Intel recommends reserving the following resources per USB4 root port, |
| 288 | # from TGL BIOS Spec (doc #611569) Revision 0.7.6 Section 7.2.5.1.5 |
| 289 | # - 42 buses |
| 290 | # - 194 MiB Non-prefetchable memory |
| 291 | # - 448 MiB Prefetchable memory |
| 292 | if SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 293 | |
| 294 | config PCIEXP_HOTPLUG_BUSES |
| 295 | default 42 |
| 296 | |
| 297 | config PCIEXP_HOTPLUG_MEM |
| 298 | default 0xc200000 # 194 MiB |
| 299 | |
| 300 | config PCIEXP_HOTPLUG_PREFETCH_MEM |
| 301 | default 0x1c000000 # 448 MiB |
| 302 | |
| 303 | endif # SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES |
| 304 | |
Tim Crawford | 1724b57 | 2021-09-21 21:50:49 -0600 | [diff] [blame] | 305 | config INTEL_GMA_BCLV_OFFSET |
| 306 | default 0xc8258 |
| 307 | |
| 308 | config INTEL_GMA_BCLV_WIDTH |
| 309 | default 32 |
| 310 | |
| 311 | config INTEL_GMA_BCLM_OFFSET |
| 312 | default 0xc8254 |
| 313 | |
| 314 | config INTEL_GMA_BCLM_WIDTH |
| 315 | default 32 |
| 316 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 317 | endif |