soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index e71586d..77d22ca 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -72,13 +72,12 @@
config DCACHE_BSP_STACK_SIZE
hex
- default 0x40400 if SOC_INTEL_TIGERLAKE
- default 0x30400 if SOC_INTEL_JASPERLAKE
+ default 0x40400
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be
- sum of FSP-M stack requirement (256KiB for TGL, 192KiB for JSL) and CB romstage
- stack requirement (~1KiB).
+ sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement
+ (~1KiB).
config FSP_TEMP_RAM_SIZE
hex
@@ -90,8 +89,7 @@
config IFD_CHIPSET
string
- default "jsl" if SOC_INTEL_JASPERLAKE
- default "tgl" if SOC_INTEL_TIGERLAKE
+ default "tgl"
config IED_REGION_SIZE
hex
@@ -103,13 +101,11 @@
config MAX_ROOT_PORTS
int
- default 8 if SOC_INTEL_JASPERLAKE
- default 12 if SOC_INTEL_TIGERLAKE
+ default 12
config MAX_PCIE_CLOCKS
int
- default 7 if SOC_INTEL_TIGERLAKE
- default 6 if SOC_INTEL_JASPERLAKE
+ default 7
config SMM_TSEG_SIZE
hex
@@ -143,8 +139,7 @@
config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
int
- default 3 if SOC_INTEL_JASPERLAKE
- default 4 if SOC_INTEL_TIGERLAKE
+ default 4
config SOC_INTEL_I2C_DEV_MAX
int
@@ -162,16 +157,13 @@
# Clock divider parameters for 115200 baud rate
# Baudrate = (UART source clcok * M) /(N *16)
# TGL UART source clock: 120MHz
-# JSL UART source clock: 100MHz
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
- default 0x30 if SOC_INTEL_JASPERLAKE
- default 0x25a if SOC_INTEL_TIGERLAKE
+ default 0x25a
config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
hex
- default 0xc35 if SOC_INTEL_JASPERLAKE
- default 0x7fff if SOC_INTEL_TIGERLAKE
+ default 0x7fff
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
@@ -193,14 +185,12 @@
config FSP_HEADER_PATH
string "Location of FSP headers"
- default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" if SOC_INTEL_JASPERLAKE
- default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/" if SOC_INTEL_TIGERLAKE
+ default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/"
config FSP_FD_PATH
string
depends on FSP_USE_REPO
- default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" if SOC_INTEL_JASPERLAKE
- default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd" if SOC_INTEL_TIGERLAKE
+ default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd"
config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
int "Debug Consent for TGL"