soc/intel/tigerlake: Add PCH-H chipset devicetree
Based on the base TGL devicetree, add one specific to TGL-H that adds
the additional supported devices.
Introduces a new Kconfig for selecting the PCH support.
Reference:
- Intel doc 615985
Change-Id: Icc130461edcecc4a3e1f6544ccb905608881d2f7
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index e337e34..3defba4 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -3,6 +3,9 @@
help
Intel Tigerlake support
+config SOC_INTEL_TIGERLAKE_PCH_H
+ bool
+
if SOC_INTEL_TIGERLAKE
config CPU_SPECIFIC_OPTIONS
@@ -112,6 +115,7 @@
config CHIPSET_DEVICETREE
string
+ default "soc/intel/tigerlake/chipset_pch_h.cb" if SOC_INTEL_TIGERLAKE_PCH_H
default "soc/intel/tigerlake/chipset.cb"
config EXT_BIOS_WIN_BASE
@@ -134,10 +138,12 @@
config MAX_ROOT_PORTS
int
+ default 24 if SOC_INTEL_TIGERLAKE_PCH_H
default 12
config MAX_PCIE_CLOCK_SRC
int
+ default 16 if SOC_INTEL_TIGERLAKE_PCH_H
default 7
config SMM_TSEG_SIZE