Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 2 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 5 | #include <assert.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
| 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
| 12 | #include <device/pci_ops.h> |
| 13 | #include <intelblocks/cse.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 14 | #include <option.h> |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 15 | #include <security/vboot/misc.h> |
| 16 | #include <security/vboot/vboot_common.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 17 | #include <soc/intel/common/reset.h> |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 18 | #include <soc/iomap.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 19 | #include <soc/pci_devs.h> |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 20 | #include <soc/me.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 21 | #include <string.h> |
| 22 | #include <timer.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 23 | #include <types.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 24 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 25 | #define MAX_HECI_MESSAGE_RETRY_COUNT 5 |
| 26 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 27 | /* Wait up to 15 sec for HECI to get ready */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 28 | #define HECI_DELAY_READY_MS (15 * 1000) |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 29 | /* Wait up to 100 usec between circular buffer polls */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 30 | #define HECI_DELAY_US 100 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 31 | /* Wait up to 5 sec for CSE to chew something we sent */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 32 | #define HECI_SEND_TIMEOUT_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 33 | /* Wait up to 5 sec for CSE to blurp a reply */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 34 | #define HECI_READ_TIMEOUT_MS (5 * 1000) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 35 | /* Wait up to 1 ms for CSE CIP */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 36 | #define HECI_CIP_TIMEOUT_US 1000 |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 37 | /* Wait up to 5 seconds for CSE to boot from RO(BP1) */ |
| 38 | #define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 39 | |
| 40 | #define SLOT_SIZE sizeof(uint32_t) |
| 41 | |
| 42 | #define MMIO_CSE_CB_WW 0x00 |
| 43 | #define MMIO_HOST_CSR 0x04 |
| 44 | #define MMIO_CSE_CB_RW 0x08 |
| 45 | #define MMIO_CSE_CSR 0x0c |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 46 | #define MMIO_CSE_DEVIDLE 0x800 |
| 47 | #define CSE_DEV_IDLE (1 << 2) |
| 48 | #define CSE_DEV_CIP (1 << 0) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 49 | |
| 50 | #define CSR_IE (1 << 0) |
| 51 | #define CSR_IS (1 << 1) |
| 52 | #define CSR_IG (1 << 2) |
| 53 | #define CSR_READY (1 << 3) |
| 54 | #define CSR_RESET (1 << 4) |
| 55 | #define CSR_RP_START 8 |
| 56 | #define CSR_RP (((1 << 8) - 1) << CSR_RP_START) |
| 57 | #define CSR_WP_START 16 |
| 58 | #define CSR_WP (((1 << 8) - 1) << CSR_WP_START) |
| 59 | #define CSR_CBD_START 24 |
| 60 | #define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) |
| 61 | |
| 62 | #define MEI_HDR_IS_COMPLETE (1 << 31) |
| 63 | #define MEI_HDR_LENGTH_START 16 |
| 64 | #define MEI_HDR_LENGTH_SIZE 9 |
| 65 | #define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ |
| 66 | << MEI_HDR_LENGTH_START) |
| 67 | #define MEI_HDR_HOST_ADDR_START 8 |
| 68 | #define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) |
| 69 | #define MEI_HDR_CSE_ADDR_START 0 |
| 70 | #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) |
| 71 | |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 72 | /* Get HECI BAR 0 from PCI configuration space */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 73 | static uintptr_t get_cse_bar(pci_devfn_t dev) |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 74 | { |
| 75 | uintptr_t bar; |
| 76 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 77 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 78 | assert(bar != 0); |
| 79 | /* |
| 80 | * Bits 31-12 are the base address as per EDS for SPI, |
| 81 | * Don't care about 0-11 bit |
| 82 | */ |
| 83 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 84 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 85 | |
| 86 | /* |
| 87 | * Initialize the device with provided temporary BAR. If BAR is 0 use a |
| 88 | * default. This is intended for pre-mem usage only where BARs haven't been |
| 89 | * assigned yet and devices are not enabled. |
| 90 | */ |
| 91 | void heci_init(uintptr_t tempbar) |
| 92 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 93 | pci_devfn_t dev = PCH_DEV_CSE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 94 | |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 95 | u16 pcireg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 96 | |
| 97 | /* Assume it is already initialized, nothing else to do */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 98 | if (get_cse_bar(dev)) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 99 | return; |
| 100 | |
| 101 | /* Use default pre-ram bar */ |
| 102 | if (!tempbar) |
| 103 | tempbar = HECI1_BASE_ADDRESS; |
| 104 | |
| 105 | /* Assign Resources to HECI1 */ |
| 106 | /* Clear BIT 1-2 of Command Register */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 107 | pcireg = pci_read_config16(dev, PCI_COMMAND); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 108 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 109 | pci_write_config16(dev, PCI_COMMAND, pcireg); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 110 | |
| 111 | /* Program Temporary BAR for HECI1 */ |
| 112 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); |
| 113 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); |
| 114 | |
| 115 | /* Enable Bus Master and MMIO Space */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 116 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Sridhar Siricilla | cb2fd20 | 2021-06-09 19:27:06 +0530 | [diff] [blame] | 117 | |
| 118 | /* Trigger HECI Reset and make Host ready for communication with CSE */ |
| 119 | heci_reset(); |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 120 | } |
| 121 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 122 | static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 123 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 124 | return read32p(get_cse_bar(dev) + offset); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 125 | } |
| 126 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 127 | static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 128 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 129 | return write32p(get_cse_bar(dev) + offset, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | static uint32_t read_cse_csr(void) |
| 133 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 134 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 135 | } |
| 136 | |
| 137 | static uint32_t read_host_csr(void) |
| 138 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 139 | return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 140 | } |
| 141 | |
| 142 | static void write_host_csr(uint32_t data) |
| 143 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 144 | write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 145 | } |
| 146 | |
| 147 | static size_t filled_slots(uint32_t data) |
| 148 | { |
| 149 | uint8_t wp, rp; |
| 150 | rp = data >> CSR_RP_START; |
| 151 | wp = data >> CSR_WP_START; |
| 152 | return (uint8_t) (wp - rp); |
| 153 | } |
| 154 | |
| 155 | static size_t cse_filled_slots(void) |
| 156 | { |
| 157 | return filled_slots(read_cse_csr()); |
| 158 | } |
| 159 | |
| 160 | static size_t host_empty_slots(void) |
| 161 | { |
| 162 | uint32_t csr; |
| 163 | csr = read_host_csr(); |
| 164 | |
| 165 | return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr); |
| 166 | } |
| 167 | |
| 168 | static void clear_int(void) |
| 169 | { |
| 170 | uint32_t csr; |
| 171 | csr = read_host_csr(); |
| 172 | csr |= CSR_IS; |
| 173 | write_host_csr(csr); |
| 174 | } |
| 175 | |
| 176 | static uint32_t read_slot(void) |
| 177 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 178 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 179 | } |
| 180 | |
| 181 | static void write_slot(uint32_t val) |
| 182 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 183 | write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | static int wait_write_slots(size_t cnt) |
| 187 | { |
| 188 | struct stopwatch sw; |
| 189 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 190 | stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 191 | while (host_empty_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 192 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 193 | if (stopwatch_expired(&sw)) { |
| 194 | printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); |
| 195 | return 0; |
| 196 | } |
| 197 | } |
| 198 | return 1; |
| 199 | } |
| 200 | |
| 201 | static int wait_read_slots(size_t cnt) |
| 202 | { |
| 203 | struct stopwatch sw; |
| 204 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 205 | stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 206 | while (cse_filled_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 207 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 208 | if (stopwatch_expired(&sw)) { |
| 209 | printk(BIOS_ERR, "HECI: timed out reading answer!\n"); |
| 210 | return 0; |
| 211 | } |
| 212 | } |
| 213 | return 1; |
| 214 | } |
| 215 | |
| 216 | /* get number of full 4-byte slots */ |
| 217 | static size_t bytes_to_slots(size_t bytes) |
| 218 | { |
| 219 | return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; |
| 220 | } |
| 221 | |
| 222 | static int cse_ready(void) |
| 223 | { |
| 224 | uint32_t csr; |
| 225 | csr = read_cse_csr(); |
| 226 | return csr & CSR_READY; |
| 227 | } |
| 228 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 229 | static bool cse_check_hfs1_com(int mode) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 230 | { |
| 231 | union me_hfsts1 hfs1; |
| 232 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 233 | return hfs1.fields.operation_mode == mode; |
| 234 | } |
| 235 | |
| 236 | bool cse_is_hfs1_cws_normal(void) |
| 237 | { |
| 238 | union me_hfsts1 hfs1; |
| 239 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 240 | if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL) |
| 241 | return true; |
| 242 | return false; |
| 243 | } |
| 244 | |
| 245 | bool cse_is_hfs1_com_normal(void) |
| 246 | { |
| 247 | return cse_check_hfs1_com(ME_HFS1_COM_NORMAL); |
| 248 | } |
| 249 | |
| 250 | bool cse_is_hfs1_com_secover_mei_msg(void) |
| 251 | { |
| 252 | return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); |
| 253 | } |
| 254 | |
| 255 | bool cse_is_hfs1_com_soft_temp_disable(void) |
| 256 | { |
| 257 | return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 258 | } |
| 259 | |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 260 | /* |
| 261 | * TGL HFSTS1.spi_protection_mode bit replaces the previous |
| 262 | * `manufacturing mode (mfg_mode)` without changing the offset and purpose |
| 263 | * of this bit. |
| 264 | * |
| 265 | * Using HFSTS1.mfg_mode to get the SPI protection status for all PCH. |
| 266 | * mfg_mode = 0 means SPI protection in on. |
| 267 | * mfg_mode = 1 means SPI is unprotected. |
| 268 | */ |
| 269 | bool cse_is_hfs1_spi_protected(void) |
| 270 | { |
| 271 | union me_hfsts1 hfs1; |
| 272 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 273 | return !hfs1.fields.mfg_mode; |
| 274 | } |
| 275 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 276 | bool cse_is_hfs3_fw_sku_lite(void) |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 277 | { |
| 278 | union me_hfsts3 hfs3; |
| 279 | hfs3.data = me_read_config32(PCI_ME_HFSTS3); |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 280 | return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE; |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 281 | } |
| 282 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 283 | /* Makes the host ready to communicate with CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 284 | void cse_set_host_ready(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 285 | { |
| 286 | uint32_t csr; |
| 287 | csr = read_host_csr(); |
| 288 | csr &= ~CSR_RESET; |
| 289 | csr |= (CSR_IG | CSR_READY); |
| 290 | write_host_csr(csr); |
| 291 | } |
| 292 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 293 | /* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */ |
| 294 | uint8_t cse_wait_sec_override_mode(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 295 | { |
| 296 | struct stopwatch sw; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 297 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 298 | while (!cse_is_hfs1_com_secover_mei_msg()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 299 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 300 | if (stopwatch_expired(&sw)) { |
| 301 | printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n"); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 302 | return 0; |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 303 | } |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 304 | } |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 305 | printk(BIOS_DEBUG, "HECI: CSE took %lu ms to enter security override mode\n", |
| 306 | stopwatch_duration_msecs(&sw)); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 307 | return 1; |
| 308 | } |
| 309 | |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 310 | /* |
| 311 | * Polls for CSE's current operation mode 'Soft Temporary Disable'. |
| 312 | * The CSE enters the current operation mode when it boots from RO(BP1). |
| 313 | */ |
| 314 | uint8_t cse_wait_com_soft_temp_disable(void) |
| 315 | { |
| 316 | struct stopwatch sw; |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 317 | stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 318 | while (!cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 319 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 320 | if (stopwatch_expired(&sw)) { |
| 321 | printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); |
| 322 | return 0; |
| 323 | } |
| 324 | } |
| 325 | printk(BIOS_SPEW, "HECI: CSE took %lu ms to boot from RO\n", |
| 326 | stopwatch_duration_msecs(&sw)); |
| 327 | return 1; |
| 328 | } |
| 329 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 330 | static int wait_heci_ready(void) |
| 331 | { |
| 332 | struct stopwatch sw; |
| 333 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 334 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 335 | while (!cse_ready()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 336 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 337 | if (stopwatch_expired(&sw)) |
| 338 | return 0; |
| 339 | } |
| 340 | |
| 341 | return 1; |
| 342 | } |
| 343 | |
| 344 | static void host_gen_interrupt(void) |
| 345 | { |
| 346 | uint32_t csr; |
| 347 | csr = read_host_csr(); |
| 348 | csr |= CSR_IG; |
| 349 | write_host_csr(csr); |
| 350 | } |
| 351 | |
| 352 | static size_t hdr_get_length(uint32_t hdr) |
| 353 | { |
| 354 | return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START; |
| 355 | } |
| 356 | |
| 357 | static int |
| 358 | send_one_message(uint32_t hdr, const void *buff) |
| 359 | { |
| 360 | size_t pend_len, pend_slots, remainder, i; |
| 361 | uint32_t tmp; |
| 362 | const uint32_t *p = buff; |
| 363 | |
| 364 | /* Get space for the header */ |
| 365 | if (!wait_write_slots(1)) |
| 366 | return 0; |
| 367 | |
| 368 | /* First, write header */ |
| 369 | write_slot(hdr); |
| 370 | |
| 371 | pend_len = hdr_get_length(hdr); |
| 372 | pend_slots = bytes_to_slots(pend_len); |
| 373 | |
| 374 | if (!wait_write_slots(pend_slots)) |
| 375 | return 0; |
| 376 | |
| 377 | /* Write the body in whole slots */ |
| 378 | i = 0; |
| 379 | while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { |
| 380 | write_slot(*p++); |
| 381 | i += SLOT_SIZE; |
| 382 | } |
| 383 | |
| 384 | remainder = pend_len % SLOT_SIZE; |
| 385 | /* Pad to 4 bytes not touching caller's buffer */ |
| 386 | if (remainder) { |
| 387 | memcpy(&tmp, p, remainder); |
| 388 | write_slot(tmp); |
| 389 | } |
| 390 | |
| 391 | host_gen_interrupt(); |
| 392 | |
| 393 | /* Make sure nothing bad happened during transmission */ |
| 394 | if (!cse_ready()) |
| 395 | return 0; |
| 396 | |
| 397 | return pend_len; |
| 398 | } |
| 399 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 400 | /* |
| 401 | * Send message msg of size len to host from host_addr to cse_addr. |
| 402 | * Returns 1 on success and 0 otherwise. |
| 403 | * In case of error heci_reset() may be required. |
| 404 | */ |
| 405 | static int |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 406 | heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) |
| 407 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 408 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 409 | uint32_t csr, hdr; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 410 | size_t sent, remaining, cb_size, max_length; |
| 411 | const uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 412 | |
| 413 | if (!msg || !len) |
| 414 | return 0; |
| 415 | |
| 416 | clear_int(); |
| 417 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 418 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 419 | p = msg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 420 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 421 | if (!wait_heci_ready()) { |
| 422 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 423 | continue; |
| 424 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 425 | |
Subrata Banik | 4a722f5 | 2017-11-13 14:56:42 +0530 | [diff] [blame] | 426 | csr = read_host_csr(); |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 427 | cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE; |
| 428 | /* |
| 429 | * Reserve one slot for the header. Limit max message |
| 430 | * length by 9 bits that are available in the header. |
| 431 | */ |
| 432 | max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) |
| 433 | - SLOT_SIZE; |
| 434 | remaining = len; |
| 435 | |
| 436 | /* |
| 437 | * Fragment the message into smaller messages not exceeding |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 438 | * useful circular buffer length. Mark last message complete. |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 439 | */ |
| 440 | do { |
| 441 | hdr = MIN(max_length, remaining) |
| 442 | << MEI_HDR_LENGTH_START; |
| 443 | hdr |= client_addr << MEI_HDR_CSE_ADDR_START; |
| 444 | hdr |= host_addr << MEI_HDR_HOST_ADDR_START; |
| 445 | hdr |= (MIN(max_length, remaining) == remaining) ? |
Lee Leahy | 68ab0b5 | 2017-03-10 13:42:34 -0800 | [diff] [blame] | 446 | MEI_HDR_IS_COMPLETE : 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 447 | sent = send_one_message(hdr, p); |
| 448 | p += sent; |
| 449 | remaining -= sent; |
| 450 | } while (remaining > 0 && sent != 0); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 451 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 452 | if (!remaining) |
| 453 | return 1; |
| 454 | } |
| 455 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 456 | } |
| 457 | |
| 458 | static size_t |
| 459 | recv_one_message(uint32_t *hdr, void *buff, size_t maxlen) |
| 460 | { |
| 461 | uint32_t reg, *p = buff; |
| 462 | size_t recv_slots, recv_len, remainder, i; |
| 463 | |
| 464 | /* first get the header */ |
| 465 | if (!wait_read_slots(1)) |
| 466 | return 0; |
| 467 | |
| 468 | *hdr = read_slot(); |
| 469 | recv_len = hdr_get_length(*hdr); |
| 470 | |
| 471 | if (!recv_len) |
| 472 | printk(BIOS_WARNING, "HECI: message is zero-sized\n"); |
| 473 | |
| 474 | recv_slots = bytes_to_slots(recv_len); |
| 475 | |
| 476 | i = 0; |
| 477 | if (recv_len > maxlen) { |
| 478 | printk(BIOS_ERR, "HECI: response is too big\n"); |
| 479 | return 0; |
| 480 | } |
| 481 | |
| 482 | /* wait for the rest of messages to arrive */ |
| 483 | wait_read_slots(recv_slots); |
| 484 | |
| 485 | /* fetch whole slots first */ |
| 486 | while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) { |
| 487 | *p++ = read_slot(); |
| 488 | i += SLOT_SIZE; |
| 489 | } |
| 490 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 491 | /* |
| 492 | * If ME is not ready, something went wrong and |
| 493 | * we received junk |
| 494 | */ |
| 495 | if (!cse_ready()) |
| 496 | return 0; |
| 497 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 498 | remainder = recv_len % SLOT_SIZE; |
| 499 | |
| 500 | if (remainder) { |
| 501 | reg = read_slot(); |
| 502 | memcpy(p, ®, remainder); |
| 503 | } |
| 504 | |
| 505 | return recv_len; |
| 506 | } |
| 507 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 508 | /* |
| 509 | * Receive message into buff not exceeding maxlen. Message is considered |
| 510 | * successfully received if a 'complete' indication is read from ME side |
| 511 | * and there was enough space in the buffer to fit that message. maxlen |
| 512 | * is updated with size of message that was received. Returns 0 on failure |
| 513 | * and 1 on success. |
| 514 | * In case of error heci_reset() may be required. |
| 515 | */ |
| 516 | static int heci_receive(void *buff, size_t *maxlen) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 517 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 518 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 519 | size_t left, received; |
| 520 | uint32_t hdr = 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 521 | uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 522 | |
| 523 | if (!buff || !maxlen || !*maxlen) |
| 524 | return 0; |
| 525 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 526 | clear_int(); |
| 527 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 528 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 529 | p = buff; |
| 530 | left = *maxlen; |
| 531 | |
| 532 | if (!wait_heci_ready()) { |
| 533 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 534 | continue; |
| 535 | } |
| 536 | |
| 537 | /* |
| 538 | * Receive multiple packets until we meet one marked |
| 539 | * complete or we run out of space in caller-provided buffer. |
| 540 | */ |
| 541 | do { |
| 542 | received = recv_one_message(&hdr, p, left); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 543 | if (!received) { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 544 | printk(BIOS_ERR, "HECI: Failed to receive!\n"); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 545 | return 0; |
| 546 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 547 | left -= received; |
| 548 | p += received; |
| 549 | /* If we read out everything ping to send more */ |
| 550 | if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots()) |
| 551 | host_gen_interrupt(); |
| 552 | } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); |
| 553 | |
| 554 | if ((hdr & MEI_HDR_IS_COMPLETE) && received) { |
| 555 | *maxlen = p - (uint8_t *) buff; |
| 556 | return 1; |
| 557 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 558 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 559 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 560 | } |
| 561 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 562 | int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, |
| 563 | uint8_t cse_addr) |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 564 | { |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 565 | if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr)) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 566 | printk(BIOS_ERR, "HECI: send Failed\n"); |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | if (rcv_msg != NULL) { |
| 571 | if (!heci_receive(rcv_msg, rcv_sz)) { |
| 572 | printk(BIOS_ERR, "HECI: receive Failed\n"); |
| 573 | return 0; |
| 574 | } |
| 575 | } |
| 576 | return 1; |
| 577 | } |
| 578 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 579 | /* |
| 580 | * Attempt to reset the device. This is useful when host and ME are out |
| 581 | * of sync during transmission or ME didn't understand the message. |
| 582 | */ |
| 583 | int heci_reset(void) |
| 584 | { |
| 585 | uint32_t csr; |
| 586 | |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 587 | /* Clear post code to prevent eventlog entry from unknown code. */ |
| 588 | post_code(0); |
| 589 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 590 | /* Send reset request */ |
| 591 | csr = read_host_csr(); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 592 | csr |= (CSR_RESET | CSR_IG); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 593 | write_host_csr(csr); |
| 594 | |
| 595 | if (wait_heci_ready()) { |
| 596 | /* Device is back on its imaginary feet, clear reset */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 597 | cse_set_host_ready(); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 598 | return 1; |
| 599 | } |
| 600 | |
| 601 | printk(BIOS_CRIT, "HECI: reset failed\n"); |
| 602 | |
| 603 | return 0; |
| 604 | } |
| 605 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 606 | bool is_cse_devfn_visible(unsigned int devfn) |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 607 | { |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 608 | int slot = PCI_SLOT(devfn); |
| 609 | int func = PCI_FUNC(devfn); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 610 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 611 | if (!is_devfn_enabled(devfn)) { |
| 612 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 613 | return false; |
| 614 | } |
| 615 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 616 | if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { |
| 617 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 618 | return false; |
| 619 | } |
| 620 | |
| 621 | return true; |
| 622 | } |
| 623 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 624 | bool is_cse_enabled(void) |
| 625 | { |
| 626 | return is_cse_devfn_visible(PCH_DEVFN_CSE); |
| 627 | } |
| 628 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 629 | uint32_t me_read_config32(int offset) |
| 630 | { |
| 631 | return pci_read_config32(PCH_DEV_CSE, offset); |
| 632 | } |
| 633 | |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 634 | static bool cse_is_global_reset_allowed(void) |
| 635 | { |
| 636 | /* |
| 637 | * Allow sending GLOBAL_RESET command only if: |
| 638 | * - CSE's current working state is Normal and current operation mode is Normal. |
| 639 | * - (or) CSE's current working state is normal and current operation mode can |
| 640 | * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 641 | * Lite. |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 642 | */ |
| 643 | if (!cse_is_hfs1_cws_normal()) |
| 644 | return false; |
| 645 | |
| 646 | if (cse_is_hfs1_com_normal()) |
| 647 | return true; |
| 648 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 649 | if (cse_is_hfs3_fw_sku_lite()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 650 | if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) |
| 651 | return true; |
| 652 | } |
| 653 | return false; |
| 654 | } |
| 655 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 656 | /* |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 657 | * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. |
| 658 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 659 | */ |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 660 | static int cse_request_reset(enum rst_req_type rst_type) |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 661 | { |
| 662 | int status; |
| 663 | struct mkhi_hdr reply; |
| 664 | struct reset_message { |
| 665 | struct mkhi_hdr hdr; |
| 666 | uint8_t req_origin; |
| 667 | uint8_t reset_type; |
| 668 | } __packed; |
| 669 | struct reset_message msg = { |
| 670 | .hdr = { |
| 671 | .group_id = MKHI_GROUP_ID_CBM, |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 672 | .command = MKHI_CBM_GLOBAL_RESET_REQ, |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 673 | }, |
| 674 | .req_origin = GR_ORIGIN_BIOS_POST, |
| 675 | .reset_type = rst_type |
| 676 | }; |
| 677 | size_t reply_size; |
| 678 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 679 | printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 680 | |
Sridhar Siricilla | c2a2d2b | 2020-02-27 17:16:13 +0530 | [diff] [blame] | 681 | if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 682 | printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); |
| 683 | return 0; |
| 684 | } |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 685 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 686 | if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 687 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 688 | return 0; |
| 689 | } |
| 690 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 691 | heci_reset(); |
| 692 | |
| 693 | reply_size = sizeof(reply); |
| 694 | memset(&reply, 0, reply_size); |
| 695 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 696 | if (rst_type == CSE_RESET_ONLY) |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 697 | status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 698 | else |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 699 | status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, |
| 700 | HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 701 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 702 | printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); |
| 703 | return status; |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 704 | } |
| 705 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 706 | int cse_request_global_reset(void) |
| 707 | { |
| 708 | return cse_request_reset(GLOBAL_RESET); |
| 709 | } |
| 710 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 711 | static bool cse_is_hmrfpo_enable_allowed(void) |
| 712 | { |
| 713 | /* |
| 714 | * Allow sending HMRFPO ENABLE command only if: |
| 715 | * - CSE's current working state is Normal and current operation mode is Normal |
| 716 | * - (or) cse's current working state is normal and current operation mode is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 717 | * Soft Temp Disable if CSE's Firmware SKU is Lite |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 718 | */ |
| 719 | if (!cse_is_hfs1_cws_normal()) |
| 720 | return false; |
| 721 | |
| 722 | if (cse_is_hfs1_com_normal()) |
| 723 | return true; |
| 724 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 725 | if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable()) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 726 | return true; |
| 727 | |
| 728 | return false; |
| 729 | } |
| 730 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 731 | /* Sends HMRFPO Enable command to CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 732 | int cse_hmrfpo_enable(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 733 | { |
| 734 | struct hmrfpo_enable_msg { |
| 735 | struct mkhi_hdr hdr; |
| 736 | uint32_t nonce[2]; |
| 737 | } __packed; |
| 738 | |
| 739 | /* HMRFPO Enable message */ |
| 740 | struct hmrfpo_enable_msg msg = { |
| 741 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 742 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 743 | .command = MKHI_HMRFPO_ENABLE, |
| 744 | }, |
| 745 | .nonce = {0}, |
| 746 | }; |
| 747 | |
| 748 | /* HMRFPO Enable response */ |
| 749 | struct hmrfpo_enable_resp { |
| 750 | struct mkhi_hdr hdr; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 751 | /* Base addr for factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 752 | uint32_t fct_base; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 753 | /* Length of factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 754 | uint32_t fct_limit; |
| 755 | uint8_t status; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 756 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 757 | } __packed; |
| 758 | |
| 759 | struct hmrfpo_enable_resp resp; |
| 760 | size_t resp_size = sizeof(struct hmrfpo_enable_resp); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 761 | |
Sridhar Siricilla | 49c25f2 | 2021-11-27 19:56:47 +0530 | [diff] [blame] | 762 | if (cse_is_hfs1_com_secover_mei_msg()) { |
| 763 | printk(BIOS_DEBUG, "HECI: CSE is already in security override mode, " |
| 764 | "skip sending HMRFPO_ENABLE command to CSE\n"); |
| 765 | return 1; |
| 766 | } |
| 767 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 768 | printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 769 | |
| 770 | if (!cse_is_hmrfpo_enable_allowed()) { |
| 771 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 772 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 773 | } |
| 774 | |
| 775 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 776 | &resp, &resp_size, HECI_MKHI_ADDR)) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 777 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 778 | |
| 779 | if (resp.hdr.result) { |
| 780 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 781 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 782 | } |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 783 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 784 | if (resp.status) { |
| 785 | printk(BIOS_ERR, "HECI: HMRFPO_Enable Failed (resp status: %d)\n", resp.status); |
| 786 | return 0; |
| 787 | } |
| 788 | |
| 789 | return 1; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 790 | } |
| 791 | |
| 792 | /* |
| 793 | * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 794 | * The status can be DISABLED/LOCKED/ENABLED |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 795 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 796 | int cse_hmrfpo_get_status(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 797 | { |
| 798 | struct hmrfpo_get_status_msg { |
| 799 | struct mkhi_hdr hdr; |
| 800 | } __packed; |
| 801 | |
| 802 | struct hmrfpo_get_status_resp { |
| 803 | struct mkhi_hdr hdr; |
| 804 | uint8_t status; |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 805 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 806 | } __packed; |
| 807 | |
| 808 | struct hmrfpo_get_status_msg msg = { |
| 809 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 810 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 811 | .command = MKHI_HMRFPO_GET_STATUS, |
| 812 | }, |
| 813 | }; |
| 814 | struct hmrfpo_get_status_resp resp; |
| 815 | size_t resp_size = sizeof(struct hmrfpo_get_status_resp); |
| 816 | |
| 817 | printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); |
| 818 | |
Sridhar Siricilla | 206905c | 2020-02-06 18:48:22 +0530 | [diff] [blame] | 819 | if (!cse_is_hfs1_cws_normal()) { |
| 820 | printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); |
| 821 | return -1; |
| 822 | } |
| 823 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 824 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 825 | &resp, &resp_size, HECI_MKHI_ADDR)) { |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 826 | printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); |
| 827 | return -1; |
| 828 | } |
| 829 | |
| 830 | if (resp.hdr.result) { |
| 831 | printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", |
| 832 | resp.hdr.result); |
| 833 | return -1; |
| 834 | } |
| 835 | |
| 836 | return resp.status; |
| 837 | } |
| 838 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 839 | void print_me_fw_version(void *unused) |
| 840 | { |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 841 | struct me_fw_ver_resp resp = {0}; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 842 | |
| 843 | /* Ignore if UART debugging is disabled */ |
| 844 | if (!CONFIG(CONSOLE_SERIAL)) |
| 845 | return; |
| 846 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 847 | if (get_me_fw_version(&resp) == CB_SUCCESS) { |
| 848 | printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, |
| 849 | resp.code.minor, resp.code.hotfix, resp.code.build); |
| 850 | return; |
| 851 | } |
| 852 | printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); |
| 853 | } |
| 854 | |
| 855 | enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) |
| 856 | { |
| 857 | const struct mkhi_hdr fw_ver_msg = { |
| 858 | .group_id = MKHI_GROUP_ID_GEN, |
| 859 | .command = MKHI_GEN_GET_FW_VERSION, |
| 860 | }; |
| 861 | |
| 862 | if (resp == NULL) { |
| 863 | printk(BIOS_ERR, "%s failed, null pointer parameter\n", __func__); |
| 864 | return CB_ERR; |
| 865 | } |
| 866 | size_t resp_size = sizeof(*resp); |
| 867 | |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 868 | /* Ignore if CSE is disabled */ |
| 869 | if (!is_cse_enabled()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 870 | return CB_ERR; |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 871 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 872 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 873 | * Ignore if ME Firmware SKU type is Lite since |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 874 | * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. |
| 875 | */ |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 876 | if (cse_is_hfs3_fw_sku_lite()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 877 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 878 | |
| 879 | /* |
| 880 | * Prerequisites: |
| 881 | * 1) HFSTS1 Current Working State is Normal |
| 882 | * 2) HFSTS1 Current Operation Mode is Normal |
| 883 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 884 | * during ramstage |
| 885 | */ |
| 886 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 887 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 888 | |
| 889 | heci_reset(); |
| 890 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 891 | if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 892 | HECI_MKHI_ADDR)) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 893 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 894 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 895 | if (resp->hdr.result) |
| 896 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 897 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 898 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 899 | return CB_SUCCESS; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 900 | } |
| 901 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 902 | void cse_trigger_vboot_recovery(enum csme_failure_reason reason) |
| 903 | { |
| 904 | printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " |
| 905 | "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), |
| 906 | me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); |
| 907 | |
| 908 | if (CONFIG(VBOOT)) { |
| 909 | struct vb2_context *ctx = vboot_get_context(); |
| 910 | if (ctx == NULL) |
| 911 | goto failure; |
| 912 | vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, reason); |
| 913 | vboot_save_data(ctx); |
| 914 | vboot_reboot(); |
| 915 | } |
| 916 | failure: |
| 917 | die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); |
| 918 | } |
| 919 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 920 | static bool disable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 921 | { |
| 922 | struct stopwatch sw; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 923 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 924 | dev_idle_ctrl &= ~CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 925 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 926 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 927 | stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 928 | do { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 929 | dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 930 | if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) |
| 931 | return true; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 932 | udelay(HECI_DELAY_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 933 | } while (!stopwatch_expired(&sw)); |
| 934 | |
| 935 | return false; |
| 936 | } |
| 937 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 938 | static void enable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 939 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 940 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 941 | dev_idle_ctrl |= CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 942 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 943 | } |
| 944 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 945 | enum cse_device_state get_cse_device_state(unsigned int devfn) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 946 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 947 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 948 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 949 | if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) |
| 950 | return DEV_IDLE; |
| 951 | |
| 952 | return DEV_ACTIVE; |
| 953 | } |
| 954 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 955 | static enum cse_device_state ensure_cse_active(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 956 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 957 | if (!disable_cse_idle(dev)) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 958 | return DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 959 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 960 | |
| 961 | return DEV_ACTIVE; |
| 962 | } |
| 963 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 964 | static void ensure_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 965 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 966 | enable_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 967 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 968 | pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 969 | } |
| 970 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 971 | bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 972 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 973 | enum cse_device_state current_state = get_cse_device_state(devfn); |
| 974 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 975 | |
| 976 | if (current_state == requested_state) |
| 977 | return true; |
| 978 | |
| 979 | if (requested_state == DEV_ACTIVE) |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 980 | return ensure_cse_active(dev) == requested_state; |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 981 | else |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 982 | ensure_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 983 | |
| 984 | return true; |
| 985 | } |
| 986 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 987 | #if ENV_RAMSTAGE |
| 988 | |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 989 | /* |
| 990 | * Disable the Intel (CS)Management Engine via HECI based on a cmos value |
| 991 | * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working) |
| 992 | * and value of `1` will result in a (CS)ME state of `3` (disabled). |
| 993 | * |
| 994 | * It isn't advised to use this in combination with me_cleaner. |
| 995 | * |
| 996 | * It is advisable to have a second cmos option called `me_state_counter`. |
| 997 | * Whilst not essential, it avoid reboots loops if the (CS)ME fails to |
| 998 | * change states after 3 attempts. Some versions of the (CS)ME need to be |
| 999 | * reset 3 times. |
| 1000 | * |
| 1001 | * Ideal cmos values would be: |
| 1002 | * |
| 1003 | * # coreboot config options: cpu |
| 1004 | * 432 1 e 5 me_state |
| 1005 | * 440 4 h 0 me_state_counter |
| 1006 | * |
| 1007 | * #ID value text |
| 1008 | * 5 0 Enable |
| 1009 | * 5 1 Disable |
| 1010 | */ |
| 1011 | |
| 1012 | static void me_reset_with_count(void) |
| 1013 | { |
| 1014 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", UINT_MAX); |
| 1015 | |
| 1016 | if (cmos_me_state_counter != UINT_MAX) { |
| 1017 | printk(BIOS_DEBUG, "CMOS: me_state_counter = %u\n", cmos_me_state_counter); |
| 1018 | /* Avoid boot loops by only trying a state change 3 times */ |
| 1019 | if (cmos_me_state_counter < ME_DISABLE_ATTEMPTS) { |
| 1020 | cmos_me_state_counter++; |
| 1021 | set_uint_option("me_state_counter", cmos_me_state_counter); |
| 1022 | printk(BIOS_DEBUG, "ME: Reset attempt %u/%u.\n", cmos_me_state_counter, |
| 1023 | ME_DISABLE_ATTEMPTS); |
| 1024 | do_global_reset(); |
| 1025 | } else { |
| 1026 | /* |
| 1027 | * If the (CS)ME fails to change states after 3 attempts, it will |
| 1028 | * likely need a cold boot, or recovering. |
| 1029 | */ |
| 1030 | printk(BIOS_ERR, "Error: Failed to change ME state in %u attempts!\n", |
| 1031 | ME_DISABLE_ATTEMPTS); |
| 1032 | |
| 1033 | } |
| 1034 | } else { |
| 1035 | printk(BIOS_DEBUG, "ME: Resetting"); |
| 1036 | do_global_reset(); |
| 1037 | } |
| 1038 | } |
| 1039 | |
| 1040 | static void cse_set_state(struct device *dev) |
| 1041 | { |
| 1042 | |
| 1043 | /* (CS)ME Disable Command */ |
| 1044 | struct me_disable_command { |
| 1045 | struct mkhi_hdr hdr; |
| 1046 | uint32_t rule_id; |
| 1047 | uint8_t rule_len; |
| 1048 | uint32_t rule_data; |
| 1049 | } __packed me_disable = { |
| 1050 | .hdr = { |
| 1051 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 1052 | .command = MKHI_SET_ME_DISABLE, |
| 1053 | }, |
| 1054 | .rule_id = ME_DISABLE_RULE_ID, |
| 1055 | .rule_len = ME_DISABLE_RULE_LENGTH, |
| 1056 | .rule_data = ME_DISABLE_COMMAND, |
| 1057 | }; |
| 1058 | |
| 1059 | struct me_disable_reply { |
| 1060 | struct mkhi_hdr hdr; |
| 1061 | uint32_t rule_id; |
| 1062 | } __packed; |
| 1063 | |
| 1064 | struct me_disable_reply disable_reply; |
| 1065 | |
| 1066 | size_t disable_reply_size; |
| 1067 | |
| 1068 | /* (CS)ME Enable Command */ |
| 1069 | struct me_enable_command { |
| 1070 | struct mkhi_hdr hdr; |
| 1071 | } me_enable = { |
| 1072 | .hdr = { |
| 1073 | .group_id = MKHI_GROUP_ID_BUP_COMMON, |
| 1074 | .command = MKHI_SET_ME_ENABLE, |
| 1075 | }, |
| 1076 | }; |
| 1077 | |
| 1078 | struct me_enable_reply { |
| 1079 | struct mkhi_hdr hdr; |
| 1080 | } __packed; |
| 1081 | |
| 1082 | struct me_enable_reply enable_reply; |
| 1083 | |
| 1084 | size_t enable_reply_size; |
| 1085 | |
| 1086 | /* Function Start */ |
| 1087 | |
| 1088 | int send; |
| 1089 | int result; |
| 1090 | /* |
| 1091 | * Check if the CMOS value "me_state" exists, if it doesn't, then |
| 1092 | * don't do anything. |
| 1093 | */ |
| 1094 | const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); |
| 1095 | |
| 1096 | if (cmos_me_state == UINT_MAX) |
| 1097 | return; |
| 1098 | |
| 1099 | printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); |
| 1100 | |
| 1101 | /* |
| 1102 | * We only take action if the me_state doesn't match the CS(ME) working state |
| 1103 | */ |
| 1104 | |
| 1105 | const unsigned int soft_temp_disable = cse_is_hfs1_com_soft_temp_disable(); |
| 1106 | |
| 1107 | if (cmos_me_state && !soft_temp_disable) { |
| 1108 | /* me_state should be disabled, but it's enabled */ |
| 1109 | printk(BIOS_DEBUG, "ME needs to be disabled.\n"); |
| 1110 | send = heci_send_receive(&me_disable, sizeof(me_disable), |
| 1111 | &disable_reply, &disable_reply_size, HECI_MKHI_ADDR); |
| 1112 | result = disable_reply.hdr.result; |
| 1113 | } else if (!cmos_me_state && soft_temp_disable) { |
| 1114 | /* me_state should be enabled, but it's disabled */ |
| 1115 | printk(BIOS_DEBUG, "ME needs to be enabled.\n"); |
| 1116 | send = heci_send_receive(&me_enable, sizeof(me_enable), |
| 1117 | &enable_reply, &enable_reply_size, HECI_MKHI_ADDR); |
| 1118 | result = enable_reply.hdr.result; |
| 1119 | } else { |
| 1120 | printk(BIOS_DEBUG, "ME is %s.\n", cmos_me_state ? "disabled" : "enabled"); |
| 1121 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", |
| 1122 | UINT_MAX); |
| 1123 | /* set me_state_counter to 0 */ |
| 1124 | if ((cmos_me_state_counter != UINT_MAX && cmos_me_state_counter != 0)) |
| 1125 | set_uint_option("me_state_counter", 0); |
| 1126 | return; |
| 1127 | } |
| 1128 | |
| 1129 | printk(BIOS_DEBUG, "HECI: ME state change send %s!\n", |
| 1130 | send ? "success" : "failure"); |
| 1131 | printk(BIOS_DEBUG, "HECI: ME state change result %s!\n", |
| 1132 | result ? "success" : "failure"); |
| 1133 | |
| 1134 | /* |
| 1135 | * Reset if the result was successful, or if the send failed as some older |
| 1136 | * version of the Intel (CS)ME won't successfully receive the message unless reset |
| 1137 | * twice. |
| 1138 | */ |
| 1139 | if (send || !result) |
| 1140 | me_reset_with_count(); |
| 1141 | } |
| 1142 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1143 | static struct device_operations cse_ops = { |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 1144 | .set_resources = pci_dev_set_resources, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1145 | .read_resources = pci_dev_read_resources, |
| 1146 | .enable_resources = pci_dev_enable_resources, |
| 1147 | .init = pci_dev_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 1148 | .ops_pci = &pci_dev_ops_pci, |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1149 | .enable = cse_set_state, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1150 | }; |
| 1151 | |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1152 | static const unsigned short pci_device_ids[] = { |
| 1153 | PCI_DEVICE_ID_INTEL_APL_CSE0, |
| 1154 | PCI_DEVICE_ID_INTEL_GLK_CSE0, |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 1155 | PCI_DEVICE_ID_INTEL_CNL_CSE0, |
Subrata Banik | d0586d2 | 2017-11-27 13:28:41 +0530 | [diff] [blame] | 1156 | PCI_DEVICE_ID_INTEL_SKL_CSE0, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 1157 | PCI_DEVICE_ID_INTEL_LWB_CSE0, |
| 1158 | PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 1159 | PCI_DEVICE_ID_INTEL_CNP_H_CSE0, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 1160 | PCI_DEVICE_ID_INTEL_ICL_CSE0, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 1161 | PCI_DEVICE_ID_INTEL_CMP_CSE0, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 1162 | PCI_DEVICE_ID_INTEL_CMP_H_CSE0, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 1163 | PCI_DEVICE_ID_INTEL_TGL_CSE0, |
Jeremy Soller | 191a8d7 | 2021-08-10 14:06:51 -0600 | [diff] [blame] | 1164 | PCI_DEVICE_ID_INTEL_TGL_H_CSE0, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 1165 | PCI_DEVICE_ID_INTEL_MCC_CSE0, |
| 1166 | PCI_DEVICE_ID_INTEL_MCC_CSE1, |
| 1167 | PCI_DEVICE_ID_INTEL_MCC_CSE2, |
| 1168 | PCI_DEVICE_ID_INTEL_MCC_CSE3, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 1169 | PCI_DEVICE_ID_INTEL_JSP_CSE0, |
| 1170 | PCI_DEVICE_ID_INTEL_JSP_CSE1, |
| 1171 | PCI_DEVICE_ID_INTEL_JSP_CSE2, |
| 1172 | PCI_DEVICE_ID_INTEL_JSP_CSE3, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 1173 | PCI_DEVICE_ID_INTEL_ADP_P_CSE0, |
| 1174 | PCI_DEVICE_ID_INTEL_ADP_P_CSE1, |
| 1175 | PCI_DEVICE_ID_INTEL_ADP_P_CSE2, |
| 1176 | PCI_DEVICE_ID_INTEL_ADP_P_CSE3, |
| 1177 | PCI_DEVICE_ID_INTEL_ADP_S_CSE0, |
| 1178 | PCI_DEVICE_ID_INTEL_ADP_S_CSE1, |
| 1179 | PCI_DEVICE_ID_INTEL_ADP_S_CSE2, |
| 1180 | PCI_DEVICE_ID_INTEL_ADP_S_CSE3, |
Varshit Pandya | f4d98fdd2 | 2021-01-17 18:39:29 +0530 | [diff] [blame] | 1181 | PCI_DEVICE_ID_INTEL_ADP_M_CSE0, |
| 1182 | PCI_DEVICE_ID_INTEL_ADP_M_CSE1, |
| 1183 | PCI_DEVICE_ID_INTEL_ADP_M_CSE2, |
| 1184 | PCI_DEVICE_ID_INTEL_ADP_M_CSE3, |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1185 | 0, |
| 1186 | }; |
| 1187 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1188 | static const struct pci_driver cse_driver __pci_driver = { |
| 1189 | .ops = &cse_ops, |
| 1190 | .vendor = PCI_VENDOR_ID_INTEL, |
| 1191 | /* SoC/chipset needs to provide PCI device ID */ |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 1192 | .devices = pci_device_ids |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1193 | }; |
| 1194 | |
| 1195 | #endif |