soc/intel/common/block/cse: Move me_read_config32() to common code
me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.
Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.
TEST=Verified reading HFSTS registers on CML RVP & Hatch board
Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 9520242..1671970 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -503,6 +503,28 @@
return 0;
}
+bool is_cse_enabled(void)
+{
+ const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE);
+
+ if (!cse_dev || !cse_dev->enabled) {
+ printk(BIOS_WARNING, "HECI: No CSE device\n");
+ return false;
+ }
+
+ if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) {
+ printk(BIOS_WARNING, "HECI: CSE device is hidden\n");
+ return false;
+ }
+
+ return true;
+}
+
+uint32_t me_read_config32(int offset)
+{
+ return pci_read_config32(PCH_DEV_CSE, offset);
+}
+
#if ENV_RAMSTAGE
static void update_sec_bar(struct device *dev)