soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macro
CSE_DELAY_BOOT_TO_RO -> CSE_DELAY_BOOT_TO_RO_MS
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I4471e4553a081eaf5c8118e9600497a2b2437ac0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 8d5644c..ffe10a5 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -29,6 +29,8 @@
#define HECI_READ_TIMEOUT_MS (5 * 1000)
/* Wait up to 1 ms for CSE CIP */
#define HECI_CIP_TIMEOUT_US 1000
+/* Wait up to 5 seconds for CSE to boot from RO(BP1) */
+#define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000)
#define SLOT_SIZE sizeof(uint32_t)
@@ -62,9 +64,6 @@
#define MEI_HDR_CSE_ADDR_START 0
#define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START)
-/* Wait up to 5 seconds for CSE to boot from RO(BP1) */
-#define CSE_DELAY_BOOT_TO_RO (5 * 1000)
-
static struct cse_device {
uintptr_t sec_bar;
} cse;
@@ -306,7 +305,7 @@
uint8_t cse_wait_com_soft_temp_disable(void)
{
struct stopwatch sw;
- stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO);
+ stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS);
while (!cse_is_hfs1_com_soft_temp_disable()) {
udelay(HECI_DELAY_US);
if (stopwatch_expired(&sw)) {