soc/intel/common/block/cse: Move cse_trigger_recovery function
This function could be applicable in situations other than just for the
CSE Lite SKU, therefore move this from cse_lite.c to cse.c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibc541f2e30ef06856da10f1f1219930dff493afa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55673
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index c6f87b4..1e6bdc8 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -9,6 +9,8 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <intelblocks/cse.h>
+#include <security/vboot/misc.h>
+#include <security/vboot/vboot_common.h>
#include <soc/iomap.h>
#include <soc/pci_devs.h>
#include <soc/me.h>
@@ -859,6 +861,24 @@
printk(BIOS_DEBUG, "ME: Version: Unavailable\n");
}
+void cse_trigger_vboot_recovery(enum csme_failure_reason reason)
+{
+ printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x "
+ "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1),
+ me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3));
+
+ if (CONFIG(VBOOT)) {
+ struct vb2_context *ctx = vboot_get_context();
+ if (ctx == NULL)
+ goto failure;
+ vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, reason);
+ vboot_save_data(ctx);
+ vboot_reboot();
+ }
+failure:
+ die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason);
+}
+
#if ENV_RAMSTAGE
static void update_sec_bar(struct device *dev)