soc/intel/common: Helper function to check CSE device `devfn` status
This patch creates a helper function in cse common code block to check
the status of any CSE `devfn`. Example: CSE, CSE_2, IDER, KT, CSE_3 and
CSE_4.
Currently cse common code is only able to read the device state of
`PCH_DEVFN_CSE` CSE device alone.
Additionally, print `slot` and 'func' number of CSE devices in case
the device is either disable or hidden.
BUG=b:200644229
TEST=Able to build and boot ADLRVP-P with this patch where the serial
message listed the CSE devices that are disabled in the device tree
as below:
HECI: CSE device 16.01 is disabled
HECI: CSE device 16.04 is disabled
HECI: CSE device 16.05 is disabled
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I208b07e89e3aa9d682837380809fbff01ea225b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 471bc1b..e41e337 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -581,23 +581,29 @@
return 0;
}
-bool is_cse_enabled(void)
+bool is_cse_devfn_visible(unsigned int devfn)
{
- const struct device *cse_dev = pcidev_path_on_root(PCH_DEVFN_CSE);
+ int slot = PCI_SLOT(devfn);
+ int func = PCI_FUNC(devfn);
- if (!cse_dev || !cse_dev->enabled) {
- printk(BIOS_WARNING, "HECI: No CSE device\n");
+ if (!is_devfn_enabled(devfn)) {
+ printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func);
return false;
}
- if (pci_read_config16(PCH_DEV_CSE, PCI_VENDOR_ID) == 0xFFFF) {
- printk(BIOS_WARNING, "HECI: CSE device is hidden\n");
+ if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) {
+ printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func);
return false;
}
return true;
}
+bool is_cse_enabled(void)
+{
+ return is_cse_devfn_visible(PCH_DEVFN_CSE);
+}
+
uint32_t me_read_config32(int offset)
{
return pci_read_config32(PCH_DEV_CSE, offset);