Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 2 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 4 | #include <acpi/acpigen.h> |
Kyösti Mälkki | 5daa1d3 | 2020-06-14 12:01:58 +0300 | [diff] [blame] | 5 | #include <acpi/acpi_gnvs.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 6 | #include <console/uart.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 9 | #include <device/pci_def.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 10 | #include <device/pci_ids.h> |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 12 | #include <intelblocks/lpss.h> |
| 13 | #include <intelblocks/uart.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/iomap.h> |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 16 | #include <soc/irq.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 17 | #include <soc/nvs.h> |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 18 | #include "chip.h" |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 19 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 20 | #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 21 | #define UART_CONSOLE_INVALID_INDEX 0xFF |
| 22 | |
Furquan Shaikh | 4fa183f | 2021-01-06 20:30:35 -0800 | [diff] [blame] | 23 | extern const struct uart_controller_config uart_ctrlr_config[]; |
Michael Niewöhner | f3faddc | 2021-01-11 13:21:19 +0100 | [diff] [blame] | 24 | extern const int uart_ctrlr_config_size; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 25 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 26 | static void uart_lpss_init(pci_devfn_t dev, uintptr_t baseaddr) |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 27 | { |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 28 | /* Ensure controller is in D0 state */ |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 29 | lpss_set_power_state(dev, STATE_D0); |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 30 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 31 | /* Take UART out of reset */ |
| 32 | lpss_reset_release(baseaddr); |
| 33 | |
| 34 | /* Set M and N divisor inputs and enable clock */ |
| 35 | lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, |
| 36 | CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); |
| 37 | } |
| 38 | |
Nico Huber | 62ddc49 | 2019-05-29 18:39:31 +0200 | [diff] [blame] | 39 | #if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) |
Felix Held | e3a1247 | 2020-09-11 15:47:09 +0200 | [diff] [blame] | 40 | uintptr_t uart_platform_base(unsigned int idx) |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 41 | { |
Nico Huber | ce8eebd | 2019-05-29 18:33:35 +0200 | [diff] [blame] | 42 | if (idx == CONFIG_UART_FOR_CONSOLE) |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 43 | return CONFIG_CONSOLE_UART_BASE_ADDRESS; |
Nico Huber | ce8eebd | 2019-05-29 18:33:35 +0200 | [diff] [blame] | 44 | return 0; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 45 | } |
| 46 | #endif |
| 47 | |
| 48 | static int uart_get_valid_index(void) |
| 49 | { |
| 50 | int index; |
| 51 | |
Michael Niewöhner | f3faddc | 2021-01-11 13:21:19 +0100 | [diff] [blame] | 52 | for (index = 0; index < uart_ctrlr_config_size; index++) { |
Furquan Shaikh | 4fa183f | 2021-01-06 20:30:35 -0800 | [diff] [blame] | 53 | if (uart_ctrlr_config[index].console_index == |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 54 | CONFIG_UART_FOR_CONSOLE) |
| 55 | return index; |
| 56 | } |
| 57 | /* For valid index, code should not reach here */ |
| 58 | return UART_CONSOLE_INVALID_INDEX; |
| 59 | } |
| 60 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 61 | static pci_devfn_t uart_console_get_pci_bdf(void) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 62 | { |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 63 | int devfn; |
| 64 | int index; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 65 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 66 | /* |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 67 | * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE |
| 68 | * config option is not selected. |
| 69 | * By default return NULL in this case to avoid compilation errors. |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 70 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 71 | if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 72 | return PCI_DEV_INVALID; |
| 73 | |
| 74 | index = uart_get_valid_index(); |
| 75 | if (index == UART_CONSOLE_INVALID_INDEX) |
| 76 | return PCI_DEV_INVALID; |
| 77 | |
| 78 | devfn = uart_ctrlr_config[index].devfn; |
| 79 | return PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 80 | } |
| 81 | |
| 82 | const struct device *uart_get_device(void) |
| 83 | { |
| 84 | pci_devfn_t dev = uart_console_get_pci_bdf(); |
| 85 | if (dev == PCI_DEV_INVALID) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 86 | return NULL; |
| 87 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 88 | return pcidev_path_on_root(PCI_DEV2DEVFN(dev)); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 89 | } |
| 90 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 91 | bool uart_is_controller_initialized(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 92 | { |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 93 | uintptr_t base; |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 94 | pci_devfn_t dev = uart_console_get_pci_bdf(); |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 95 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 96 | if (dev == PCI_DEV_INVALID) |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 97 | return false; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 98 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 99 | base = pci_s_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 100 | if (!base) |
| 101 | return false; |
| 102 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 103 | if ((pci_s_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 104 | != UART_PCI_ENABLE) |
| 105 | return false; |
| 106 | |
| 107 | return !lpss_is_controller_in_reset(base); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 108 | } |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 109 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 110 | static void uart_configure_gpio_pads(void) |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 111 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 112 | int index = uart_get_valid_index(); |
| 113 | |
| 114 | if (index != UART_CONSOLE_INVALID_INDEX) |
Furquan Shaikh | 4fa183f | 2021-01-06 20:30:35 -0800 | [diff] [blame] | 115 | gpio_configure_pads(uart_ctrlr_config[index].gpios, |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 116 | MAX_GPIO_PAD_PER_UART); |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 117 | } |
| 118 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 119 | void uart_bootblock_init(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 120 | { |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 121 | const uint32_t baseaddr = CONFIG_CONSOLE_UART_BASE_ADDRESS; |
| 122 | pci_devfn_t dev = uart_console_get_pci_bdf(); |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 123 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 124 | if (dev == PCI_DEV_INVALID) |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 125 | return; |
| 126 | |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 127 | /* Set UART base address */ |
| 128 | pci_s_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 129 | |
| 130 | /* Enable memory access and bus master */ |
| 131 | pci_s_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); |
| 132 | |
| 133 | uart_lpss_init(dev, baseaddr); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 134 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 135 | /* Configure the 2 pads per UART. */ |
| 136 | uart_configure_gpio_pads(); |
| 137 | } |
| 138 | |
| 139 | #if ENV_RAMSTAGE |
| 140 | |
| 141 | static void uart_read_resources(struct device *dev) |
| 142 | { |
| 143 | pci_dev_read_resources(dev); |
| 144 | |
| 145 | /* Set the configured UART base address for the debug port */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 146 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 147 | uart_is_debug_controller(dev)) { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 148 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 149 | /* Need to set the base and size for the resource allocator. */ |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 150 | res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS; |
| 151 | res->size = 0x1000; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 152 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 153 | IORESOURCE_FIXED; |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Check if UART debug port controller needs to be initialized on resume. |
| 159 | * |
| 160 | * Returns: |
| 161 | * true = when SoC wants debug port initialization on resume |
| 162 | * false = otherwise |
| 163 | */ |
| 164 | static bool pch_uart_init_debug_controller_on_resume(void) |
| 165 | { |
Kyösti Mälkki | 0c1dd9c | 2020-06-17 23:37:49 +0300 | [diff] [blame] | 166 | struct global_nvs *gnvs = acpi_get_gnvs(); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 167 | |
| 168 | if (gnvs) |
| 169 | return !!gnvs->uior; |
| 170 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 171 | return false; |
| 172 | } |
| 173 | |
| 174 | bool uart_is_debug_controller(struct device *dev) |
| 175 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 176 | return dev == uart_get_device(); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | /* |
| 180 | * This is a workaround to enable UART controller for the debug port if: |
| 181 | * 1. CONSOLE_SERIAL is not enabled in coreboot, and |
| 182 | * 2. This boot is S3 resume, and |
| 183 | * 3. SoC wants to initialize debug UART controller. |
| 184 | * |
| 185 | * This workaround is required because Linux kernel hangs on resume if console |
| 186 | * is not enabled in coreboot, but it is enabled in kernel and not suspended. |
| 187 | */ |
| 188 | static bool uart_controller_needs_init(struct device *dev) |
| 189 | { |
| 190 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 191 | * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 192 | * controller here. |
| 193 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 194 | if (CONFIG(CONSOLE_SERIAL)) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 195 | return false; |
| 196 | |
| 197 | /* If this device does not correspond to debug port, then skip. */ |
| 198 | if (!uart_is_debug_controller(dev)) |
| 199 | return false; |
| 200 | |
| 201 | /* Initialize UART controller only on S3 resume. */ |
| 202 | if (!acpi_is_wakeup_s3()) |
| 203 | return false; |
| 204 | |
| 205 | /* |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 206 | * check if SOC wants to initialize UART on resume |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 207 | */ |
| 208 | return pch_uart_init_debug_controller_on_resume(); |
| 209 | } |
| 210 | |
| 211 | static void uart_common_enable_resources(struct device *dev) |
| 212 | { |
| 213 | pci_dev_enable_resources(dev); |
| 214 | |
| 215 | if (uart_controller_needs_init(dev)) { |
| 216 | uintptr_t base; |
| 217 | |
| 218 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 219 | if (base) |
Furquan Shaikh | 582a0e2 | 2021-01-07 00:16:35 -0800 | [diff] [blame] | 220 | uart_lpss_init(PCI_BDF(dev), base); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 221 | } |
| 222 | } |
| 223 | |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 224 | static void uart_acpi_write_irq(const struct device *dev) |
| 225 | { |
| 226 | struct acpi_irq irq; |
| 227 | |
| 228 | switch (dev->path.pci.devfn) { |
| 229 | case PCH_DEVFN_UART0: |
| 230 | irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART0_IRQ); |
| 231 | break; |
| 232 | case PCH_DEVFN_UART1: |
| 233 | irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART1_IRQ); |
| 234 | break; |
| 235 | case PCH_DEVFN_UART2: |
| 236 | irq = (struct acpi_irq)ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ); |
| 237 | break; |
| 238 | default: |
| 239 | return; |
| 240 | } |
| 241 | |
| 242 | acpi_device_write_interrupt(&irq); |
| 243 | } |
| 244 | |
| 245 | /* |
| 246 | * Generate an ACPI entry if the device is enabled in devicetree for the ACPI |
| 247 | * LPSS driver. In this mode the device and vendor ID reads as 0xffff, but the |
| 248 | * PCI device is still there. |
| 249 | */ |
| 250 | static void uart_fill_ssdt(const struct device *dev) |
| 251 | { |
| 252 | const char *scope = acpi_device_scope(dev); |
| 253 | const char *hid = acpi_device_hid(dev); |
| 254 | struct resource *res; |
| 255 | |
| 256 | /* In ACPI mode the device is "invisible" */ |
| 257 | if (!dev->hidden) |
| 258 | return; |
| 259 | |
| 260 | if (!scope || !hid) |
| 261 | return; |
| 262 | |
| 263 | res = probe_resource(dev, PCI_BASE_ADDRESS_0); |
| 264 | if (!res) |
| 265 | return; |
| 266 | |
| 267 | /* Scope */ |
| 268 | acpigen_write_scope(scope); |
| 269 | |
| 270 | /* Device */ |
| 271 | acpigen_write_device(acpi_device_name(dev)); |
| 272 | acpigen_write_name_string("_HID", hid); |
| 273 | /* |
| 274 | * Advertise compatibility to Sunrise Point, as the Linux kernel doesn't support |
| 275 | * CannonPoint yet... |
| 276 | */ |
| 277 | if (strcmp(hid, "INT34B8") == 0) |
| 278 | acpigen_write_name_string("_CID", "INT3448"); |
| 279 | else if (strcmp(hid, "INT34B9") == 0) |
| 280 | acpigen_write_name_string("_CID", "INT3449"); |
| 281 | else if (strcmp(hid, "INT34BA") == 0) |
| 282 | acpigen_write_name_string("_CID", "INT344A"); |
| 283 | |
| 284 | acpi_device_write_uid(dev); |
| 285 | acpigen_write_name_string("_DDN", "LPSS ACPI UART"); |
| 286 | acpigen_write_STA(acpi_device_status(dev)); |
| 287 | |
| 288 | /* Resources */ |
| 289 | acpigen_write_name("_CRS"); |
| 290 | acpigen_write_resourcetemplate_header(); |
| 291 | |
| 292 | uart_acpi_write_irq(dev); |
| 293 | acpigen_write_mem32fixed(1, res->base, res->size); |
| 294 | |
| 295 | acpigen_write_resourcetemplate_footer(); |
| 296 | |
| 297 | acpigen_pop_len(); /* Device */ |
| 298 | acpigen_pop_len(); /* Scope */ |
| 299 | } |
| 300 | |
| 301 | static const char *uart_acpi_hid(const struct device *dev) |
| 302 | { |
| 303 | switch (dev->device) { |
| 304 | case PCI_DEVICE_ID_INTEL_APL_UART0: |
| 305 | return "80865abc"; |
| 306 | case PCI_DEVICE_ID_INTEL_APL_UART1: |
| 307 | return "80865abe"; |
| 308 | case PCI_DEVICE_ID_INTEL_APL_UART2: |
| 309 | return "80865ac0"; |
| 310 | case PCI_DEVICE_ID_INTEL_GLK_UART0: |
| 311 | return "808631bc"; |
| 312 | case PCI_DEVICE_ID_INTEL_GLK_UART1: |
| 313 | return "808631be"; |
| 314 | case PCI_DEVICE_ID_INTEL_GLK_UART2: |
| 315 | return "808631c0"; |
| 316 | case PCI_DEVICE_ID_INTEL_GLK_UART3: |
| 317 | return "808631ee"; |
| 318 | case PCI_DEVICE_ID_INTEL_SPT_UART0: |
| 319 | case PCI_DEVICE_ID_INTEL_SPT_H_UART0: |
| 320 | return "INT3448"; |
| 321 | case PCI_DEVICE_ID_INTEL_SPT_UART1: |
| 322 | case PCI_DEVICE_ID_INTEL_SPT_H_UART1: |
| 323 | return "INT3449"; |
| 324 | case PCI_DEVICE_ID_INTEL_SPT_UART2: |
| 325 | case PCI_DEVICE_ID_INTEL_SPT_H_UART2: |
| 326 | return "INT344A"; |
| 327 | case PCI_DEVICE_ID_INTEL_CNP_H_UART0: |
| 328 | return "INT34B8"; |
| 329 | case PCI_DEVICE_ID_INTEL_CNP_H_UART1: |
| 330 | return "INT34B9"; |
| 331 | case PCI_DEVICE_ID_INTEL_CNP_H_UART2: |
| 332 | return "INT34BA"; |
| 333 | default: |
| 334 | return NULL; |
| 335 | } |
| 336 | } |
| 337 | |
| 338 | static const char *uart_acpi_name(const struct device *dev) |
| 339 | { |
| 340 | switch (dev->device) { |
| 341 | case PCI_DEVICE_ID_INTEL_APL_UART0: |
| 342 | case PCI_DEVICE_ID_INTEL_GLK_UART0: |
| 343 | case PCI_DEVICE_ID_INTEL_SPT_UART0: |
| 344 | case PCI_DEVICE_ID_INTEL_SPT_H_UART0: |
| 345 | case PCI_DEVICE_ID_INTEL_CNP_H_UART0: |
| 346 | return "UAR0"; |
| 347 | case PCI_DEVICE_ID_INTEL_APL_UART1: |
| 348 | case PCI_DEVICE_ID_INTEL_GLK_UART1: |
| 349 | case PCI_DEVICE_ID_INTEL_SPT_UART1: |
| 350 | case PCI_DEVICE_ID_INTEL_SPT_H_UART1: |
| 351 | case PCI_DEVICE_ID_INTEL_CNP_H_UART1: |
| 352 | return "UAR1"; |
| 353 | case PCI_DEVICE_ID_INTEL_APL_UART2: |
| 354 | case PCI_DEVICE_ID_INTEL_GLK_UART2: |
| 355 | case PCI_DEVICE_ID_INTEL_SPT_UART2: |
| 356 | case PCI_DEVICE_ID_INTEL_SPT_H_UART2: |
| 357 | case PCI_DEVICE_ID_INTEL_CNP_H_UART2: |
| 358 | return "UAR2"; |
| 359 | case PCI_DEVICE_ID_INTEL_GLK_UART3: |
| 360 | return "UAR3"; |
| 361 | default: |
| 362 | return NULL; |
| 363 | } |
| 364 | } |
| 365 | |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 366 | static struct device_operations device_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 367 | .read_resources = uart_read_resources, |
| 368 | .set_resources = pci_dev_set_resources, |
| 369 | .enable_resources = uart_common_enable_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 370 | .ops_pci = &pci_dev_ops_pci, |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 371 | .acpi_fill_ssdt = uart_fill_ssdt, |
| 372 | .acpi_hid = uart_acpi_hid, |
| 373 | .acpi_name = uart_acpi_name, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 374 | }; |
| 375 | |
| 376 | static const unsigned short pci_device_ids[] = { |
| 377 | PCI_DEVICE_ID_INTEL_SPT_UART0, |
| 378 | PCI_DEVICE_ID_INTEL_SPT_UART1, |
| 379 | PCI_DEVICE_ID_INTEL_SPT_UART2, |
V Sowmya | 7c15047 | 2018-01-23 14:44:45 +0530 | [diff] [blame] | 380 | PCI_DEVICE_ID_INTEL_SPT_H_UART0, |
| 381 | PCI_DEVICE_ID_INTEL_SPT_H_UART1, |
| 382 | PCI_DEVICE_ID_INTEL_SPT_H_UART2, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 383 | PCI_DEVICE_ID_INTEL_KBP_H_UART0, |
| 384 | PCI_DEVICE_ID_INTEL_KBP_H_UART1, |
| 385 | PCI_DEVICE_ID_INTEL_KBP_H_UART2, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 386 | PCI_DEVICE_ID_INTEL_APL_UART0, |
| 387 | PCI_DEVICE_ID_INTEL_APL_UART1, |
| 388 | PCI_DEVICE_ID_INTEL_APL_UART2, |
| 389 | PCI_DEVICE_ID_INTEL_APL_UART3, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 390 | PCI_DEVICE_ID_INTEL_CNL_UART0, |
| 391 | PCI_DEVICE_ID_INTEL_CNL_UART1, |
| 392 | PCI_DEVICE_ID_INTEL_CNL_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 393 | PCI_DEVICE_ID_INTEL_GLK_UART0, |
| 394 | PCI_DEVICE_ID_INTEL_GLK_UART1, |
| 395 | PCI_DEVICE_ID_INTEL_GLK_UART2, |
| 396 | PCI_DEVICE_ID_INTEL_GLK_UART3, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 397 | PCI_DEVICE_ID_INTEL_CNP_H_UART0, |
| 398 | PCI_DEVICE_ID_INTEL_CNP_H_UART1, |
| 399 | PCI_DEVICE_ID_INTEL_CNP_H_UART2, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 400 | PCI_DEVICE_ID_INTEL_ICP_UART0, |
| 401 | PCI_DEVICE_ID_INTEL_ICP_UART1, |
| 402 | PCI_DEVICE_ID_INTEL_ICP_UART2, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 403 | PCI_DEVICE_ID_INTEL_CMP_UART0, |
| 404 | PCI_DEVICE_ID_INTEL_CMP_UART1, |
| 405 | PCI_DEVICE_ID_INTEL_CMP_UART2, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 406 | PCI_DEVICE_ID_INTEL_CMP_H_UART0, |
| 407 | PCI_DEVICE_ID_INTEL_CMP_H_UART1, |
| 408 | PCI_DEVICE_ID_INTEL_CMP_H_UART2, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 409 | PCI_DEVICE_ID_INTEL_TGP_UART0, |
| 410 | PCI_DEVICE_ID_INTEL_TGP_UART1, |
| 411 | PCI_DEVICE_ID_INTEL_TGP_UART2, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 412 | PCI_DEVICE_ID_INTEL_MCC_UART0, |
| 413 | PCI_DEVICE_ID_INTEL_MCC_UART1, |
| 414 | PCI_DEVICE_ID_INTEL_MCC_UART2, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 415 | PCI_DEVICE_ID_INTEL_JSP_UART0, |
| 416 | PCI_DEVICE_ID_INTEL_JSP_UART1, |
| 417 | PCI_DEVICE_ID_INTEL_JSP_UART2, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 418 | PCI_DEVICE_ID_INTEL_ADP_S_UART0, |
| 419 | PCI_DEVICE_ID_INTEL_ADP_S_UART1, |
| 420 | PCI_DEVICE_ID_INTEL_ADP_S_UART2, |
| 421 | PCI_DEVICE_ID_INTEL_ADP_S_UART3, |
| 422 | PCI_DEVICE_ID_INTEL_ADP_S_UART4, |
| 423 | PCI_DEVICE_ID_INTEL_ADP_S_UART5, |
| 424 | PCI_DEVICE_ID_INTEL_ADP_S_UART6, |
| 425 | PCI_DEVICE_ID_INTEL_ADP_P_UART0, |
| 426 | PCI_DEVICE_ID_INTEL_ADP_P_UART1, |
| 427 | PCI_DEVICE_ID_INTEL_ADP_P_UART2, |
| 428 | PCI_DEVICE_ID_INTEL_ADP_P_UART3, |
| 429 | PCI_DEVICE_ID_INTEL_ADP_P_UART4, |
| 430 | PCI_DEVICE_ID_INTEL_ADP_P_UART5, |
| 431 | PCI_DEVICE_ID_INTEL_ADP_P_UART6, |
Varshit Pandya | f4d98fdd2 | 2021-01-17 18:39:29 +0530 | [diff] [blame^] | 432 | PCI_DEVICE_ID_INTEL_ADP_M_UART0, |
| 433 | PCI_DEVICE_ID_INTEL_ADP_M_UART1, |
| 434 | PCI_DEVICE_ID_INTEL_ADP_M_UART2, |
| 435 | PCI_DEVICE_ID_INTEL_ADP_M_UART3, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 436 | 0, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 437 | }; |
| 438 | |
| 439 | static const struct pci_driver pch_uart __pci_driver = { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 440 | .ops = &device_ops, |
| 441 | .vendor = PCI_VENDOR_ID_INTEL, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 442 | .devices = pci_device_ids, |
| 443 | }; |
Patrick Rudolph | 49ae596 | 2020-04-15 11:19:31 +0200 | [diff] [blame] | 444 | |
| 445 | static void uart_enable(struct device *dev) |
| 446 | { |
| 447 | struct soc_intel_common_block_uart_config *conf = dev->chip_info; |
| 448 | dev->ops = &device_ops; |
| 449 | dev->device = conf ? conf->devid : 0; |
| 450 | } |
| 451 | |
| 452 | struct chip_operations soc_intel_common_block_uart_ops = { |
| 453 | CHIP_NAME("LPSS UART in ACPI mode") |
| 454 | .enable_dev = uart_enable |
| 455 | }; |
| 456 | |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 457 | #endif /* ENV_RAMSTAGE */ |