| Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <device/pci_def.h> |
| 17 | #include <intelblocks/lpss.h> |
| 18 | #include <intelblocks/uart.h> |
| 19 | |
| 20 | void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, |
| 21 | uint32_t clk_n_val) |
| 22 | { |
| 23 | /* Set UART base address */ |
| 24 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 25 | |
| 26 | /* Enable memory access and bus master */ |
| 27 | pci_write_config32(dev, PCI_COMMAND, |
| 28 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 29 | |
| 30 | /* Take UART out of reset */ |
| 31 | lpss_reset_release(baseaddr); |
| 32 | |
| 33 | /* Set M and N divisor inputs and enable clock */ |
| 34 | lpss_clk_update(baseaddr, clk_m_val, clk_n_val); |
| 35 | } |