soc/intel/common/uart: Refactor uart_common_init
1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index e8f1bc8..be30464 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -19,8 +19,17 @@
#include <intelblocks/lpss.h>
#include <intelblocks/uart.h>
-void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val,
- uint32_t clk_n_val)
+static void uart_lpss_init(uintptr_t baseaddr)
+{
+ /* Take UART out of reset */
+ lpss_reset_release(baseaddr);
+
+ /* Set M and N divisor inputs and enable clock */
+ lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
+ CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
+}
+
+void uart_common_init(device_t dev, uintptr_t baseaddr)
{
/* Set UART base address */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
@@ -29,11 +38,8 @@
pci_write_config32(dev, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
- /* Take UART out of reset */
- lpss_reset_release(baseaddr);
+ uart_lpss_init(baseaddr);
- /* Set M and N divisor inputs and enable clock */
- lpss_clk_update(baseaddr, clk_m_val, clk_n_val);
}
#if ENV_RAMSTAGE