Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 4 | * Copyright (C) 2017-2018 Intel Corporation. |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 15 | |
| 16 | #include <arch/acpi.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 17 | #include <cbmem.h> |
| 18 | #include <console/uart.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 19 | #include <device/device.h> |
| 20 | #include <device/pci.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 22 | #include <device/pci_ids.h> |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 23 | #include <device/pci_ops.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 24 | #include <intelblocks/lpss.h> |
| 25 | #include <intelblocks/uart.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/iomap.h> |
| 28 | #include <soc/nvs.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 29 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 30 | #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 31 | #define UART_CONSOLE_INVALID_INDEX 0xFF |
| 32 | |
| 33 | extern const struct uart_gpio_pad_config uart_gpio_pads[]; |
| 34 | extern const int uart_max_index; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 35 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 36 | static void uart_lpss_init(uintptr_t baseaddr) |
| 37 | { |
| 38 | /* Take UART out of reset */ |
| 39 | lpss_reset_release(baseaddr); |
| 40 | |
| 41 | /* Set M and N divisor inputs and enable clock */ |
| 42 | lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, |
| 43 | CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); |
| 44 | } |
| 45 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 46 | #if CONFIG(DRIVERS_UART_8250MEM) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 47 | uintptr_t uart_platform_base(int idx) |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 48 | { |
Nico Huber | ce8eebd | 2019-05-29 18:33:35 +0200 | [diff] [blame^] | 49 | if (idx == CONFIG_UART_FOR_CONSOLE) |
| 50 | return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); |
| 51 | return 0; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 52 | } |
| 53 | #endif |
| 54 | |
| 55 | static int uart_get_valid_index(void) |
| 56 | { |
| 57 | int index; |
| 58 | |
| 59 | for (index = 0; index < uart_max_index; index++) { |
| 60 | if (uart_gpio_pads[index].console_index == |
| 61 | CONFIG_UART_FOR_CONSOLE) |
| 62 | return index; |
| 63 | } |
| 64 | /* For valid index, code should not reach here */ |
| 65 | return UART_CONSOLE_INVALID_INDEX; |
| 66 | } |
| 67 | |
| 68 | void uart_common_init(struct device *device, uintptr_t baseaddr) |
| 69 | { |
| 70 | #if defined(__SIMPLE_DEVICE__) |
| 71 | pci_devfn_t dev = (pci_devfn_t)(uintptr_t)device; |
| 72 | #else |
| 73 | struct device *dev = device; |
| 74 | #endif |
| 75 | if (!dev) |
| 76 | return; |
| 77 | |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 78 | /* Set UART base address */ |
| 79 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 80 | |
| 81 | /* Enable memory access and bus master */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 82 | pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 83 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 84 | uart_lpss_init(baseaddr); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 85 | } |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 86 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 87 | struct device *uart_get_device(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 88 | { |
| 89 | /* |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 90 | * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE |
| 91 | * config option is not selected. |
| 92 | * By default return NULL in this case to avoid compilation errors. |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 93 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 94 | if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 95 | return NULL; |
| 96 | |
| 97 | int console_index = uart_get_valid_index(); |
| 98 | |
| 99 | if (console_index != UART_CONSOLE_INVALID_INDEX) |
| 100 | return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE); |
| 101 | else |
| 102 | return NULL; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 103 | } |
| 104 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 105 | bool uart_is_controller_initialized(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 106 | { |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 107 | uintptr_t base; |
| 108 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 109 | #if defined(__SIMPLE_DEVICE__) |
| 110 | pci_devfn_t dev = (pci_devfn_t)(uintptr_t)uart_get_device(); |
| 111 | #else |
| 112 | struct device *dev = uart_get_device(); |
| 113 | #endif |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 114 | if (!dev) |
| 115 | return false; |
| 116 | |
| 117 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 118 | if (!base) |
| 119 | return false; |
| 120 | |
| 121 | if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE) |
| 122 | != UART_PCI_ENABLE) |
| 123 | return false; |
| 124 | |
| 125 | return !lpss_is_controller_in_reset(base); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 126 | } |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 127 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 128 | static void uart_configure_gpio_pads(void) |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 129 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 130 | int index = uart_get_valid_index(); |
| 131 | |
| 132 | if (index != UART_CONSOLE_INVALID_INDEX) |
| 133 | gpio_configure_pads(uart_gpio_pads[index].gpios, |
| 134 | MAX_GPIO_PAD_PER_UART); |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 135 | } |
| 136 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 137 | void uart_bootblock_init(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 138 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 139 | /* Program UART BAR0, command, reset and clock register */ |
| 140 | uart_common_init(uart_get_device(), |
| 141 | UART_BASE(CONFIG_UART_FOR_CONSOLE)); |
| 142 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 143 | /* Configure the 2 pads per UART. */ |
| 144 | uart_configure_gpio_pads(); |
| 145 | } |
| 146 | |
| 147 | #if ENV_RAMSTAGE |
| 148 | |
| 149 | static void uart_read_resources(struct device *dev) |
| 150 | { |
| 151 | pci_dev_read_resources(dev); |
| 152 | |
| 153 | /* Set the configured UART base address for the debug port */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 154 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 155 | uart_is_debug_controller(dev)) { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 156 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 157 | /* Need to set the base and size for the resource allocator. */ |
| 158 | res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); |
| 159 | res->size = UART_BASE_SIZE; |
| 160 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 161 | IORESOURCE_FIXED; |
| 162 | } |
| 163 | } |
| 164 | |
| 165 | /* |
| 166 | * Check if UART debug port controller needs to be initialized on resume. |
| 167 | * |
| 168 | * Returns: |
| 169 | * true = when SoC wants debug port initialization on resume |
| 170 | * false = otherwise |
| 171 | */ |
| 172 | static bool pch_uart_init_debug_controller_on_resume(void) |
| 173 | { |
| 174 | global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 175 | |
| 176 | if (gnvs) |
| 177 | return !!gnvs->uior; |
| 178 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 179 | return false; |
| 180 | } |
| 181 | |
| 182 | bool uart_is_debug_controller(struct device *dev) |
| 183 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 184 | return dev == uart_get_device(); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 185 | } |
| 186 | |
| 187 | /* |
| 188 | * This is a workaround to enable UART controller for the debug port if: |
| 189 | * 1. CONSOLE_SERIAL is not enabled in coreboot, and |
| 190 | * 2. This boot is S3 resume, and |
| 191 | * 3. SoC wants to initialize debug UART controller. |
| 192 | * |
| 193 | * This workaround is required because Linux kernel hangs on resume if console |
| 194 | * is not enabled in coreboot, but it is enabled in kernel and not suspended. |
| 195 | */ |
| 196 | static bool uart_controller_needs_init(struct device *dev) |
| 197 | { |
| 198 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 199 | * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 200 | * controller here. |
| 201 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 202 | if (CONFIG(CONSOLE_SERIAL)) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 203 | return false; |
| 204 | |
| 205 | /* If this device does not correspond to debug port, then skip. */ |
| 206 | if (!uart_is_debug_controller(dev)) |
| 207 | return false; |
| 208 | |
| 209 | /* Initialize UART controller only on S3 resume. */ |
| 210 | if (!acpi_is_wakeup_s3()) |
| 211 | return false; |
| 212 | |
| 213 | /* |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 214 | * check if SOC wants to initialize UART on resume |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 215 | */ |
| 216 | return pch_uart_init_debug_controller_on_resume(); |
| 217 | } |
| 218 | |
| 219 | static void uart_common_enable_resources(struct device *dev) |
| 220 | { |
| 221 | pci_dev_enable_resources(dev); |
| 222 | |
| 223 | if (uart_controller_needs_init(dev)) { |
| 224 | uintptr_t base; |
| 225 | |
| 226 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 227 | if (base) |
| 228 | uart_lpss_init(base); |
| 229 | } |
| 230 | } |
| 231 | |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 232 | static struct device_operations device_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 233 | .read_resources = uart_read_resources, |
| 234 | .set_resources = pci_dev_set_resources, |
| 235 | .enable_resources = uart_common_enable_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 236 | .ops_pci = &pci_dev_ops_pci, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 237 | }; |
| 238 | |
| 239 | static const unsigned short pci_device_ids[] = { |
| 240 | PCI_DEVICE_ID_INTEL_SPT_UART0, |
| 241 | PCI_DEVICE_ID_INTEL_SPT_UART1, |
| 242 | PCI_DEVICE_ID_INTEL_SPT_UART2, |
V Sowmya | 7c15047 | 2018-01-23 14:44:45 +0530 | [diff] [blame] | 243 | PCI_DEVICE_ID_INTEL_SPT_H_UART0, |
| 244 | PCI_DEVICE_ID_INTEL_SPT_H_UART1, |
| 245 | PCI_DEVICE_ID_INTEL_SPT_H_UART2, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 246 | PCI_DEVICE_ID_INTEL_KBP_H_UART0, |
| 247 | PCI_DEVICE_ID_INTEL_KBP_H_UART1, |
| 248 | PCI_DEVICE_ID_INTEL_KBP_H_UART2, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 249 | PCI_DEVICE_ID_INTEL_APL_UART0, |
| 250 | PCI_DEVICE_ID_INTEL_APL_UART1, |
| 251 | PCI_DEVICE_ID_INTEL_APL_UART2, |
| 252 | PCI_DEVICE_ID_INTEL_APL_UART3, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 253 | PCI_DEVICE_ID_INTEL_CNL_UART0, |
| 254 | PCI_DEVICE_ID_INTEL_CNL_UART1, |
| 255 | PCI_DEVICE_ID_INTEL_CNL_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 256 | PCI_DEVICE_ID_INTEL_GLK_UART0, |
| 257 | PCI_DEVICE_ID_INTEL_GLK_UART1, |
| 258 | PCI_DEVICE_ID_INTEL_GLK_UART2, |
| 259 | PCI_DEVICE_ID_INTEL_GLK_UART3, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 260 | PCI_DEVICE_ID_INTEL_CNP_H_UART0, |
| 261 | PCI_DEVICE_ID_INTEL_CNP_H_UART1, |
| 262 | PCI_DEVICE_ID_INTEL_CNP_H_UART2, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 263 | PCI_DEVICE_ID_INTEL_ICP_UART0, |
| 264 | PCI_DEVICE_ID_INTEL_ICP_UART1, |
| 265 | PCI_DEVICE_ID_INTEL_ICP_UART2, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 266 | PCI_DEVICE_ID_INTEL_CMP_UART0, |
| 267 | PCI_DEVICE_ID_INTEL_CMP_UART1, |
| 268 | PCI_DEVICE_ID_INTEL_CMP_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 269 | 0, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 270 | }; |
| 271 | |
| 272 | static const struct pci_driver pch_uart __pci_driver = { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 273 | .ops = &device_ops, |
| 274 | .vendor = PCI_VENDOR_ID_INTEL, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 275 | .devices = pci_device_ids, |
| 276 | }; |
| 277 | #endif /* ENV_RAMSTAGE */ |