Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 4 | * Copyright (C) 2017-2018 Intel Corporation. |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 15 | |
| 16 | #include <arch/acpi.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 17 | #include <assert.h> |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 18 | #include <compiler.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 19 | #include <cbmem.h> |
| 20 | #include <console/uart.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 23 | #include <device/pci_def.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 24 | #include <device/pci_ids.h> |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 25 | #include <device/pci_ops.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 26 | #include <intelblocks/lpss.h> |
| 27 | #include <intelblocks/uart.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 28 | #include <soc/pci_devs.h> |
| 29 | #include <soc/iomap.h> |
| 30 | #include <soc/nvs.h> |
| 31 | #include <string.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 32 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 33 | #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 34 | #define UART_CONSOLE_INVALID_INDEX 0xFF |
| 35 | |
| 36 | extern const struct uart_gpio_pad_config uart_gpio_pads[]; |
| 37 | extern const int uart_max_index; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 38 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 39 | static void uart_lpss_init(uintptr_t baseaddr) |
| 40 | { |
| 41 | /* Take UART out of reset */ |
| 42 | lpss_reset_release(baseaddr); |
| 43 | |
| 44 | /* Set M and N divisor inputs and enable clock */ |
| 45 | lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, |
| 46 | CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); |
| 47 | } |
| 48 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 49 | #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) |
| 50 | uintptr_t uart_platform_base(int idx) |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 51 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 52 | /* return Base address for UART console index */ |
| 53 | return UART_BASE_0_ADDR(idx); |
| 54 | } |
| 55 | #endif |
| 56 | |
| 57 | static int uart_get_valid_index(void) |
| 58 | { |
| 59 | int index; |
| 60 | |
| 61 | for (index = 0; index < uart_max_index; index++) { |
| 62 | if (uart_gpio_pads[index].console_index == |
| 63 | CONFIG_UART_FOR_CONSOLE) |
| 64 | return index; |
| 65 | } |
| 66 | /* For valid index, code should not reach here */ |
| 67 | return UART_CONSOLE_INVALID_INDEX; |
| 68 | } |
| 69 | |
| 70 | void uart_common_init(struct device *device, uintptr_t baseaddr) |
| 71 | { |
| 72 | #if defined(__SIMPLE_DEVICE__) |
| 73 | pci_devfn_t dev = (pci_devfn_t)(uintptr_t)device; |
| 74 | #else |
| 75 | struct device *dev = device; |
| 76 | #endif |
| 77 | if (!dev) |
| 78 | return; |
| 79 | |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 80 | /* Set UART base address */ |
| 81 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 82 | |
| 83 | /* Enable memory access and bus master */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 84 | pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 85 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 86 | uart_lpss_init(baseaddr); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 87 | } |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 88 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 89 | struct device *uart_get_device(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 90 | { |
| 91 | /* |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 92 | * This function will get called even if UART_DEBUG config options is |
| 93 | * not selected. |
| 94 | * By default returning NULL in case CONFIG_UART_DEBUG option is not |
| 95 | * selected to avoid compilation errors. |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 96 | */ |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 97 | if (!IS_ENABLED(CONFIG_UART_DEBUG)) |
| 98 | return NULL; |
| 99 | |
| 100 | int console_index = uart_get_valid_index(); |
| 101 | |
| 102 | if (console_index != UART_CONSOLE_INVALID_INDEX) |
| 103 | return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE); |
| 104 | else |
| 105 | return NULL; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 106 | } |
| 107 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 108 | bool uart_is_controller_initialized(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 109 | { |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 110 | uintptr_t base; |
| 111 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 112 | #if defined(__SIMPLE_DEVICE__) |
| 113 | pci_devfn_t dev = (pci_devfn_t)(uintptr_t)uart_get_device(); |
| 114 | #else |
| 115 | struct device *dev = uart_get_device(); |
| 116 | #endif |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 117 | if (!dev) |
| 118 | return false; |
| 119 | |
| 120 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 121 | if (!base) |
| 122 | return false; |
| 123 | |
| 124 | if ((pci_read_config32(dev, PCI_COMMAND) & UART_PCI_ENABLE) |
| 125 | != UART_PCI_ENABLE) |
| 126 | return false; |
| 127 | |
| 128 | return !lpss_is_controller_in_reset(base); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 129 | } |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 130 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 131 | static void uart_configure_gpio_pads(void) |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 132 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 133 | int index = uart_get_valid_index(); |
| 134 | |
| 135 | if (index != UART_CONSOLE_INVALID_INDEX) |
| 136 | gpio_configure_pads(uart_gpio_pads[index].gpios, |
| 137 | MAX_GPIO_PAD_PER_UART); |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 138 | } |
| 139 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 140 | void uart_bootblock_init(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 141 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 142 | /* Program UART BAR0, command, reset and clock register */ |
| 143 | uart_common_init(uart_get_device(), |
| 144 | UART_BASE(CONFIG_UART_FOR_CONSOLE)); |
| 145 | |
| 146 | if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) |
| 147 | /* Put UART in byte access mode for 16550 compatibility */ |
| 148 | soc_uart_set_legacy_mode(); |
| 149 | |
| 150 | /* Configure the 2 pads per UART. */ |
| 151 | uart_configure_gpio_pads(); |
| 152 | } |
| 153 | |
| 154 | #if ENV_RAMSTAGE |
| 155 | |
| 156 | static void uart_read_resources(struct device *dev) |
| 157 | { |
| 158 | pci_dev_read_resources(dev); |
| 159 | |
| 160 | /* Set the configured UART base address for the debug port */ |
| 161 | if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { |
| 162 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 163 | /* Need to set the base and size for the resource allocator. */ |
| 164 | res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE); |
| 165 | res->size = UART_BASE_SIZE; |
| 166 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 167 | IORESOURCE_FIXED; |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | /* |
| 172 | * Check if UART debug port controller needs to be initialized on resume. |
| 173 | * |
| 174 | * Returns: |
| 175 | * true = when SoC wants debug port initialization on resume |
| 176 | * false = otherwise |
| 177 | */ |
| 178 | static bool pch_uart_init_debug_controller_on_resume(void) |
| 179 | { |
| 180 | global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 181 | |
| 182 | if (gnvs) |
| 183 | return !!gnvs->uior; |
| 184 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 185 | return false; |
| 186 | } |
| 187 | |
| 188 | bool uart_is_debug_controller(struct device *dev) |
| 189 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 190 | return dev == uart_get_device(); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | /* |
| 194 | * This is a workaround to enable UART controller for the debug port if: |
| 195 | * 1. CONSOLE_SERIAL is not enabled in coreboot, and |
| 196 | * 2. This boot is S3 resume, and |
| 197 | * 3. SoC wants to initialize debug UART controller. |
| 198 | * |
| 199 | * This workaround is required because Linux kernel hangs on resume if console |
| 200 | * is not enabled in coreboot, but it is enabled in kernel and not suspended. |
| 201 | */ |
| 202 | static bool uart_controller_needs_init(struct device *dev) |
| 203 | { |
| 204 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 205 | * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 206 | * controller here. |
| 207 | */ |
| 208 | if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) |
| 209 | return false; |
| 210 | |
| 211 | /* If this device does not correspond to debug port, then skip. */ |
| 212 | if (!uart_is_debug_controller(dev)) |
| 213 | return false; |
| 214 | |
| 215 | /* Initialize UART controller only on S3 resume. */ |
| 216 | if (!acpi_is_wakeup_s3()) |
| 217 | return false; |
| 218 | |
| 219 | /* |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 220 | * check if SOC wants to initialize UART on resume |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 221 | */ |
| 222 | return pch_uart_init_debug_controller_on_resume(); |
| 223 | } |
| 224 | |
| 225 | static void uart_common_enable_resources(struct device *dev) |
| 226 | { |
| 227 | pci_dev_enable_resources(dev); |
| 228 | |
| 229 | if (uart_controller_needs_init(dev)) { |
| 230 | uintptr_t base; |
| 231 | |
| 232 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 233 | if (base) |
| 234 | uart_lpss_init(base); |
| 235 | } |
| 236 | } |
| 237 | |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 238 | static struct device_operations device_ops = { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 239 | .read_resources = &uart_read_resources, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 240 | .set_resources = &pci_dev_set_resources, |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 241 | .enable_resources = &uart_common_enable_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 242 | .ops_pci = &pci_dev_ops_pci, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | static const unsigned short pci_device_ids[] = { |
| 246 | PCI_DEVICE_ID_INTEL_SPT_UART0, |
| 247 | PCI_DEVICE_ID_INTEL_SPT_UART1, |
| 248 | PCI_DEVICE_ID_INTEL_SPT_UART2, |
V Sowmya | 7c15047 | 2018-01-23 14:44:45 +0530 | [diff] [blame] | 249 | PCI_DEVICE_ID_INTEL_SPT_H_UART0, |
| 250 | PCI_DEVICE_ID_INTEL_SPT_H_UART1, |
| 251 | PCI_DEVICE_ID_INTEL_SPT_H_UART2, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 252 | PCI_DEVICE_ID_INTEL_KBP_H_UART0, |
| 253 | PCI_DEVICE_ID_INTEL_KBP_H_UART1, |
| 254 | PCI_DEVICE_ID_INTEL_KBP_H_UART2, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 255 | PCI_DEVICE_ID_INTEL_APL_UART0, |
| 256 | PCI_DEVICE_ID_INTEL_APL_UART1, |
| 257 | PCI_DEVICE_ID_INTEL_APL_UART2, |
| 258 | PCI_DEVICE_ID_INTEL_APL_UART3, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 259 | PCI_DEVICE_ID_INTEL_CNL_UART0, |
| 260 | PCI_DEVICE_ID_INTEL_CNL_UART1, |
| 261 | PCI_DEVICE_ID_INTEL_CNL_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 262 | PCI_DEVICE_ID_INTEL_GLK_UART0, |
| 263 | PCI_DEVICE_ID_INTEL_GLK_UART1, |
| 264 | PCI_DEVICE_ID_INTEL_GLK_UART2, |
| 265 | PCI_DEVICE_ID_INTEL_GLK_UART3, |
| 266 | 0, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 267 | }; |
| 268 | |
| 269 | static const struct pci_driver pch_uart __pci_driver = { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame^] | 270 | .ops = &device_ops, |
| 271 | .vendor = PCI_VENDOR_ID_INTEL, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 272 | .devices = pci_device_ids, |
| 273 | }; |
| 274 | #endif /* ENV_RAMSTAGE */ |