soc/intel: Replace UART_BASE() and friends with a Kconfig
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 84ba1ee..9d820ff 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -47,7 +47,7 @@
uintptr_t uart_platform_base(int idx)
{
if (idx == CONFIG_UART_FOR_CONSOLE)
- return UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);
+ return CONFIG_CONSOLE_UART_BASE_ADDRESS;
return 0;
}
#endif
@@ -137,8 +137,7 @@
void uart_bootblock_init(void)
{
/* Program UART BAR0, command, reset and clock register */
- uart_common_init(uart_get_device(),
- UART_BASE(CONFIG_UART_FOR_CONSOLE));
+ uart_common_init(uart_get_device(), CONFIG_CONSOLE_UART_BASE_ADDRESS);
/* Configure the 2 pads per UART. */
uart_configure_gpio_pads();
@@ -155,8 +154,8 @@
uart_is_debug_controller(dev)) {
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
/* Need to set the base and size for the resource allocator. */
- res->base = UART_BASE(CONFIG_UART_FOR_CONSOLE);
- res->size = UART_BASE_SIZE;
+ res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS;
+ res->size = 0x1000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED;
}