soc/intel/common: Set controller state to active in uart init
Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.
One more argument "const struct device *dev" has been added
to uart_lpss_init function.
BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
sequence in CML, ICL and APL platforms
Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34810
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index f556aed..364835d 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -33,8 +33,11 @@
extern const struct uart_gpio_pad_config uart_gpio_pads[];
extern const int uart_max_index;
-static void uart_lpss_init(uintptr_t baseaddr)
+static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr)
{
+ /* Ensure controller is in D0 state */
+ lpss_set_power_state(dev, STATE_D0);
+
/* Take UART out of reset */
lpss_reset_release(baseaddr);
@@ -79,7 +82,7 @@
/* Enable memory access and bus master */
pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE);
- uart_lpss_init(baseaddr);
+ uart_lpss_init(device, baseaddr);
}
const struct device *uart_get_device(void)
@@ -231,7 +234,7 @@
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF;
if (base)
- uart_lpss_init(base);
+ uart_lpss_init(dev, base);
}
}