| Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2017 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 15 | #include <device/device.h> |
| 16 | #include <device/pci.h> |
| Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 17 | #include <device/pci_def.h> |
| Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 18 | #include <device/pci_ids.h> |
| Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 19 | #include <intelblocks/lpss.h> |
| 20 | #include <intelblocks/uart.h> |
| 21 | |
| 22 | void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, |
| 23 | uint32_t clk_n_val) |
| 24 | { |
| 25 | /* Set UART base address */ |
| 26 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 27 | |
| 28 | /* Enable memory access and bus master */ |
| 29 | pci_write_config32(dev, PCI_COMMAND, |
| 30 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
| 31 | |
| 32 | /* Take UART out of reset */ |
| 33 | lpss_reset_release(baseaddr); |
| 34 | |
| 35 | /* Set M and N divisor inputs and enable clock */ |
| 36 | lpss_clk_update(baseaddr, clk_m_val, clk_n_val); |
| 37 | } |
| Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 38 | |
| 39 | #if ENV_RAMSTAGE |
| 40 | |
| 41 | __attribute__((weak)) void pch_uart_read_resources(struct device *dev) |
| 42 | { |
| 43 | pci_dev_read_resources(dev); |
| 44 | } |
| 45 | |
| 46 | static struct device_operations device_ops = { |
| 47 | .read_resources = &pch_uart_read_resources, |
| 48 | .set_resources = &pci_dev_set_resources, |
| 49 | .enable_resources = &pci_dev_enable_resources, |
| 50 | }; |
| 51 | |
| 52 | static const unsigned short pci_device_ids[] = { |
| 53 | PCI_DEVICE_ID_INTEL_SPT_UART0, |
| 54 | PCI_DEVICE_ID_INTEL_SPT_UART1, |
| 55 | PCI_DEVICE_ID_INTEL_SPT_UART2, |
| 56 | PCI_DEVICE_ID_INTEL_KBP_H_UART0, |
| 57 | PCI_DEVICE_ID_INTEL_KBP_H_UART1, |
| 58 | PCI_DEVICE_ID_INTEL_KBP_H_UART2, |
| 59 | PCI_DEVICE_ID_INTEL_APL_UART0, |
| 60 | PCI_DEVICE_ID_INTEL_APL_UART1, |
| 61 | PCI_DEVICE_ID_INTEL_APL_UART2, |
| 62 | PCI_DEVICE_ID_INTEL_APL_UART3, |
| Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame^] | 63 | PCI_DEVICE_ID_INTEL_CNL_UART0, |
| 64 | PCI_DEVICE_ID_INTEL_CNL_UART1, |
| 65 | PCI_DEVICE_ID_INTEL_CNL_UART2, |
| Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 66 | PCI_DEVICE_ID_INTEL_GLK_UART0, |
| 67 | PCI_DEVICE_ID_INTEL_GLK_UART1, |
| 68 | PCI_DEVICE_ID_INTEL_GLK_UART2, |
| 69 | PCI_DEVICE_ID_INTEL_GLK_UART3, |
| 70 | 0, |
| Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 71 | }; |
| 72 | |
| 73 | static const struct pci_driver pch_uart __pci_driver = { |
| 74 | .ops = &device_ops, |
| 75 | .vendor = PCI_VENDOR_ID_INTEL, |
| 76 | .devices = pci_device_ids, |
| 77 | }; |
| 78 | #endif /* ENV_RAMSTAGE */ |