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Aamir Bohra01d75f42017-03-30 20:12:21 +05301/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2017 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
Aamir Bohra83f7bae2017-04-26 19:30:41 +053015#include <device/device.h>
16#include <device/pci.h>
Aamir Bohra01d75f42017-03-30 20:12:21 +053017#include <device/pci_def.h>
Aamir Bohra83f7bae2017-04-26 19:30:41 +053018#include <device/pci_ids.h>
Aamir Bohra01d75f42017-03-30 20:12:21 +053019#include <intelblocks/lpss.h>
20#include <intelblocks/uart.h>
21
Furquan Shaikh3406dd62017-08-04 15:58:26 -070022static void uart_lpss_init(uintptr_t baseaddr)
23{
24 /* Take UART out of reset */
25 lpss_reset_release(baseaddr);
26
27 /* Set M and N divisor inputs and enable clock */
28 lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL,
29 CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL);
30}
31
32void uart_common_init(device_t dev, uintptr_t baseaddr)
Aamir Bohra01d75f42017-03-30 20:12:21 +053033{
34 /* Set UART base address */
35 pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr);
36
37 /* Enable memory access and bus master */
38 pci_write_config32(dev, PCI_COMMAND,
39 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
40
Furquan Shaikh3406dd62017-08-04 15:58:26 -070041 uart_lpss_init(baseaddr);
Aamir Bohra01d75f42017-03-30 20:12:21 +053042
Aamir Bohra01d75f42017-03-30 20:12:21 +053043}
Aamir Bohra83f7bae2017-04-26 19:30:41 +053044
45#if ENV_RAMSTAGE
46
47__attribute__((weak)) void pch_uart_read_resources(struct device *dev)
48{
49 pci_dev_read_resources(dev);
50}
51
52static struct device_operations device_ops = {
53 .read_resources = &pch_uart_read_resources,
54 .set_resources = &pci_dev_set_resources,
55 .enable_resources = &pci_dev_enable_resources,
56};
57
58static const unsigned short pci_device_ids[] = {
59 PCI_DEVICE_ID_INTEL_SPT_UART0,
60 PCI_DEVICE_ID_INTEL_SPT_UART1,
61 PCI_DEVICE_ID_INTEL_SPT_UART2,
62 PCI_DEVICE_ID_INTEL_KBP_H_UART0,
63 PCI_DEVICE_ID_INTEL_KBP_H_UART1,
64 PCI_DEVICE_ID_INTEL_KBP_H_UART2,
65 PCI_DEVICE_ID_INTEL_APL_UART0,
66 PCI_DEVICE_ID_INTEL_APL_UART1,
67 PCI_DEVICE_ID_INTEL_APL_UART2,
68 PCI_DEVICE_ID_INTEL_APL_UART3,
Lijian Zhaobbedef92017-07-29 16:38:38 -070069 PCI_DEVICE_ID_INTEL_CNL_UART0,
70 PCI_DEVICE_ID_INTEL_CNL_UART1,
71 PCI_DEVICE_ID_INTEL_CNL_UART2,
Hannah Williamsf7149652017-05-13 16:18:02 -070072 PCI_DEVICE_ID_INTEL_GLK_UART0,
73 PCI_DEVICE_ID_INTEL_GLK_UART1,
74 PCI_DEVICE_ID_INTEL_GLK_UART2,
75 PCI_DEVICE_ID_INTEL_GLK_UART3,
76 0,
Aamir Bohra83f7bae2017-04-26 19:30:41 +053077};
78
79static const struct pci_driver pch_uart __pci_driver = {
80 .ops = &device_ops,
81 .vendor = PCI_VENDOR_ID_INTEL,
82 .devices = pci_device_ids,
83};
84#endif /* ENV_RAMSTAGE */