Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 3 | |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame^] | 4 | #include <acpi/acpi.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 5 | #include <cbmem.h> |
| 6 | #include <console/uart.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 9 | #include <device/pci_def.h> |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 10 | #include <device/pci_ids.h> |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 11 | #include <device/pci_ops.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 12 | #include <intelblocks/lpss.h> |
| 13 | #include <intelblocks/uart.h> |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 14 | #include <soc/pci_devs.h> |
| 15 | #include <soc/iomap.h> |
| 16 | #include <soc/nvs.h> |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 17 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 18 | #define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 19 | #define UART_CONSOLE_INVALID_INDEX 0xFF |
| 20 | |
| 21 | extern const struct uart_gpio_pad_config uart_gpio_pads[]; |
| 22 | extern const int uart_max_index; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 23 | |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 24 | static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 25 | { |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 26 | /* Ensure controller is in D0 state */ |
| 27 | lpss_set_power_state(dev, STATE_D0); |
| 28 | |
Furquan Shaikh | 3406dd6 | 2017-08-04 15:58:26 -0700 | [diff] [blame] | 29 | /* Take UART out of reset */ |
| 30 | lpss_reset_release(baseaddr); |
| 31 | |
| 32 | /* Set M and N divisor inputs and enable clock */ |
| 33 | lpss_clk_update(baseaddr, CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL, |
| 34 | CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL); |
| 35 | } |
| 36 | |
Nico Huber | 62ddc49 | 2019-05-29 18:39:31 +0200 | [diff] [blame] | 37 | #if CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 38 | uintptr_t uart_platform_base(int idx) |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 39 | { |
Nico Huber | ce8eebd | 2019-05-29 18:33:35 +0200 | [diff] [blame] | 40 | if (idx == CONFIG_UART_FOR_CONSOLE) |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 41 | return CONFIG_CONSOLE_UART_BASE_ADDRESS; |
Nico Huber | ce8eebd | 2019-05-29 18:33:35 +0200 | [diff] [blame] | 42 | return 0; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 43 | } |
| 44 | #endif |
| 45 | |
| 46 | static int uart_get_valid_index(void) |
| 47 | { |
| 48 | int index; |
| 49 | |
| 50 | for (index = 0; index < uart_max_index; index++) { |
| 51 | if (uart_gpio_pads[index].console_index == |
| 52 | CONFIG_UART_FOR_CONSOLE) |
| 53 | return index; |
| 54 | } |
| 55 | /* For valid index, code should not reach here */ |
| 56 | return UART_CONSOLE_INVALID_INDEX; |
| 57 | } |
| 58 | |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 59 | void uart_common_init(const struct device *device, uintptr_t baseaddr) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 60 | { |
| 61 | #if defined(__SIMPLE_DEVICE__) |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 62 | pci_devfn_t dev = PCI_BDF(device); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 63 | #else |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 64 | const struct device *dev = device; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 65 | #endif |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 66 | |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 67 | /* Set UART base address */ |
| 68 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, baseaddr); |
| 69 | |
| 70 | /* Enable memory access and bus master */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 71 | pci_write_config16(dev, PCI_COMMAND, UART_PCI_ENABLE); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 72 | |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 73 | uart_lpss_init(device, baseaddr); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 74 | } |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 75 | |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 76 | const struct device *uart_get_device(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 77 | { |
| 78 | /* |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 79 | * This function will get called even if INTEL_LPSS_UART_FOR_CONSOLE |
| 80 | * config option is not selected. |
| 81 | * By default return NULL in this case to avoid compilation errors. |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 82 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 83 | if (!CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 84 | return NULL; |
| 85 | |
| 86 | int console_index = uart_get_valid_index(); |
| 87 | |
| 88 | if (console_index != UART_CONSOLE_INVALID_INDEX) |
| 89 | return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE); |
| 90 | else |
| 91 | return NULL; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 94 | bool uart_is_controller_initialized(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 95 | { |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 96 | uintptr_t base; |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 97 | const struct device *dev_uart = uart_get_device(); |
| 98 | |
| 99 | if (!dev_uart) |
| 100 | return false; |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 101 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 102 | #if defined(__SIMPLE_DEVICE__) |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 103 | pci_devfn_t dev = PCI_BDF(dev_uart); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 104 | #else |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 105 | const struct device *dev = dev_uart; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 106 | #endif |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 107 | |
| 108 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 109 | if (!base) |
| 110 | return false; |
| 111 | |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 112 | if ((pci_read_config16(dev, PCI_COMMAND) & UART_PCI_ENABLE) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 113 | != UART_PCI_ENABLE) |
| 114 | return false; |
| 115 | |
| 116 | return !lpss_is_controller_in_reset(base); |
Aamir Bohra | 01d75f4 | 2017-03-30 20:12:21 +0530 | [diff] [blame] | 117 | } |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 118 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 119 | static void uart_configure_gpio_pads(void) |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 120 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 121 | int index = uart_get_valid_index(); |
| 122 | |
| 123 | if (index != UART_CONSOLE_INVALID_INDEX) |
| 124 | gpio_configure_pads(uart_gpio_pads[index].gpios, |
| 125 | MAX_GPIO_PAD_PER_UART); |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 126 | } |
| 127 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 128 | void uart_bootblock_init(void) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 129 | { |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 130 | const struct device *dev_uart; |
| 131 | |
| 132 | dev_uart = uart_get_device(); |
| 133 | |
| 134 | if (!dev_uart) |
| 135 | return; |
| 136 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 137 | /* Program UART BAR0, command, reset and clock register */ |
Aamir Bohra | 17cfba6 | 2019-07-25 20:56:54 +0530 | [diff] [blame] | 138 | uart_common_init(dev_uart, CONFIG_CONSOLE_UART_BASE_ADDRESS); |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 139 | |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 140 | /* Configure the 2 pads per UART. */ |
| 141 | uart_configure_gpio_pads(); |
| 142 | } |
| 143 | |
| 144 | #if ENV_RAMSTAGE |
| 145 | |
| 146 | static void uart_read_resources(struct device *dev) |
| 147 | { |
| 148 | pci_dev_read_resources(dev); |
| 149 | |
| 150 | /* Set the configured UART base address for the debug port */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 151 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE) && |
Nico Huber | a96e66a | 2018-11-11 02:51:14 +0100 | [diff] [blame] | 152 | uart_is_debug_controller(dev)) { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 153 | struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); |
| 154 | /* Need to set the base and size for the resource allocator. */ |
Nico Huber | 9995418 | 2019-05-29 23:33:06 +0200 | [diff] [blame] | 155 | res->base = CONFIG_CONSOLE_UART_BASE_ADDRESS; |
| 156 | res->size = 0x1000; |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 157 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | |
| 158 | IORESOURCE_FIXED; |
| 159 | } |
| 160 | } |
| 161 | |
| 162 | /* |
| 163 | * Check if UART debug port controller needs to be initialized on resume. |
| 164 | * |
| 165 | * Returns: |
| 166 | * true = when SoC wants debug port initialization on resume |
| 167 | * false = otherwise |
| 168 | */ |
| 169 | static bool pch_uart_init_debug_controller_on_resume(void) |
| 170 | { |
| 171 | global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 172 | |
| 173 | if (gnvs) |
| 174 | return !!gnvs->uior; |
| 175 | |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 176 | return false; |
| 177 | } |
| 178 | |
| 179 | bool uart_is_debug_controller(struct device *dev) |
| 180 | { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 181 | return dev == uart_get_device(); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | /* |
| 185 | * This is a workaround to enable UART controller for the debug port if: |
| 186 | * 1. CONSOLE_SERIAL is not enabled in coreboot, and |
| 187 | * 2. This boot is S3 resume, and |
| 188 | * 3. SoC wants to initialize debug UART controller. |
| 189 | * |
| 190 | * This workaround is required because Linux kernel hangs on resume if console |
| 191 | * is not enabled in coreboot, but it is enabled in kernel and not suspended. |
| 192 | */ |
| 193 | static bool uart_controller_needs_init(struct device *dev) |
| 194 | { |
| 195 | /* |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 196 | * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 197 | * controller here. |
| 198 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 199 | if (CONFIG(CONSOLE_SERIAL)) |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 200 | return false; |
| 201 | |
| 202 | /* If this device does not correspond to debug port, then skip. */ |
| 203 | if (!uart_is_debug_controller(dev)) |
| 204 | return false; |
| 205 | |
| 206 | /* Initialize UART controller only on S3 resume. */ |
| 207 | if (!acpi_is_wakeup_s3()) |
| 208 | return false; |
| 209 | |
| 210 | /* |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 211 | * check if SOC wants to initialize UART on resume |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 212 | */ |
| 213 | return pch_uart_init_debug_controller_on_resume(); |
| 214 | } |
| 215 | |
| 216 | static void uart_common_enable_resources(struct device *dev) |
| 217 | { |
| 218 | pci_dev_enable_resources(dev); |
| 219 | |
| 220 | if (uart_controller_needs_init(dev)) { |
| 221 | uintptr_t base; |
| 222 | |
| 223 | base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; |
| 224 | if (base) |
Usha P | 5e59a82 | 2019-08-09 18:42:00 +0530 | [diff] [blame] | 225 | uart_lpss_init(dev, base); |
Furquan Shaikh | a8198eb | 2017-08-04 16:12:19 -0700 | [diff] [blame] | 226 | } |
| 227 | } |
| 228 | |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 229 | static struct device_operations device_ops = { |
Elyes HAOUAS | 1d19127 | 2018-11-27 12:23:48 +0100 | [diff] [blame] | 230 | .read_resources = uart_read_resources, |
| 231 | .set_resources = pci_dev_set_resources, |
| 232 | .enable_resources = uart_common_enable_resources, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 233 | .ops_pci = &pci_dev_ops_pci, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 234 | }; |
| 235 | |
| 236 | static const unsigned short pci_device_ids[] = { |
| 237 | PCI_DEVICE_ID_INTEL_SPT_UART0, |
| 238 | PCI_DEVICE_ID_INTEL_SPT_UART1, |
| 239 | PCI_DEVICE_ID_INTEL_SPT_UART2, |
V Sowmya | 7c15047 | 2018-01-23 14:44:45 +0530 | [diff] [blame] | 240 | PCI_DEVICE_ID_INTEL_SPT_H_UART0, |
| 241 | PCI_DEVICE_ID_INTEL_SPT_H_UART1, |
| 242 | PCI_DEVICE_ID_INTEL_SPT_H_UART2, |
V Sowmya | acc2a48 | 2018-01-23 15:27:23 +0530 | [diff] [blame] | 243 | PCI_DEVICE_ID_INTEL_KBP_H_UART0, |
| 244 | PCI_DEVICE_ID_INTEL_KBP_H_UART1, |
| 245 | PCI_DEVICE_ID_INTEL_KBP_H_UART2, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 246 | PCI_DEVICE_ID_INTEL_APL_UART0, |
| 247 | PCI_DEVICE_ID_INTEL_APL_UART1, |
| 248 | PCI_DEVICE_ID_INTEL_APL_UART2, |
| 249 | PCI_DEVICE_ID_INTEL_APL_UART3, |
Lijian Zhao | bbedef9 | 2017-07-29 16:38:38 -0700 | [diff] [blame] | 250 | PCI_DEVICE_ID_INTEL_CNL_UART0, |
| 251 | PCI_DEVICE_ID_INTEL_CNL_UART1, |
| 252 | PCI_DEVICE_ID_INTEL_CNL_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 253 | PCI_DEVICE_ID_INTEL_GLK_UART0, |
| 254 | PCI_DEVICE_ID_INTEL_GLK_UART1, |
| 255 | PCI_DEVICE_ID_INTEL_GLK_UART2, |
| 256 | PCI_DEVICE_ID_INTEL_GLK_UART3, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 257 | PCI_DEVICE_ID_INTEL_CNP_H_UART0, |
| 258 | PCI_DEVICE_ID_INTEL_CNP_H_UART1, |
| 259 | PCI_DEVICE_ID_INTEL_CNP_H_UART2, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 260 | PCI_DEVICE_ID_INTEL_ICP_UART0, |
| 261 | PCI_DEVICE_ID_INTEL_ICP_UART1, |
| 262 | PCI_DEVICE_ID_INTEL_ICP_UART2, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 263 | PCI_DEVICE_ID_INTEL_CMP_UART0, |
| 264 | PCI_DEVICE_ID_INTEL_CMP_UART1, |
| 265 | PCI_DEVICE_ID_INTEL_CMP_UART2, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 266 | PCI_DEVICE_ID_INTEL_CMP_H_UART0, |
| 267 | PCI_DEVICE_ID_INTEL_CMP_H_UART1, |
| 268 | PCI_DEVICE_ID_INTEL_CMP_H_UART2, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 269 | PCI_DEVICE_ID_INTEL_TGP_UART0, |
| 270 | PCI_DEVICE_ID_INTEL_TGP_UART1, |
| 271 | PCI_DEVICE_ID_INTEL_TGP_UART2, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 272 | PCI_DEVICE_ID_INTEL_MCC_UART0, |
| 273 | PCI_DEVICE_ID_INTEL_MCC_UART1, |
| 274 | PCI_DEVICE_ID_INTEL_MCC_UART2, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 275 | PCI_DEVICE_ID_INTEL_JSP_UART0, |
| 276 | PCI_DEVICE_ID_INTEL_JSP_UART1, |
| 277 | PCI_DEVICE_ID_INTEL_JSP_UART2, |
Hannah Williams | f714965 | 2017-05-13 16:18:02 -0700 | [diff] [blame] | 278 | 0, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 279 | }; |
| 280 | |
| 281 | static const struct pci_driver pch_uart __pci_driver = { |
Subrata Banik | afa07f7 | 2018-05-24 12:21:06 +0530 | [diff] [blame] | 282 | .ops = &device_ops, |
| 283 | .vendor = PCI_VENDOR_ID_INTEL, |
Aamir Bohra | 83f7bae | 2017-04-26 19:30:41 +0530 | [diff] [blame] | 284 | .devices = pci_device_ids, |
| 285 | }; |
| 286 | #endif /* ENV_RAMSTAGE */ |