Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 2 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 5 | #include <assert.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
| 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
| 12 | #include <device/pci_ops.h> |
| 13 | #include <intelblocks/cse.h> |
Subrata Banik | 80c9289 | 2022-02-01 00:26:55 +0530 | [diff] [blame] | 14 | #include <intelblocks/pmclib.h> |
Martin Roth | 8c97450 | 2022-11-20 17:56:44 -0700 | [diff] [blame] | 15 | #include <intelblocks/post_codes.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 16 | #include <option.h> |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 17 | #include <security/vboot/misc.h> |
| 18 | #include <security/vboot/vboot_common.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 19 | #include <soc/intel/common/reset.h> |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 20 | #include <soc/iomap.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 21 | #include <soc/pci_devs.h> |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 22 | #include <soc/me.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 23 | #include <string.h> |
| 24 | #include <timer.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 25 | #include <types.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 26 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 27 | #define HECI_BASE_SIZE (4 * KiB) |
| 28 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 29 | #define MAX_HECI_MESSAGE_RETRY_COUNT 5 |
| 30 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 31 | /* Wait up to 15 sec for HECI to get ready */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 32 | #define HECI_DELAY_READY_MS (15 * 1000) |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 33 | /* Wait up to 100 usec between circular buffer polls */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 34 | #define HECI_DELAY_US 100 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 35 | /* Wait up to 5 sec for CSE to chew something we sent */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 36 | #define HECI_SEND_TIMEOUT_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 37 | /* Wait up to 5 sec for CSE to blurp a reply */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 38 | #define HECI_READ_TIMEOUT_MS (5 * 1000) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 39 | /* Wait up to 1 ms for CSE CIP */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 40 | #define HECI_CIP_TIMEOUT_US 1000 |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 41 | /* Wait up to 5 seconds for CSE to boot from RO(BP1) */ |
| 42 | #define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 43 | |
| 44 | #define SLOT_SIZE sizeof(uint32_t) |
| 45 | |
| 46 | #define MMIO_CSE_CB_WW 0x00 |
| 47 | #define MMIO_HOST_CSR 0x04 |
| 48 | #define MMIO_CSE_CB_RW 0x08 |
| 49 | #define MMIO_CSE_CSR 0x0c |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 50 | #define MMIO_CSE_DEVIDLE 0x800 |
| 51 | #define CSE_DEV_IDLE (1 << 2) |
| 52 | #define CSE_DEV_CIP (1 << 0) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 53 | |
| 54 | #define CSR_IE (1 << 0) |
| 55 | #define CSR_IS (1 << 1) |
| 56 | #define CSR_IG (1 << 2) |
| 57 | #define CSR_READY (1 << 3) |
| 58 | #define CSR_RESET (1 << 4) |
| 59 | #define CSR_RP_START 8 |
| 60 | #define CSR_RP (((1 << 8) - 1) << CSR_RP_START) |
| 61 | #define CSR_WP_START 16 |
| 62 | #define CSR_WP (((1 << 8) - 1) << CSR_WP_START) |
| 63 | #define CSR_CBD_START 24 |
| 64 | #define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) |
| 65 | |
| 66 | #define MEI_HDR_IS_COMPLETE (1 << 31) |
| 67 | #define MEI_HDR_LENGTH_START 16 |
| 68 | #define MEI_HDR_LENGTH_SIZE 9 |
| 69 | #define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ |
| 70 | << MEI_HDR_LENGTH_START) |
| 71 | #define MEI_HDR_HOST_ADDR_START 8 |
| 72 | #define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) |
| 73 | #define MEI_HDR_CSE_ADDR_START 0 |
| 74 | #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) |
| 75 | |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 76 | /* Get HECI BAR 0 from PCI configuration space */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 77 | static uintptr_t get_cse_bar(pci_devfn_t dev) |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 78 | { |
| 79 | uintptr_t bar; |
| 80 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 81 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 82 | assert(bar != 0); |
| 83 | /* |
| 84 | * Bits 31-12 are the base address as per EDS for SPI, |
| 85 | * Don't care about 0-11 bit |
| 86 | */ |
| 87 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 88 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 89 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 90 | static void heci_assign_resource(pci_devfn_t dev, uintptr_t tempbar) |
| 91 | { |
| 92 | u16 pcireg; |
| 93 | |
| 94 | /* Assign Resources */ |
| 95 | /* Clear BIT 1-2 of Command Register */ |
| 96 | pcireg = pci_read_config16(dev, PCI_COMMAND); |
| 97 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 98 | pci_write_config16(dev, PCI_COMMAND, pcireg); |
| 99 | |
| 100 | /* Program Temporary BAR for HECI device */ |
| 101 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); |
| 102 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); |
| 103 | |
| 104 | /* Enable Bus Master and MMIO Space */ |
| 105 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 106 | } |
| 107 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 108 | /* |
Subrata Banik | 0b92aa6 | 2022-06-01 06:54:44 +0000 | [diff] [blame] | 109 | * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 110 | * default. This is intended for pre-mem usage only where BARs haven't been |
| 111 | * assigned yet and devices are not enabled. |
| 112 | */ |
Subrata Banik | 0b92aa6 | 2022-06-01 06:54:44 +0000 | [diff] [blame] | 113 | void cse_init(uintptr_t tempbar) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 114 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 115 | pci_devfn_t dev = PCH_DEV_CSE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 116 | |
Matt DeVillier | f711bf0 | 2022-01-25 19:48:38 -0600 | [diff] [blame] | 117 | /* Check if device enabled */ |
| 118 | if (!is_cse_enabled()) |
| 119 | return; |
| 120 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 121 | /* Assume it is already initialized, nothing else to do */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 122 | if (get_cse_bar(dev)) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 123 | return; |
| 124 | |
| 125 | /* Use default pre-ram bar */ |
| 126 | if (!tempbar) |
| 127 | tempbar = HECI1_BASE_ADDRESS; |
| 128 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 129 | /* Assign HECI resource and enable the resource */ |
| 130 | heci_assign_resource(dev, tempbar); |
Sridhar Siricilla | cb2fd20 | 2021-06-09 19:27:06 +0530 | [diff] [blame] | 131 | |
| 132 | /* Trigger HECI Reset and make Host ready for communication with CSE */ |
| 133 | heci_reset(); |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 134 | } |
| 135 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 136 | static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 137 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 138 | return read32p(get_cse_bar(dev) + offset); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 139 | } |
| 140 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 141 | static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 142 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 143 | return write32p(get_cse_bar(dev) + offset, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static uint32_t read_cse_csr(void) |
| 147 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 148 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | static uint32_t read_host_csr(void) |
| 152 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 153 | return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void write_host_csr(uint32_t data) |
| 157 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 158 | write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | static size_t filled_slots(uint32_t data) |
| 162 | { |
| 163 | uint8_t wp, rp; |
| 164 | rp = data >> CSR_RP_START; |
| 165 | wp = data >> CSR_WP_START; |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 166 | return (uint8_t)(wp - rp); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static size_t cse_filled_slots(void) |
| 170 | { |
| 171 | return filled_slots(read_cse_csr()); |
| 172 | } |
| 173 | |
| 174 | static size_t host_empty_slots(void) |
| 175 | { |
| 176 | uint32_t csr; |
| 177 | csr = read_host_csr(); |
| 178 | |
| 179 | return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr); |
| 180 | } |
| 181 | |
| 182 | static void clear_int(void) |
| 183 | { |
| 184 | uint32_t csr; |
| 185 | csr = read_host_csr(); |
| 186 | csr |= CSR_IS; |
| 187 | write_host_csr(csr); |
| 188 | } |
| 189 | |
| 190 | static uint32_t read_slot(void) |
| 191 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 192 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static void write_slot(uint32_t val) |
| 196 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 197 | write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static int wait_write_slots(size_t cnt) |
| 201 | { |
| 202 | struct stopwatch sw; |
| 203 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 204 | stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 205 | while (host_empty_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 206 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 207 | if (stopwatch_expired(&sw)) { |
| 208 | printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); |
| 209 | return 0; |
| 210 | } |
| 211 | } |
| 212 | return 1; |
| 213 | } |
| 214 | |
| 215 | static int wait_read_slots(size_t cnt) |
| 216 | { |
| 217 | struct stopwatch sw; |
| 218 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 219 | stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 220 | while (cse_filled_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 221 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 222 | if (stopwatch_expired(&sw)) { |
| 223 | printk(BIOS_ERR, "HECI: timed out reading answer!\n"); |
| 224 | return 0; |
| 225 | } |
| 226 | } |
| 227 | return 1; |
| 228 | } |
| 229 | |
| 230 | /* get number of full 4-byte slots */ |
| 231 | static size_t bytes_to_slots(size_t bytes) |
| 232 | { |
| 233 | return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; |
| 234 | } |
| 235 | |
| 236 | static int cse_ready(void) |
| 237 | { |
| 238 | uint32_t csr; |
| 239 | csr = read_cse_csr(); |
| 240 | return csr & CSR_READY; |
| 241 | } |
| 242 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 243 | static bool cse_check_hfs1_com(int mode) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 244 | { |
| 245 | union me_hfsts1 hfs1; |
| 246 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 247 | return hfs1.fields.operation_mode == mode; |
| 248 | } |
| 249 | |
Michał Żygowski | daa1710 | 2022-10-04 10:55:38 +0200 | [diff] [blame^] | 250 | static bool cse_is_hfs1_fw_init_complete(void) |
| 251 | { |
| 252 | union me_hfsts1 hfs1; |
| 253 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 254 | if (hfs1.fields.fw_init_complete) |
| 255 | return true; |
| 256 | return false; |
| 257 | } |
| 258 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 259 | bool cse_is_hfs1_cws_normal(void) |
| 260 | { |
| 261 | union me_hfsts1 hfs1; |
| 262 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 263 | if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL) |
| 264 | return true; |
| 265 | return false; |
| 266 | } |
| 267 | |
| 268 | bool cse_is_hfs1_com_normal(void) |
| 269 | { |
| 270 | return cse_check_hfs1_com(ME_HFS1_COM_NORMAL); |
| 271 | } |
| 272 | |
| 273 | bool cse_is_hfs1_com_secover_mei_msg(void) |
| 274 | { |
| 275 | return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); |
| 276 | } |
| 277 | |
| 278 | bool cse_is_hfs1_com_soft_temp_disable(void) |
| 279 | { |
| 280 | return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 281 | } |
| 282 | |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 283 | /* |
Sridhar Siricilla | 90a4393 | 2022-09-12 10:37:17 +0530 | [diff] [blame] | 284 | * Starting from TGL platform, HFSTS1.spi_protection_mode replaces mfg_mode to indicate |
| 285 | * SPI protection status as well as end-of-manufacturing(EOM) status where EOM flow is |
| 286 | * triggered in single staged operation (either through first boot with required MFIT |
| 287 | * configuratin or FPT /CLOSEMANUF). |
| 288 | * In staged manufacturing flow, spi_protection_mode alone doesn't indicate the EOM status. |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 289 | * |
Sridhar Siricilla | 90a4393 | 2022-09-12 10:37:17 +0530 | [diff] [blame] | 290 | * HFSTS1.spi_protection_mode description: |
| 291 | * mfg_mode = 0 means SPI protection is on. |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 292 | * mfg_mode = 1 means SPI is unprotected. |
| 293 | */ |
| 294 | bool cse_is_hfs1_spi_protected(void) |
| 295 | { |
| 296 | union me_hfsts1 hfs1; |
| 297 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 298 | return !hfs1.fields.mfg_mode; |
| 299 | } |
| 300 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 301 | bool cse_is_hfs3_fw_sku_lite(void) |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 302 | { |
| 303 | union me_hfsts3 hfs3; |
| 304 | hfs3.data = me_read_config32(PCI_ME_HFSTS3); |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 305 | return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE; |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 306 | } |
| 307 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 308 | /* Makes the host ready to communicate with CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 309 | void cse_set_host_ready(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 310 | { |
| 311 | uint32_t csr; |
| 312 | csr = read_host_csr(); |
| 313 | csr &= ~CSR_RESET; |
| 314 | csr |= (CSR_IG | CSR_READY); |
| 315 | write_host_csr(csr); |
| 316 | } |
| 317 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 318 | /* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */ |
| 319 | uint8_t cse_wait_sec_override_mode(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 320 | { |
| 321 | struct stopwatch sw; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 322 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 323 | while (!cse_is_hfs1_com_secover_mei_msg()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 324 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 325 | if (stopwatch_expired(&sw)) { |
| 326 | printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n"); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 327 | return 0; |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 328 | } |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 329 | } |
Rob Barnes | d522f38 | 2022-09-12 06:31:47 -0600 | [diff] [blame] | 330 | printk(BIOS_DEBUG, "HECI: CSE took %lld ms to enter security override mode\n", |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 331 | stopwatch_duration_msecs(&sw)); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 332 | return 1; |
| 333 | } |
| 334 | |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 335 | /* |
| 336 | * Polls for CSE's current operation mode 'Soft Temporary Disable'. |
| 337 | * The CSE enters the current operation mode when it boots from RO(BP1). |
| 338 | */ |
| 339 | uint8_t cse_wait_com_soft_temp_disable(void) |
| 340 | { |
| 341 | struct stopwatch sw; |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 342 | stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 343 | while (!cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 344 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 345 | if (stopwatch_expired(&sw)) { |
| 346 | printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); |
| 347 | return 0; |
| 348 | } |
| 349 | } |
Rob Barnes | d522f38 | 2022-09-12 06:31:47 -0600 | [diff] [blame] | 350 | printk(BIOS_SPEW, "HECI: CSE took %lld ms to boot from RO\n", |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 351 | stopwatch_duration_msecs(&sw)); |
| 352 | return 1; |
| 353 | } |
| 354 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 355 | static int wait_heci_ready(void) |
| 356 | { |
| 357 | struct stopwatch sw; |
| 358 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 359 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 360 | while (!cse_ready()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 361 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 362 | if (stopwatch_expired(&sw)) |
| 363 | return 0; |
| 364 | } |
| 365 | |
| 366 | return 1; |
| 367 | } |
| 368 | |
| 369 | static void host_gen_interrupt(void) |
| 370 | { |
| 371 | uint32_t csr; |
| 372 | csr = read_host_csr(); |
| 373 | csr |= CSR_IG; |
| 374 | write_host_csr(csr); |
| 375 | } |
| 376 | |
| 377 | static size_t hdr_get_length(uint32_t hdr) |
| 378 | { |
| 379 | return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START; |
| 380 | } |
| 381 | |
| 382 | static int |
| 383 | send_one_message(uint32_t hdr, const void *buff) |
| 384 | { |
| 385 | size_t pend_len, pend_slots, remainder, i; |
| 386 | uint32_t tmp; |
| 387 | const uint32_t *p = buff; |
| 388 | |
| 389 | /* Get space for the header */ |
| 390 | if (!wait_write_slots(1)) |
| 391 | return 0; |
| 392 | |
| 393 | /* First, write header */ |
| 394 | write_slot(hdr); |
| 395 | |
| 396 | pend_len = hdr_get_length(hdr); |
| 397 | pend_slots = bytes_to_slots(pend_len); |
| 398 | |
| 399 | if (!wait_write_slots(pend_slots)) |
| 400 | return 0; |
| 401 | |
| 402 | /* Write the body in whole slots */ |
| 403 | i = 0; |
| 404 | while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { |
| 405 | write_slot(*p++); |
| 406 | i += SLOT_SIZE; |
| 407 | } |
| 408 | |
| 409 | remainder = pend_len % SLOT_SIZE; |
| 410 | /* Pad to 4 bytes not touching caller's buffer */ |
| 411 | if (remainder) { |
| 412 | memcpy(&tmp, p, remainder); |
| 413 | write_slot(tmp); |
| 414 | } |
| 415 | |
| 416 | host_gen_interrupt(); |
| 417 | |
| 418 | /* Make sure nothing bad happened during transmission */ |
| 419 | if (!cse_ready()) |
| 420 | return 0; |
| 421 | |
| 422 | return pend_len; |
| 423 | } |
| 424 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 425 | /* |
| 426 | * Send message msg of size len to host from host_addr to cse_addr. |
Sridhar Siricilla | c760e41a | 2022-08-15 21:10:58 +0530 | [diff] [blame] | 427 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 428 | * Also, in case of errors, heci_reset() is triggered. |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 429 | */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 430 | static enum cse_tx_rx_status |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 431 | heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) |
| 432 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 433 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 434 | uint32_t csr, hdr; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 435 | size_t sent, remaining, cb_size, max_length; |
| 436 | const uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 437 | |
| 438 | if (!msg || !len) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 439 | return CSE_TX_ERR_INPUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 440 | |
| 441 | clear_int(); |
| 442 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 443 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 444 | p = msg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 445 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 446 | if (!wait_heci_ready()) { |
| 447 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 448 | continue; |
| 449 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 450 | |
Subrata Banik | 4a722f5 | 2017-11-13 14:56:42 +0530 | [diff] [blame] | 451 | csr = read_host_csr(); |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 452 | cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE; |
| 453 | /* |
| 454 | * Reserve one slot for the header. Limit max message |
| 455 | * length by 9 bits that are available in the header. |
| 456 | */ |
| 457 | max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) |
| 458 | - SLOT_SIZE; |
| 459 | remaining = len; |
| 460 | |
| 461 | /* |
| 462 | * Fragment the message into smaller messages not exceeding |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 463 | * useful circular buffer length. Mark last message complete. |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 464 | */ |
| 465 | do { |
| 466 | hdr = MIN(max_length, remaining) |
| 467 | << MEI_HDR_LENGTH_START; |
| 468 | hdr |= client_addr << MEI_HDR_CSE_ADDR_START; |
| 469 | hdr |= host_addr << MEI_HDR_HOST_ADDR_START; |
| 470 | hdr |= (MIN(max_length, remaining) == remaining) ? |
Lee Leahy | 68ab0b5 | 2017-03-10 13:42:34 -0800 | [diff] [blame] | 471 | MEI_HDR_IS_COMPLETE : 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 472 | sent = send_one_message(hdr, p); |
| 473 | p += sent; |
| 474 | remaining -= sent; |
| 475 | } while (remaining > 0 && sent != 0); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 476 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 477 | if (!remaining) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 478 | return CSE_TX_RX_SUCCESS; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 479 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 480 | |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 481 | printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n"); |
| 482 | heci_reset(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 483 | return CSE_TX_ERR_CSE_NOT_READY; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 484 | } |
| 485 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 486 | static enum cse_tx_rx_status |
| 487 | recv_one_message(uint32_t *hdr, void *buff, size_t maxlen, size_t *recv_len) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 488 | { |
| 489 | uint32_t reg, *p = buff; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 490 | size_t recv_slots, remainder, i; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 491 | |
| 492 | /* first get the header */ |
| 493 | if (!wait_read_slots(1)) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 494 | return CSE_RX_ERR_TIMEOUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 495 | |
| 496 | *hdr = read_slot(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 497 | *recv_len = hdr_get_length(*hdr); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 498 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 499 | if (!*recv_len) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 500 | printk(BIOS_WARNING, "HECI: message is zero-sized\n"); |
| 501 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 502 | recv_slots = bytes_to_slots(*recv_len); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 503 | |
| 504 | i = 0; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 505 | if (*recv_len > maxlen) { |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 506 | printk(BIOS_ERR, "HECI: response is too big\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 507 | return CSE_RX_ERR_RESP_LEN_MISMATCH; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 508 | } |
| 509 | |
| 510 | /* wait for the rest of messages to arrive */ |
| 511 | wait_read_slots(recv_slots); |
| 512 | |
| 513 | /* fetch whole slots first */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 514 | while (i < ALIGN_DOWN(*recv_len, SLOT_SIZE)) { |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 515 | *p++ = read_slot(); |
| 516 | i += SLOT_SIZE; |
| 517 | } |
| 518 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 519 | /* |
| 520 | * If ME is not ready, something went wrong and |
| 521 | * we received junk |
| 522 | */ |
| 523 | if (!cse_ready()) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 524 | return CSE_RX_ERR_CSE_NOT_READY; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 525 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 526 | remainder = *recv_len % SLOT_SIZE; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 527 | |
| 528 | if (remainder) { |
| 529 | reg = read_slot(); |
| 530 | memcpy(p, ®, remainder); |
| 531 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 532 | return CSE_TX_RX_SUCCESS; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 533 | } |
| 534 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 535 | /* |
| 536 | * Receive message into buff not exceeding maxlen. Message is considered |
| 537 | * successfully received if a 'complete' indication is read from ME side |
| 538 | * and there was enough space in the buffer to fit that message. maxlen |
Sridhar Siricilla | c760e41a | 2022-08-15 21:10:58 +0530 | [diff] [blame] | 539 | * is updated with size of message that was received. |
| 540 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 541 | * Also, in case of errors, heci_reset() is triggered. |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 542 | */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 543 | static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 544 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 545 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 546 | size_t left, received; |
| 547 | uint32_t hdr = 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 548 | uint8_t *p; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 549 | enum cse_tx_rx_status ret = CSE_RX_ERR_TIMEOUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 550 | |
| 551 | if (!buff || !maxlen || !*maxlen) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 552 | return CSE_RX_ERR_INPUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 553 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 554 | clear_int(); |
| 555 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 556 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 557 | p = buff; |
| 558 | left = *maxlen; |
| 559 | |
| 560 | if (!wait_heci_ready()) { |
| 561 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 562 | continue; |
| 563 | } |
| 564 | |
| 565 | /* |
| 566 | * Receive multiple packets until we meet one marked |
| 567 | * complete or we run out of space in caller-provided buffer. |
| 568 | */ |
| 569 | do { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 570 | ret = recv_one_message(&hdr, p, left, &received); |
| 571 | if (ret) { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 572 | printk(BIOS_ERR, "HECI: Failed to receive!\n"); |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 573 | goto CSE_RX_ERR_HANDLE; |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 574 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 575 | left -= received; |
| 576 | p += received; |
| 577 | /* If we read out everything ping to send more */ |
| 578 | if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots()) |
| 579 | host_gen_interrupt(); |
| 580 | } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); |
| 581 | |
| 582 | if ((hdr & MEI_HDR_IS_COMPLETE) && received) { |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 583 | *maxlen = p - (uint8_t *)buff; |
Johnny Lin | a3e68c9 | 2022-08-09 15:36:30 +0800 | [diff] [blame] | 584 | if (CONFIG(SOC_INTEL_CSE_SERVER_SKU)) |
| 585 | clear_int(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 586 | return CSE_TX_RX_SUCCESS; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 587 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 588 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 589 | |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 590 | CSE_RX_ERR_HANDLE: |
| 591 | printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n"); |
| 592 | heci_reset(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 593 | return CSE_RX_ERR_CSE_NOT_READY; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 594 | } |
| 595 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 596 | enum cse_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, |
| 597 | size_t *rcv_sz, uint8_t cse_addr) |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 598 | { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 599 | enum cse_tx_rx_status ret; |
| 600 | |
| 601 | ret = heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr); |
| 602 | if (ret) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 603 | printk(BIOS_ERR, "HECI: send Failed\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 604 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 605 | } |
| 606 | |
| 607 | if (rcv_msg != NULL) { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 608 | ret = heci_receive(rcv_msg, rcv_sz); |
| 609 | if (ret) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 610 | printk(BIOS_ERR, "HECI: receive Failed\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 611 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 612 | } |
| 613 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 614 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 615 | } |
| 616 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 617 | /* |
| 618 | * Attempt to reset the device. This is useful when host and ME are out |
| 619 | * of sync during transmission or ME didn't understand the message. |
| 620 | */ |
| 621 | int heci_reset(void) |
| 622 | { |
| 623 | uint32_t csr; |
| 624 | |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 625 | /* Clear post code to prevent eventlog entry from unknown code. */ |
Martin Roth | 8c97450 | 2022-11-20 17:56:44 -0700 | [diff] [blame] | 626 | post_code(POST_CODE_ZERO); |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 627 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 628 | /* Send reset request */ |
| 629 | csr = read_host_csr(); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 630 | csr |= (CSR_RESET | CSR_IG); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 631 | write_host_csr(csr); |
| 632 | |
| 633 | if (wait_heci_ready()) { |
| 634 | /* Device is back on its imaginary feet, clear reset */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 635 | cse_set_host_ready(); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 636 | return 1; |
| 637 | } |
| 638 | |
| 639 | printk(BIOS_CRIT, "HECI: reset failed\n"); |
| 640 | |
| 641 | return 0; |
| 642 | } |
| 643 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 644 | bool is_cse_devfn_visible(unsigned int devfn) |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 645 | { |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 646 | int slot = PCI_SLOT(devfn); |
| 647 | int func = PCI_FUNC(devfn); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 648 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 649 | if (!is_devfn_enabled(devfn)) { |
| 650 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 651 | return false; |
| 652 | } |
| 653 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 654 | if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { |
| 655 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 656 | return false; |
| 657 | } |
| 658 | |
| 659 | return true; |
| 660 | } |
| 661 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 662 | bool is_cse_enabled(void) |
| 663 | { |
| 664 | return is_cse_devfn_visible(PCH_DEVFN_CSE); |
| 665 | } |
| 666 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 667 | uint32_t me_read_config32(int offset) |
| 668 | { |
| 669 | return pci_read_config32(PCH_DEV_CSE, offset); |
| 670 | } |
| 671 | |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 672 | static bool cse_is_global_reset_allowed(void) |
| 673 | { |
| 674 | /* |
| 675 | * Allow sending GLOBAL_RESET command only if: |
| 676 | * - CSE's current working state is Normal and current operation mode is Normal. |
| 677 | * - (or) CSE's current working state is normal and current operation mode can |
| 678 | * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 679 | * Lite. |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 680 | */ |
| 681 | if (!cse_is_hfs1_cws_normal()) |
| 682 | return false; |
| 683 | |
| 684 | if (cse_is_hfs1_com_normal()) |
| 685 | return true; |
| 686 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 687 | if (cse_is_hfs3_fw_sku_lite()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 688 | if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) |
| 689 | return true; |
| 690 | } |
| 691 | return false; |
| 692 | } |
| 693 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 694 | /* |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 695 | * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. |
| 696 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 697 | */ |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 698 | static int cse_request_reset(enum rst_req_type rst_type) |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 699 | { |
| 700 | int status; |
| 701 | struct mkhi_hdr reply; |
| 702 | struct reset_message { |
| 703 | struct mkhi_hdr hdr; |
| 704 | uint8_t req_origin; |
| 705 | uint8_t reset_type; |
| 706 | } __packed; |
| 707 | struct reset_message msg = { |
| 708 | .hdr = { |
| 709 | .group_id = MKHI_GROUP_ID_CBM, |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 710 | .command = MKHI_CBM_GLOBAL_RESET_REQ, |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 711 | }, |
| 712 | .req_origin = GR_ORIGIN_BIOS_POST, |
| 713 | .reset_type = rst_type |
| 714 | }; |
| 715 | size_t reply_size; |
| 716 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 717 | printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 718 | |
Sridhar Siricilla | c2a2d2b | 2020-02-27 17:16:13 +0530 | [diff] [blame] | 719 | if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 720 | printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); |
| 721 | return 0; |
| 722 | } |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 723 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 724 | if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 725 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 726 | return 0; |
| 727 | } |
| 728 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 729 | heci_reset(); |
| 730 | |
| 731 | reply_size = sizeof(reply); |
| 732 | memset(&reply, 0, reply_size); |
| 733 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 734 | if (rst_type == CSE_RESET_ONLY) |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 735 | status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 736 | else |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 737 | status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, |
| 738 | HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 739 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 740 | printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", !status ? "success" : "failure"); |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 741 | return status; |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 742 | } |
| 743 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 744 | int cse_request_global_reset(void) |
| 745 | { |
| 746 | return cse_request_reset(GLOBAL_RESET); |
| 747 | } |
| 748 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 749 | static bool cse_is_hmrfpo_enable_allowed(void) |
| 750 | { |
| 751 | /* |
| 752 | * Allow sending HMRFPO ENABLE command only if: |
| 753 | * - CSE's current working state is Normal and current operation mode is Normal |
| 754 | * - (or) cse's current working state is normal and current operation mode is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 755 | * Soft Temp Disable if CSE's Firmware SKU is Lite |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 756 | */ |
| 757 | if (!cse_is_hfs1_cws_normal()) |
| 758 | return false; |
| 759 | |
| 760 | if (cse_is_hfs1_com_normal()) |
| 761 | return true; |
| 762 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 763 | if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable()) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 764 | return true; |
| 765 | |
| 766 | return false; |
| 767 | } |
| 768 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 769 | /* Sends HMRFPO Enable command to CSE */ |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 770 | enum cb_err cse_hmrfpo_enable(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 771 | { |
| 772 | struct hmrfpo_enable_msg { |
| 773 | struct mkhi_hdr hdr; |
| 774 | uint32_t nonce[2]; |
| 775 | } __packed; |
| 776 | |
| 777 | /* HMRFPO Enable message */ |
| 778 | struct hmrfpo_enable_msg msg = { |
| 779 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 780 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 781 | .command = MKHI_HMRFPO_ENABLE, |
| 782 | }, |
| 783 | .nonce = {0}, |
| 784 | }; |
| 785 | |
| 786 | /* HMRFPO Enable response */ |
| 787 | struct hmrfpo_enable_resp { |
| 788 | struct mkhi_hdr hdr; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 789 | /* Base addr for factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 790 | uint32_t fct_base; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 791 | /* Length of factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 792 | uint32_t fct_limit; |
| 793 | uint8_t status; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 794 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 795 | } __packed; |
| 796 | |
| 797 | struct hmrfpo_enable_resp resp; |
| 798 | size_t resp_size = sizeof(struct hmrfpo_enable_resp); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 799 | |
Sridhar Siricilla | 49c25f2 | 2021-11-27 19:56:47 +0530 | [diff] [blame] | 800 | if (cse_is_hfs1_com_secover_mei_msg()) { |
| 801 | printk(BIOS_DEBUG, "HECI: CSE is already in security override mode, " |
| 802 | "skip sending HMRFPO_ENABLE command to CSE\n"); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 803 | return CB_SUCCESS; |
Sridhar Siricilla | 49c25f2 | 2021-11-27 19:56:47 +0530 | [diff] [blame] | 804 | } |
| 805 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 806 | printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 807 | |
| 808 | if (!cse_is_hmrfpo_enable_allowed()) { |
| 809 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 810 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 811 | } |
| 812 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 813 | if (heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 814 | &resp, &resp_size, HECI_MKHI_ADDR)) |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 815 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 816 | |
| 817 | if (resp.hdr.result) { |
| 818 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 819 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 820 | } |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 821 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 822 | if (resp.status) { |
| 823 | printk(BIOS_ERR, "HECI: HMRFPO_Enable Failed (resp status: %d)\n", resp.status); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 824 | return CB_ERR; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 825 | } |
| 826 | |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 827 | return CB_SUCCESS; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 828 | } |
| 829 | |
| 830 | /* |
| 831 | * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 832 | * The status can be DISABLED/LOCKED/ENABLED |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 833 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 834 | int cse_hmrfpo_get_status(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 835 | { |
| 836 | struct hmrfpo_get_status_msg { |
| 837 | struct mkhi_hdr hdr; |
| 838 | } __packed; |
| 839 | |
| 840 | struct hmrfpo_get_status_resp { |
| 841 | struct mkhi_hdr hdr; |
| 842 | uint8_t status; |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 843 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 844 | } __packed; |
| 845 | |
| 846 | struct hmrfpo_get_status_msg msg = { |
| 847 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 848 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 849 | .command = MKHI_HMRFPO_GET_STATUS, |
| 850 | }, |
| 851 | }; |
| 852 | struct hmrfpo_get_status_resp resp; |
| 853 | size_t resp_size = sizeof(struct hmrfpo_get_status_resp); |
| 854 | |
| 855 | printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); |
| 856 | |
Sridhar Siricilla | 206905c | 2020-02-06 18:48:22 +0530 | [diff] [blame] | 857 | if (!cse_is_hfs1_cws_normal()) { |
| 858 | printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); |
| 859 | return -1; |
| 860 | } |
| 861 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 862 | if (heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 863 | &resp, &resp_size, HECI_MKHI_ADDR)) { |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 864 | printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); |
| 865 | return -1; |
| 866 | } |
| 867 | |
| 868 | if (resp.hdr.result) { |
| 869 | printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", |
| 870 | resp.hdr.result); |
| 871 | return -1; |
| 872 | } |
| 873 | |
| 874 | return resp.status; |
| 875 | } |
| 876 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 877 | void print_me_fw_version(void *unused) |
| 878 | { |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 879 | struct me_fw_ver_resp resp = {0}; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 880 | |
| 881 | /* Ignore if UART debugging is disabled */ |
| 882 | if (!CONFIG(CONSOLE_SERIAL)) |
| 883 | return; |
| 884 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 885 | if (get_me_fw_version(&resp) == CB_SUCCESS) { |
| 886 | printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, |
| 887 | resp.code.minor, resp.code.hotfix, resp.code.build); |
| 888 | return; |
| 889 | } |
| 890 | printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); |
| 891 | } |
| 892 | |
| 893 | enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) |
| 894 | { |
| 895 | const struct mkhi_hdr fw_ver_msg = { |
| 896 | .group_id = MKHI_GROUP_ID_GEN, |
| 897 | .command = MKHI_GEN_GET_FW_VERSION, |
| 898 | }; |
| 899 | |
| 900 | if (resp == NULL) { |
| 901 | printk(BIOS_ERR, "%s failed, null pointer parameter\n", __func__); |
| 902 | return CB_ERR; |
| 903 | } |
| 904 | size_t resp_size = sizeof(*resp); |
| 905 | |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 906 | /* Ignore if CSE is disabled */ |
| 907 | if (!is_cse_enabled()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 908 | return CB_ERR; |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 909 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 910 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 911 | * Ignore if ME Firmware SKU type is Lite since |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 912 | * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. |
| 913 | */ |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 914 | if (cse_is_hfs3_fw_sku_lite()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 915 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 916 | |
| 917 | /* |
| 918 | * Prerequisites: |
| 919 | * 1) HFSTS1 Current Working State is Normal |
| 920 | * 2) HFSTS1 Current Operation Mode is Normal |
| 921 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 922 | * during ramstage |
| 923 | */ |
| 924 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 925 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 926 | |
| 927 | heci_reset(); |
| 928 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 929 | if (heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 930 | HECI_MKHI_ADDR)) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 931 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 932 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 933 | if (resp->hdr.result) |
| 934 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 935 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 936 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 937 | return CB_SUCCESS; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 938 | } |
| 939 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 940 | void cse_trigger_vboot_recovery(enum csme_failure_reason reason) |
| 941 | { |
| 942 | printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " |
| 943 | "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), |
| 944 | me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); |
| 945 | |
Jakub Czapiga | 605f793 | 2022-11-04 12:18:04 +0000 | [diff] [blame] | 946 | if (CONFIG(VBOOT)) |
| 947 | vboot_fail_and_reboot(vboot_get_context(), VB2_RECOVERY_INTEL_CSE_LITE_SKU, |
| 948 | reason); |
| 949 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 950 | die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); |
| 951 | } |
| 952 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 953 | static bool disable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 954 | { |
| 955 | struct stopwatch sw; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 956 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 957 | dev_idle_ctrl &= ~CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 958 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 959 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 960 | stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 961 | do { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 962 | dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 963 | if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) |
| 964 | return true; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 965 | udelay(HECI_DELAY_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 966 | } while (!stopwatch_expired(&sw)); |
| 967 | |
| 968 | return false; |
| 969 | } |
| 970 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 971 | static void enable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 972 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 973 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 974 | dev_idle_ctrl |= CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 975 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 976 | } |
| 977 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 978 | enum cse_device_state get_cse_device_state(unsigned int devfn) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 979 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 980 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 981 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 982 | if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) |
| 983 | return DEV_IDLE; |
| 984 | |
| 985 | return DEV_ACTIVE; |
| 986 | } |
| 987 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 988 | static enum cse_device_state ensure_cse_active(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 989 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 990 | if (!disable_cse_idle(dev)) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 991 | return DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 992 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 993 | |
| 994 | return DEV_ACTIVE; |
| 995 | } |
| 996 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 997 | static void ensure_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 998 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 999 | enable_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1000 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1001 | pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1002 | } |
| 1003 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1004 | bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1005 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1006 | enum cse_device_state current_state = get_cse_device_state(devfn); |
| 1007 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1008 | |
| 1009 | if (current_state == requested_state) |
| 1010 | return true; |
| 1011 | |
| 1012 | if (requested_state == DEV_ACTIVE) |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1013 | return ensure_cse_active(dev) == requested_state; |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1014 | else |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1015 | ensure_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1016 | |
| 1017 | return true; |
| 1018 | } |
| 1019 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1020 | void cse_set_to_d0i3(void) |
| 1021 | { |
| 1022 | if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) |
| 1023 | return; |
| 1024 | |
| 1025 | set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); |
| 1026 | } |
| 1027 | |
| 1028 | /* Function to set D0I3 for all HECI devices */ |
| 1029 | void heci_set_to_d0i3(void) |
| 1030 | { |
| 1031 | for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { |
Subrata Banik | 5790956 | 2022-06-02 00:25:36 +0530 | [diff] [blame] | 1032 | unsigned int devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); |
Subrata Banik | 01bf002 | 2022-04-06 18:59:37 +0530 | [diff] [blame] | 1033 | if (!is_cse_devfn_visible(devfn)) |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1034 | continue; |
| 1035 | |
Subrata Banik | 01bf002 | 2022-04-06 18:59:37 +0530 | [diff] [blame] | 1036 | set_cse_device_state(devfn, DEV_IDLE); |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1037 | } |
| 1038 | } |
| 1039 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 1040 | /* Initialize the HECI devices. */ |
| 1041 | void heci_init(void) |
| 1042 | { |
| 1043 | for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { |
| 1044 | unsigned int devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); |
| 1045 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 1046 | |
| 1047 | if (!is_cse_devfn_visible(devfn)) |
| 1048 | continue; |
| 1049 | |
| 1050 | /* Assume it is already initialized, nothing else to do */ |
| 1051 | if (get_cse_bar(dev)) |
| 1052 | return; |
| 1053 | |
| 1054 | heci_assign_resource(dev, HECI1_BASE_ADDRESS + (i * HECI_BASE_SIZE)); |
| 1055 | |
| 1056 | ensure_cse_active(dev); |
| 1057 | } |
| 1058 | /* Trigger HECI Reset and make Host ready for communication with CSE */ |
| 1059 | heci_reset(); |
| 1060 | } |
| 1061 | |
Subrata Banik | 80c9289 | 2022-02-01 00:26:55 +0530 | [diff] [blame] | 1062 | void cse_control_global_reset_lock(void) |
| 1063 | { |
| 1064 | /* |
| 1065 | * As per ME BWG recommendation the BIOS should not lock down CF9GR bit during |
| 1066 | * manufacturing and re-manufacturing environment if HFSTS1 [4] is set. Note: |
| 1067 | * this recommendation is not applicable for CSE-Lite SKUs where BIOS should set |
| 1068 | * CF9LOCK bit irrespectively. |
| 1069 | * |
| 1070 | * Other than that, make sure payload/OS can't trigger global reset. |
| 1071 | * |
| 1072 | * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) |
| 1073 | * prior to transferring control to the OS. |
| 1074 | */ |
| 1075 | if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || cse_is_hfs1_spi_protected()) |
| 1076 | pmc_global_reset_disable_and_lock(); |
| 1077 | else |
| 1078 | pmc_global_reset_enable(false); |
| 1079 | } |
| 1080 | |
Michał Żygowski | daa1710 | 2022-10-04 10:55:38 +0200 | [diff] [blame^] | 1081 | enum cb_err cse_get_fw_feature_state(uint32_t *feature_state) |
| 1082 | { |
| 1083 | struct fw_feature_state_msg { |
| 1084 | struct mkhi_hdr hdr; |
| 1085 | uint32_t rule_id; |
| 1086 | } __packed; |
| 1087 | |
| 1088 | /* Get Firmware Feature State message */ |
| 1089 | struct fw_feature_state_msg msg = { |
| 1090 | .hdr = { |
| 1091 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 1092 | .command = MKHI_FWCAPS_GET_FW_FEATURE_STATE, |
| 1093 | }, |
| 1094 | .rule_id = ME_FEATURE_STATE_RULE_ID |
| 1095 | }; |
| 1096 | |
| 1097 | /* Get Firmware Feature State response */ |
| 1098 | struct fw_feature_state_resp { |
| 1099 | struct mkhi_hdr hdr; |
| 1100 | uint32_t rule_id; |
| 1101 | uint8_t rule_len; |
| 1102 | uint32_t fw_runtime_status; |
| 1103 | } __packed; |
| 1104 | |
| 1105 | struct fw_feature_state_resp resp; |
| 1106 | size_t resp_size = sizeof(struct fw_feature_state_resp); |
| 1107 | |
| 1108 | /* Ignore if CSE is disabled or input buffer is invalid */ |
| 1109 | if (!is_cse_enabled() || !feature_state) |
| 1110 | return CB_ERR; |
| 1111 | |
| 1112 | /* |
| 1113 | * Prerequisites: |
| 1114 | * 1) HFSTS1 Current Working State is Normal |
| 1115 | * 2) HFSTS1 Current Operation Mode is Normal |
| 1116 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 1117 | * during ramstage) |
| 1118 | */ |
| 1119 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || !ENV_RAMSTAGE) |
| 1120 | return CB_ERR; |
| 1121 | |
| 1122 | printk(BIOS_DEBUG, "HECI: Send GET FW FEATURE STATE Command\n"); |
| 1123 | |
| 1124 | if (heci_send_receive(&msg, sizeof(struct fw_feature_state_msg), |
| 1125 | &resp, &resp_size, HECI_MKHI_ADDR)) |
| 1126 | return CB_ERR; |
| 1127 | |
| 1128 | if (resp.hdr.result) { |
| 1129 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
| 1130 | return CB_ERR; |
| 1131 | } |
| 1132 | |
| 1133 | if (resp.rule_len != sizeof(resp.fw_runtime_status)) { |
| 1134 | printk(BIOS_ERR, "HECI: GET FW FEATURE STATE has invalid rule data length\n"); |
| 1135 | return CB_ERR; |
| 1136 | } |
| 1137 | |
| 1138 | *feature_state = resp.fw_runtime_status; |
| 1139 | |
| 1140 | return CB_SUCCESS; |
| 1141 | } |
| 1142 | |
| 1143 | void cse_enable_ptt(bool state) |
| 1144 | { |
| 1145 | struct fw_feature_shipment_override_msg { |
| 1146 | struct mkhi_hdr hdr; |
| 1147 | uint32_t enable_mask; |
| 1148 | uint32_t disable_mask; |
| 1149 | } __packed; |
| 1150 | |
| 1151 | /* FW Feature Shipment Time State Override message */ |
| 1152 | struct fw_feature_shipment_override_msg msg = { |
| 1153 | .hdr = { |
| 1154 | .group_id = MKHI_GROUP_ID_GEN, |
| 1155 | .command = MKHI_GEN_FW_FEATURE_SHIPMENT_OVER, |
| 1156 | }, |
| 1157 | .enable_mask = 0, |
| 1158 | .disable_mask = 0 |
| 1159 | }; |
| 1160 | |
| 1161 | /* FW Feature Shipment Time State Override response */ |
| 1162 | struct fw_feature_shipment_override_resp { |
| 1163 | struct mkhi_hdr hdr; |
| 1164 | uint32_t data; |
| 1165 | } __packed; |
| 1166 | |
| 1167 | struct fw_feature_shipment_override_resp resp; |
| 1168 | size_t resp_size = sizeof(struct fw_feature_shipment_override_resp); |
| 1169 | uint32_t feature_status; |
| 1170 | |
| 1171 | /* Ignore if CSE is disabled */ |
| 1172 | if (!is_cse_enabled()) |
| 1173 | return; |
| 1174 | |
| 1175 | printk(BIOS_DEBUG, "Requested to change PTT state to %sabled\n", state ? "en" : "dis"); |
| 1176 | |
| 1177 | /* |
| 1178 | * Prerequisites: |
| 1179 | * 1) HFSTS1 Current Working State is Normal |
| 1180 | * 2) HFSTS1 Current Operation Mode is Normal |
| 1181 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 1182 | * during ramstage |
| 1183 | * 4) HFSTS1 FW Init Complete is set |
| 1184 | * 5) Before EOP issued to CSE |
| 1185 | */ |
| 1186 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || |
| 1187 | !cse_is_hfs1_fw_init_complete() || !ENV_RAMSTAGE) { |
| 1188 | printk(BIOS_ERR, "HECI: Unmet prerequisites for" |
| 1189 | "FW FEATURE SHIPMENT TIME STATE OVERRIDE\n"); |
| 1190 | return; |
| 1191 | } |
| 1192 | |
| 1193 | if (cse_get_fw_feature_state(&feature_status) != CB_SUCCESS) { |
| 1194 | printk(BIOS_ERR, "HECI: Cannot determine current feature status\n"); |
| 1195 | return; |
| 1196 | } |
| 1197 | |
| 1198 | if (!!(feature_status & ME_FW_FEATURE_PTT) == state) { |
| 1199 | printk(BIOS_DEBUG, "HECI: PTT is already in the requested state\n"); |
| 1200 | return; |
| 1201 | } |
| 1202 | |
| 1203 | printk(BIOS_DEBUG, "HECI: Send FW FEATURE SHIPMENT TIME STATE OVERRIDE Command\n"); |
| 1204 | |
| 1205 | if (state) |
| 1206 | msg.enable_mask |= ME_FW_FEATURE_PTT; |
| 1207 | else |
| 1208 | msg.disable_mask |= ME_FW_FEATURE_PTT; |
| 1209 | |
| 1210 | if (heci_send_receive(&msg, sizeof(struct fw_feature_shipment_override_msg), |
| 1211 | &resp, &resp_size, HECI_MKHI_ADDR)) |
| 1212 | return; |
| 1213 | |
| 1214 | if (resp.hdr.result) { |
| 1215 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
| 1216 | return; |
| 1217 | } |
| 1218 | |
| 1219 | /* Global reset is required after acceptance of the command */ |
| 1220 | if (resp.data == 0) { |
| 1221 | printk(BIOS_DEBUG, "HECI: FW FEATURE SHIPMENT TIME STATE OVERRIDE success\n"); |
| 1222 | do_global_reset(); |
| 1223 | } else { |
| 1224 | printk(BIOS_ERR, "HECI: FW FEATURE SHIPMENT TIME STATE OVERRIDE error (%x)\n", |
| 1225 | resp.data); |
| 1226 | } |
| 1227 | } |
| 1228 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1229 | #if ENV_RAMSTAGE |
| 1230 | |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1231 | /* |
| 1232 | * Disable the Intel (CS)Management Engine via HECI based on a cmos value |
| 1233 | * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working) |
| 1234 | * and value of `1` will result in a (CS)ME state of `3` (disabled). |
| 1235 | * |
| 1236 | * It isn't advised to use this in combination with me_cleaner. |
| 1237 | * |
| 1238 | * It is advisable to have a second cmos option called `me_state_counter`. |
| 1239 | * Whilst not essential, it avoid reboots loops if the (CS)ME fails to |
| 1240 | * change states after 3 attempts. Some versions of the (CS)ME need to be |
| 1241 | * reset 3 times. |
| 1242 | * |
| 1243 | * Ideal cmos values would be: |
| 1244 | * |
| 1245 | * # coreboot config options: cpu |
| 1246 | * 432 1 e 5 me_state |
| 1247 | * 440 4 h 0 me_state_counter |
| 1248 | * |
| 1249 | * #ID value text |
| 1250 | * 5 0 Enable |
| 1251 | * 5 1 Disable |
| 1252 | */ |
| 1253 | |
| 1254 | static void me_reset_with_count(void) |
| 1255 | { |
| 1256 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", UINT_MAX); |
| 1257 | |
| 1258 | if (cmos_me_state_counter != UINT_MAX) { |
| 1259 | printk(BIOS_DEBUG, "CMOS: me_state_counter = %u\n", cmos_me_state_counter); |
| 1260 | /* Avoid boot loops by only trying a state change 3 times */ |
| 1261 | if (cmos_me_state_counter < ME_DISABLE_ATTEMPTS) { |
| 1262 | cmos_me_state_counter++; |
| 1263 | set_uint_option("me_state_counter", cmos_me_state_counter); |
| 1264 | printk(BIOS_DEBUG, "ME: Reset attempt %u/%u.\n", cmos_me_state_counter, |
| 1265 | ME_DISABLE_ATTEMPTS); |
| 1266 | do_global_reset(); |
| 1267 | } else { |
| 1268 | /* |
| 1269 | * If the (CS)ME fails to change states after 3 attempts, it will |
| 1270 | * likely need a cold boot, or recovering. |
| 1271 | */ |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 1272 | printk(BIOS_ERR, "Failed to change ME state in %u attempts!\n", |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1273 | ME_DISABLE_ATTEMPTS); |
| 1274 | |
| 1275 | } |
| 1276 | } else { |
| 1277 | printk(BIOS_DEBUG, "ME: Resetting"); |
| 1278 | do_global_reset(); |
| 1279 | } |
| 1280 | } |
| 1281 | |
| 1282 | static void cse_set_state(struct device *dev) |
| 1283 | { |
| 1284 | |
| 1285 | /* (CS)ME Disable Command */ |
| 1286 | struct me_disable_command { |
| 1287 | struct mkhi_hdr hdr; |
| 1288 | uint32_t rule_id; |
| 1289 | uint8_t rule_len; |
| 1290 | uint32_t rule_data; |
| 1291 | } __packed me_disable = { |
| 1292 | .hdr = { |
| 1293 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 1294 | .command = MKHI_SET_ME_DISABLE, |
| 1295 | }, |
| 1296 | .rule_id = ME_DISABLE_RULE_ID, |
| 1297 | .rule_len = ME_DISABLE_RULE_LENGTH, |
| 1298 | .rule_data = ME_DISABLE_COMMAND, |
| 1299 | }; |
| 1300 | |
| 1301 | struct me_disable_reply { |
| 1302 | struct mkhi_hdr hdr; |
| 1303 | uint32_t rule_id; |
| 1304 | } __packed; |
| 1305 | |
| 1306 | struct me_disable_reply disable_reply; |
| 1307 | |
| 1308 | size_t disable_reply_size; |
| 1309 | |
| 1310 | /* (CS)ME Enable Command */ |
| 1311 | struct me_enable_command { |
| 1312 | struct mkhi_hdr hdr; |
| 1313 | } me_enable = { |
| 1314 | .hdr = { |
| 1315 | .group_id = MKHI_GROUP_ID_BUP_COMMON, |
| 1316 | .command = MKHI_SET_ME_ENABLE, |
| 1317 | }, |
| 1318 | }; |
| 1319 | |
| 1320 | struct me_enable_reply { |
| 1321 | struct mkhi_hdr hdr; |
| 1322 | } __packed; |
| 1323 | |
| 1324 | struct me_enable_reply enable_reply; |
| 1325 | |
| 1326 | size_t enable_reply_size; |
| 1327 | |
| 1328 | /* Function Start */ |
| 1329 | |
| 1330 | int send; |
| 1331 | int result; |
| 1332 | /* |
| 1333 | * Check if the CMOS value "me_state" exists, if it doesn't, then |
| 1334 | * don't do anything. |
| 1335 | */ |
| 1336 | const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); |
| 1337 | |
| 1338 | if (cmos_me_state == UINT_MAX) |
| 1339 | return; |
| 1340 | |
| 1341 | printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); |
| 1342 | |
| 1343 | /* |
| 1344 | * We only take action if the me_state doesn't match the CS(ME) working state |
| 1345 | */ |
| 1346 | |
| 1347 | const unsigned int soft_temp_disable = cse_is_hfs1_com_soft_temp_disable(); |
| 1348 | |
| 1349 | if (cmos_me_state && !soft_temp_disable) { |
| 1350 | /* me_state should be disabled, but it's enabled */ |
| 1351 | printk(BIOS_DEBUG, "ME needs to be disabled.\n"); |
| 1352 | send = heci_send_receive(&me_disable, sizeof(me_disable), |
| 1353 | &disable_reply, &disable_reply_size, HECI_MKHI_ADDR); |
| 1354 | result = disable_reply.hdr.result; |
| 1355 | } else if (!cmos_me_state && soft_temp_disable) { |
| 1356 | /* me_state should be enabled, but it's disabled */ |
| 1357 | printk(BIOS_DEBUG, "ME needs to be enabled.\n"); |
| 1358 | send = heci_send_receive(&me_enable, sizeof(me_enable), |
| 1359 | &enable_reply, &enable_reply_size, HECI_MKHI_ADDR); |
| 1360 | result = enable_reply.hdr.result; |
| 1361 | } else { |
| 1362 | printk(BIOS_DEBUG, "ME is %s.\n", cmos_me_state ? "disabled" : "enabled"); |
| 1363 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", |
| 1364 | UINT_MAX); |
| 1365 | /* set me_state_counter to 0 */ |
| 1366 | if ((cmos_me_state_counter != UINT_MAX && cmos_me_state_counter != 0)) |
| 1367 | set_uint_option("me_state_counter", 0); |
| 1368 | return; |
| 1369 | } |
| 1370 | |
| 1371 | printk(BIOS_DEBUG, "HECI: ME state change send %s!\n", |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 1372 | !send ? "success" : "failure"); |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1373 | printk(BIOS_DEBUG, "HECI: ME state change result %s!\n", |
| 1374 | result ? "success" : "failure"); |
| 1375 | |
| 1376 | /* |
| 1377 | * Reset if the result was successful, or if the send failed as some older |
| 1378 | * version of the Intel (CS)ME won't successfully receive the message unless reset |
| 1379 | * twice. |
| 1380 | */ |
| 1381 | if (send || !result) |
| 1382 | me_reset_with_count(); |
| 1383 | } |
| 1384 | |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1385 | /* |
| 1386 | * `cse_final_ready_to_boot` function is native implementation of equivalent events |
| 1387 | * performed by FSP NotifyPhase(Ready To Boot) API invocations. |
| 1388 | * |
| 1389 | * Operations are: |
Subrata Banik | 5214c40 | 2022-11-24 20:43:37 +0530 | [diff] [blame] | 1390 | * 1. Perform global reset lock. |
| 1391 | * 2. Put HECI1 to D0i3 and disable the HECI1 if the user selects |
Subrata Banik | 670572f | 2022-04-25 15:39:55 +0530 | [diff] [blame] | 1392 | * DISABLE_HECI1_AT_PRE_BOOT config or CSE HFSTS1 Operation Mode is |
| 1393 | * `Software Temporary Disable`. |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1394 | */ |
| 1395 | static void cse_final_ready_to_boot(void) |
| 1396 | { |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1397 | cse_control_global_reset_lock(); |
| 1398 | |
Subrata Banik | 670572f | 2022-04-25 15:39:55 +0530 | [diff] [blame] | 1399 | if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1400 | cse_set_to_d0i3(); |
| 1401 | heci1_disable(); |
| 1402 | } |
| 1403 | } |
| 1404 | |
| 1405 | /* |
| 1406 | * `cse_final_end_of_firmware` function is native implementation of equivalent events |
| 1407 | * performed by FSP NotifyPhase(End of Firmware) API invocations. |
| 1408 | * |
| 1409 | * Operations are: |
| 1410 | * 1. Set D0I3 for all HECI devices. |
| 1411 | */ |
| 1412 | static void cse_final_end_of_firmware(void) |
| 1413 | { |
| 1414 | heci_set_to_d0i3(); |
| 1415 | } |
| 1416 | |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1417 | /* |
Subrata Banik | 17a3da8 | 2022-11-24 21:51:42 +0530 | [diff] [blame] | 1418 | * This function to perform essential post EOP cse related operations |
| 1419 | * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config |
| 1420 | */ |
| 1421 | void cse_late_finalize(void) |
| 1422 | { |
| 1423 | if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) |
| 1424 | return; |
| 1425 | |
| 1426 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) |
| 1427 | cse_final_ready_to_boot(); |
| 1428 | |
| 1429 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) |
| 1430 | cse_final_end_of_firmware(); |
| 1431 | } |
| 1432 | |
| 1433 | /* |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1434 | * `cse_final` function is native implementation of equivalent events performed by |
| 1435 | * each FSP NotifyPhase() API invocations. |
| 1436 | */ |
| 1437 | static void cse_final(struct device *dev) |
| 1438 | { |
Subrata Banik | 5214c40 | 2022-11-24 20:43:37 +0530 | [diff] [blame] | 1439 | /* SoC user decided to send EOP late */ |
| 1440 | if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) |
| 1441 | return; |
| 1442 | |
| 1443 | /* 1. Send EOP to CSE if not done.*/ |
| 1444 | if (CONFIG(SOC_INTEL_CSE_SET_EOP)) |
| 1445 | cse_send_end_of_post(); |
| 1446 | |
Angel Pons | 28315f8 | 2022-04-19 10:03:56 +0200 | [diff] [blame] | 1447 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) |
| 1448 | cse_final_ready_to_boot(); |
| 1449 | |
| 1450 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) |
| 1451 | cse_final_end_of_firmware(); |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1452 | } |
| 1453 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 1454 | struct device_operations cse_ops = { |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 1455 | .set_resources = pci_dev_set_resources, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1456 | .read_resources = pci_dev_read_resources, |
| 1457 | .enable_resources = pci_dev_enable_resources, |
| 1458 | .init = pci_dev_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 1459 | .ops_pci = &pci_dev_ops_pci, |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1460 | .enable = cse_set_state, |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1461 | .final = cse_final, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1462 | }; |
| 1463 | |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1464 | static const unsigned short pci_device_ids[] = { |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 1465 | PCI_DID_INTEL_MTL_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1466 | PCI_DID_INTEL_APL_CSE0, |
| 1467 | PCI_DID_INTEL_GLK_CSE0, |
| 1468 | PCI_DID_INTEL_CNL_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1469 | PCI_DID_INTEL_LWB_CSE0, |
| 1470 | PCI_DID_INTEL_LWB_CSE0_SUPER, |
| 1471 | PCI_DID_INTEL_CNP_H_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1472 | PCI_DID_INTEL_CMP_CSE0, |
| 1473 | PCI_DID_INTEL_CMP_H_CSE0, |
| 1474 | PCI_DID_INTEL_TGL_CSE0, |
| 1475 | PCI_DID_INTEL_TGL_H_CSE0, |
| 1476 | PCI_DID_INTEL_MCC_CSE0, |
| 1477 | PCI_DID_INTEL_MCC_CSE1, |
| 1478 | PCI_DID_INTEL_MCC_CSE2, |
| 1479 | PCI_DID_INTEL_MCC_CSE3, |
| 1480 | PCI_DID_INTEL_JSP_CSE0, |
| 1481 | PCI_DID_INTEL_JSP_CSE1, |
| 1482 | PCI_DID_INTEL_JSP_CSE2, |
| 1483 | PCI_DID_INTEL_JSP_CSE3, |
| 1484 | PCI_DID_INTEL_ADP_P_CSE0, |
| 1485 | PCI_DID_INTEL_ADP_P_CSE1, |
| 1486 | PCI_DID_INTEL_ADP_P_CSE2, |
| 1487 | PCI_DID_INTEL_ADP_P_CSE3, |
| 1488 | PCI_DID_INTEL_ADP_S_CSE0, |
| 1489 | PCI_DID_INTEL_ADP_S_CSE1, |
| 1490 | PCI_DID_INTEL_ADP_S_CSE2, |
| 1491 | PCI_DID_INTEL_ADP_S_CSE3, |
| 1492 | PCI_DID_INTEL_ADP_M_CSE0, |
| 1493 | PCI_DID_INTEL_ADP_M_CSE1, |
| 1494 | PCI_DID_INTEL_ADP_M_CSE2, |
| 1495 | PCI_DID_INTEL_ADP_M_CSE3, |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1496 | 0, |
| 1497 | }; |
| 1498 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1499 | static const struct pci_driver cse_driver __pci_driver = { |
| 1500 | .ops = &cse_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1501 | .vendor = PCI_VID_INTEL, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1502 | /* SoC/chipset needs to provide PCI device ID */ |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 1503 | .devices = pci_device_ids |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1504 | }; |
| 1505 | |
| 1506 | #endif |