Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 2 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 5 | #include <assert.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
| 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
| 12 | #include <device/pci_ops.h> |
| 13 | #include <intelblocks/cse.h> |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 14 | #include <security/vboot/misc.h> |
| 15 | #include <security/vboot/vboot_common.h> |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 16 | #include <soc/iomap.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 17 | #include <soc/pci_devs.h> |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 18 | #include <soc/me.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 19 | #include <string.h> |
| 20 | #include <timer.h> |
| 21 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 22 | #define MAX_HECI_MESSAGE_RETRY_COUNT 5 |
| 23 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 24 | /* Wait up to 15 sec for HECI to get ready */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 25 | #define HECI_DELAY_READY_MS (15 * 1000) |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 26 | /* Wait up to 100 usec between circular buffer polls */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 27 | #define HECI_DELAY_US 100 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 28 | /* Wait up to 5 sec for CSE to chew something we sent */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 29 | #define HECI_SEND_TIMEOUT_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 30 | /* Wait up to 5 sec for CSE to blurp a reply */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 31 | #define HECI_READ_TIMEOUT_MS (5 * 1000) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 32 | /* Wait up to 1 ms for CSE CIP */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 33 | #define HECI_CIP_TIMEOUT_US 1000 |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 34 | /* Wait up to 5 seconds for CSE to boot from RO(BP1) */ |
| 35 | #define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 36 | |
| 37 | #define SLOT_SIZE sizeof(uint32_t) |
| 38 | |
| 39 | #define MMIO_CSE_CB_WW 0x00 |
| 40 | #define MMIO_HOST_CSR 0x04 |
| 41 | #define MMIO_CSE_CB_RW 0x08 |
| 42 | #define MMIO_CSE_CSR 0x0c |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 43 | #define MMIO_CSE_DEVIDLE 0x800 |
| 44 | #define CSE_DEV_IDLE (1 << 2) |
| 45 | #define CSE_DEV_CIP (1 << 0) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 46 | |
| 47 | #define CSR_IE (1 << 0) |
| 48 | #define CSR_IS (1 << 1) |
| 49 | #define CSR_IG (1 << 2) |
| 50 | #define CSR_READY (1 << 3) |
| 51 | #define CSR_RESET (1 << 4) |
| 52 | #define CSR_RP_START 8 |
| 53 | #define CSR_RP (((1 << 8) - 1) << CSR_RP_START) |
| 54 | #define CSR_WP_START 16 |
| 55 | #define CSR_WP (((1 << 8) - 1) << CSR_WP_START) |
| 56 | #define CSR_CBD_START 24 |
| 57 | #define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) |
| 58 | |
| 59 | #define MEI_HDR_IS_COMPLETE (1 << 31) |
| 60 | #define MEI_HDR_LENGTH_START 16 |
| 61 | #define MEI_HDR_LENGTH_SIZE 9 |
| 62 | #define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ |
| 63 | << MEI_HDR_LENGTH_START) |
| 64 | #define MEI_HDR_HOST_ADDR_START 8 |
| 65 | #define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) |
| 66 | #define MEI_HDR_CSE_ADDR_START 0 |
| 67 | #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) |
| 68 | |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 69 | /* Get HECI BAR 0 from PCI configuration space */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 70 | static uintptr_t get_cse_bar(pci_devfn_t dev) |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 71 | { |
| 72 | uintptr_t bar; |
| 73 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 74 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 75 | assert(bar != 0); |
| 76 | /* |
| 77 | * Bits 31-12 are the base address as per EDS for SPI, |
| 78 | * Don't care about 0-11 bit |
| 79 | */ |
| 80 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 81 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * Initialize the device with provided temporary BAR. If BAR is 0 use a |
| 85 | * default. This is intended for pre-mem usage only where BARs haven't been |
| 86 | * assigned yet and devices are not enabled. |
| 87 | */ |
| 88 | void heci_init(uintptr_t tempbar) |
| 89 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 90 | pci_devfn_t dev = PCH_DEV_CSE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 91 | |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 92 | u16 pcireg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 93 | |
| 94 | /* Assume it is already initialized, nothing else to do */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 95 | if (get_cse_bar(dev)) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 96 | return; |
| 97 | |
| 98 | /* Use default pre-ram bar */ |
| 99 | if (!tempbar) |
| 100 | tempbar = HECI1_BASE_ADDRESS; |
| 101 | |
| 102 | /* Assign Resources to HECI1 */ |
| 103 | /* Clear BIT 1-2 of Command Register */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 104 | pcireg = pci_read_config16(dev, PCI_COMMAND); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 105 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 106 | pci_write_config16(dev, PCI_COMMAND, pcireg); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 107 | |
| 108 | /* Program Temporary BAR for HECI1 */ |
| 109 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); |
| 110 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); |
| 111 | |
| 112 | /* Enable Bus Master and MMIO Space */ |
Elyes HAOUAS | 2ec1c13 | 2020-04-29 09:57:05 +0200 | [diff] [blame] | 113 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 114 | } |
| 115 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 116 | static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 117 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 118 | return read32p(get_cse_bar(dev) + offset); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 119 | } |
| 120 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 121 | static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 122 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 123 | return write32p(get_cse_bar(dev) + offset, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static uint32_t read_cse_csr(void) |
| 127 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 128 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 129 | } |
| 130 | |
| 131 | static uint32_t read_host_csr(void) |
| 132 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 133 | return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 134 | } |
| 135 | |
| 136 | static void write_host_csr(uint32_t data) |
| 137 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 138 | write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static size_t filled_slots(uint32_t data) |
| 142 | { |
| 143 | uint8_t wp, rp; |
| 144 | rp = data >> CSR_RP_START; |
| 145 | wp = data >> CSR_WP_START; |
| 146 | return (uint8_t) (wp - rp); |
| 147 | } |
| 148 | |
| 149 | static size_t cse_filled_slots(void) |
| 150 | { |
| 151 | return filled_slots(read_cse_csr()); |
| 152 | } |
| 153 | |
| 154 | static size_t host_empty_slots(void) |
| 155 | { |
| 156 | uint32_t csr; |
| 157 | csr = read_host_csr(); |
| 158 | |
| 159 | return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr); |
| 160 | } |
| 161 | |
| 162 | static void clear_int(void) |
| 163 | { |
| 164 | uint32_t csr; |
| 165 | csr = read_host_csr(); |
| 166 | csr |= CSR_IS; |
| 167 | write_host_csr(csr); |
| 168 | } |
| 169 | |
| 170 | static uint32_t read_slot(void) |
| 171 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 172 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static void write_slot(uint32_t val) |
| 176 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 177 | write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 178 | } |
| 179 | |
| 180 | static int wait_write_slots(size_t cnt) |
| 181 | { |
| 182 | struct stopwatch sw; |
| 183 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 184 | stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 185 | while (host_empty_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 186 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 187 | if (stopwatch_expired(&sw)) { |
| 188 | printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); |
| 189 | return 0; |
| 190 | } |
| 191 | } |
| 192 | return 1; |
| 193 | } |
| 194 | |
| 195 | static int wait_read_slots(size_t cnt) |
| 196 | { |
| 197 | struct stopwatch sw; |
| 198 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 199 | stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 200 | while (cse_filled_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 201 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 202 | if (stopwatch_expired(&sw)) { |
| 203 | printk(BIOS_ERR, "HECI: timed out reading answer!\n"); |
| 204 | return 0; |
| 205 | } |
| 206 | } |
| 207 | return 1; |
| 208 | } |
| 209 | |
| 210 | /* get number of full 4-byte slots */ |
| 211 | static size_t bytes_to_slots(size_t bytes) |
| 212 | { |
| 213 | return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; |
| 214 | } |
| 215 | |
| 216 | static int cse_ready(void) |
| 217 | { |
| 218 | uint32_t csr; |
| 219 | csr = read_cse_csr(); |
| 220 | return csr & CSR_READY; |
| 221 | } |
| 222 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 223 | static bool cse_check_hfs1_com(int mode) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 224 | { |
| 225 | union me_hfsts1 hfs1; |
| 226 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 227 | return hfs1.fields.operation_mode == mode; |
| 228 | } |
| 229 | |
| 230 | bool cse_is_hfs1_cws_normal(void) |
| 231 | { |
| 232 | union me_hfsts1 hfs1; |
| 233 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 234 | if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL) |
| 235 | return true; |
| 236 | return false; |
| 237 | } |
| 238 | |
| 239 | bool cse_is_hfs1_com_normal(void) |
| 240 | { |
| 241 | return cse_check_hfs1_com(ME_HFS1_COM_NORMAL); |
| 242 | } |
| 243 | |
| 244 | bool cse_is_hfs1_com_secover_mei_msg(void) |
| 245 | { |
| 246 | return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); |
| 247 | } |
| 248 | |
| 249 | bool cse_is_hfs1_com_soft_temp_disable(void) |
| 250 | { |
| 251 | return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 252 | } |
| 253 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 254 | bool cse_is_hfs3_fw_sku_lite(void) |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 255 | { |
| 256 | union me_hfsts3 hfs3; |
| 257 | hfs3.data = me_read_config32(PCI_ME_HFSTS3); |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 258 | return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE; |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 259 | } |
| 260 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 261 | /* Makes the host ready to communicate with CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 262 | void cse_set_host_ready(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 263 | { |
| 264 | uint32_t csr; |
| 265 | csr = read_host_csr(); |
| 266 | csr &= ~CSR_RESET; |
| 267 | csr |= (CSR_IG | CSR_READY); |
| 268 | write_host_csr(csr); |
| 269 | } |
| 270 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 271 | /* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */ |
| 272 | uint8_t cse_wait_sec_override_mode(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 273 | { |
| 274 | struct stopwatch sw; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 275 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 276 | while (!cse_is_hfs1_com_secover_mei_msg()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 277 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 278 | if (stopwatch_expired(&sw)) { |
| 279 | printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n"); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 280 | return 0; |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 281 | } |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 282 | } |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 283 | printk(BIOS_DEBUG, "HECI: CSE took %lu ms to enter security override mode\n", |
| 284 | stopwatch_duration_msecs(&sw)); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 285 | return 1; |
| 286 | } |
| 287 | |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 288 | /* |
| 289 | * Polls for CSE's current operation mode 'Soft Temporary Disable'. |
| 290 | * The CSE enters the current operation mode when it boots from RO(BP1). |
| 291 | */ |
| 292 | uint8_t cse_wait_com_soft_temp_disable(void) |
| 293 | { |
| 294 | struct stopwatch sw; |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 295 | stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 296 | while (!cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 297 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 298 | if (stopwatch_expired(&sw)) { |
| 299 | printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); |
| 300 | return 0; |
| 301 | } |
| 302 | } |
| 303 | printk(BIOS_SPEW, "HECI: CSE took %lu ms to boot from RO\n", |
| 304 | stopwatch_duration_msecs(&sw)); |
| 305 | return 1; |
| 306 | } |
| 307 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 308 | static int wait_heci_ready(void) |
| 309 | { |
| 310 | struct stopwatch sw; |
| 311 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 312 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 313 | while (!cse_ready()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 314 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 315 | if (stopwatch_expired(&sw)) |
| 316 | return 0; |
| 317 | } |
| 318 | |
| 319 | return 1; |
| 320 | } |
| 321 | |
| 322 | static void host_gen_interrupt(void) |
| 323 | { |
| 324 | uint32_t csr; |
| 325 | csr = read_host_csr(); |
| 326 | csr |= CSR_IG; |
| 327 | write_host_csr(csr); |
| 328 | } |
| 329 | |
| 330 | static size_t hdr_get_length(uint32_t hdr) |
| 331 | { |
| 332 | return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START; |
| 333 | } |
| 334 | |
| 335 | static int |
| 336 | send_one_message(uint32_t hdr, const void *buff) |
| 337 | { |
| 338 | size_t pend_len, pend_slots, remainder, i; |
| 339 | uint32_t tmp; |
| 340 | const uint32_t *p = buff; |
| 341 | |
| 342 | /* Get space for the header */ |
| 343 | if (!wait_write_slots(1)) |
| 344 | return 0; |
| 345 | |
| 346 | /* First, write header */ |
| 347 | write_slot(hdr); |
| 348 | |
| 349 | pend_len = hdr_get_length(hdr); |
| 350 | pend_slots = bytes_to_slots(pend_len); |
| 351 | |
| 352 | if (!wait_write_slots(pend_slots)) |
| 353 | return 0; |
| 354 | |
| 355 | /* Write the body in whole slots */ |
| 356 | i = 0; |
| 357 | while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { |
| 358 | write_slot(*p++); |
| 359 | i += SLOT_SIZE; |
| 360 | } |
| 361 | |
| 362 | remainder = pend_len % SLOT_SIZE; |
| 363 | /* Pad to 4 bytes not touching caller's buffer */ |
| 364 | if (remainder) { |
| 365 | memcpy(&tmp, p, remainder); |
| 366 | write_slot(tmp); |
| 367 | } |
| 368 | |
| 369 | host_gen_interrupt(); |
| 370 | |
| 371 | /* Make sure nothing bad happened during transmission */ |
| 372 | if (!cse_ready()) |
| 373 | return 0; |
| 374 | |
| 375 | return pend_len; |
| 376 | } |
| 377 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 378 | /* |
| 379 | * Send message msg of size len to host from host_addr to cse_addr. |
| 380 | * Returns 1 on success and 0 otherwise. |
| 381 | * In case of error heci_reset() may be required. |
| 382 | */ |
| 383 | static int |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 384 | heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) |
| 385 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 386 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 387 | uint32_t csr, hdr; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 388 | size_t sent, remaining, cb_size, max_length; |
| 389 | const uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 390 | |
| 391 | if (!msg || !len) |
| 392 | return 0; |
| 393 | |
| 394 | clear_int(); |
| 395 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 396 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 397 | p = msg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 398 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 399 | if (!wait_heci_ready()) { |
| 400 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 401 | continue; |
| 402 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 403 | |
Subrata Banik | 4a722f5 | 2017-11-13 14:56:42 +0530 | [diff] [blame] | 404 | csr = read_host_csr(); |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 405 | cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE; |
| 406 | /* |
| 407 | * Reserve one slot for the header. Limit max message |
| 408 | * length by 9 bits that are available in the header. |
| 409 | */ |
| 410 | max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) |
| 411 | - SLOT_SIZE; |
| 412 | remaining = len; |
| 413 | |
| 414 | /* |
| 415 | * Fragment the message into smaller messages not exceeding |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 416 | * useful circular buffer length. Mark last message complete. |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 417 | */ |
| 418 | do { |
| 419 | hdr = MIN(max_length, remaining) |
| 420 | << MEI_HDR_LENGTH_START; |
| 421 | hdr |= client_addr << MEI_HDR_CSE_ADDR_START; |
| 422 | hdr |= host_addr << MEI_HDR_HOST_ADDR_START; |
| 423 | hdr |= (MIN(max_length, remaining) == remaining) ? |
Lee Leahy | 68ab0b5 | 2017-03-10 13:42:34 -0800 | [diff] [blame] | 424 | MEI_HDR_IS_COMPLETE : 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 425 | sent = send_one_message(hdr, p); |
| 426 | p += sent; |
| 427 | remaining -= sent; |
| 428 | } while (remaining > 0 && sent != 0); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 429 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 430 | if (!remaining) |
| 431 | return 1; |
| 432 | } |
| 433 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 434 | } |
| 435 | |
| 436 | static size_t |
| 437 | recv_one_message(uint32_t *hdr, void *buff, size_t maxlen) |
| 438 | { |
| 439 | uint32_t reg, *p = buff; |
| 440 | size_t recv_slots, recv_len, remainder, i; |
| 441 | |
| 442 | /* first get the header */ |
| 443 | if (!wait_read_slots(1)) |
| 444 | return 0; |
| 445 | |
| 446 | *hdr = read_slot(); |
| 447 | recv_len = hdr_get_length(*hdr); |
| 448 | |
| 449 | if (!recv_len) |
| 450 | printk(BIOS_WARNING, "HECI: message is zero-sized\n"); |
| 451 | |
| 452 | recv_slots = bytes_to_slots(recv_len); |
| 453 | |
| 454 | i = 0; |
| 455 | if (recv_len > maxlen) { |
| 456 | printk(BIOS_ERR, "HECI: response is too big\n"); |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | /* wait for the rest of messages to arrive */ |
| 461 | wait_read_slots(recv_slots); |
| 462 | |
| 463 | /* fetch whole slots first */ |
| 464 | while (i < ALIGN_DOWN(recv_len, SLOT_SIZE)) { |
| 465 | *p++ = read_slot(); |
| 466 | i += SLOT_SIZE; |
| 467 | } |
| 468 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 469 | /* |
| 470 | * If ME is not ready, something went wrong and |
| 471 | * we received junk |
| 472 | */ |
| 473 | if (!cse_ready()) |
| 474 | return 0; |
| 475 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 476 | remainder = recv_len % SLOT_SIZE; |
| 477 | |
| 478 | if (remainder) { |
| 479 | reg = read_slot(); |
| 480 | memcpy(p, ®, remainder); |
| 481 | } |
| 482 | |
| 483 | return recv_len; |
| 484 | } |
| 485 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 486 | /* |
| 487 | * Receive message into buff not exceeding maxlen. Message is considered |
| 488 | * successfully received if a 'complete' indication is read from ME side |
| 489 | * and there was enough space in the buffer to fit that message. maxlen |
| 490 | * is updated with size of message that was received. Returns 0 on failure |
| 491 | * and 1 on success. |
| 492 | * In case of error heci_reset() may be required. |
| 493 | */ |
| 494 | static int heci_receive(void *buff, size_t *maxlen) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 495 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 496 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 497 | size_t left, received; |
| 498 | uint32_t hdr = 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 499 | uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 500 | |
| 501 | if (!buff || !maxlen || !*maxlen) |
| 502 | return 0; |
| 503 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 504 | clear_int(); |
| 505 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 506 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 507 | p = buff; |
| 508 | left = *maxlen; |
| 509 | |
| 510 | if (!wait_heci_ready()) { |
| 511 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 512 | continue; |
| 513 | } |
| 514 | |
| 515 | /* |
| 516 | * Receive multiple packets until we meet one marked |
| 517 | * complete or we run out of space in caller-provided buffer. |
| 518 | */ |
| 519 | do { |
| 520 | received = recv_one_message(&hdr, p, left); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 521 | if (!received) { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 522 | printk(BIOS_ERR, "HECI: Failed to receive!\n"); |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 523 | return 0; |
| 524 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 525 | left -= received; |
| 526 | p += received; |
| 527 | /* If we read out everything ping to send more */ |
| 528 | if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots()) |
| 529 | host_gen_interrupt(); |
| 530 | } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); |
| 531 | |
| 532 | if ((hdr & MEI_HDR_IS_COMPLETE) && received) { |
| 533 | *maxlen = p - (uint8_t *) buff; |
| 534 | return 1; |
| 535 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 536 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 537 | return 0; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 538 | } |
| 539 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 540 | int heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, size_t *rcv_sz, |
| 541 | uint8_t cse_addr) |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 542 | { |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 543 | if (!heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr)) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 544 | printk(BIOS_ERR, "HECI: send Failed\n"); |
| 545 | return 0; |
| 546 | } |
| 547 | |
| 548 | if (rcv_msg != NULL) { |
| 549 | if (!heci_receive(rcv_msg, rcv_sz)) { |
| 550 | printk(BIOS_ERR, "HECI: receive Failed\n"); |
| 551 | return 0; |
| 552 | } |
| 553 | } |
| 554 | return 1; |
| 555 | } |
| 556 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 557 | /* |
| 558 | * Attempt to reset the device. This is useful when host and ME are out |
| 559 | * of sync during transmission or ME didn't understand the message. |
| 560 | */ |
| 561 | int heci_reset(void) |
| 562 | { |
| 563 | uint32_t csr; |
| 564 | |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 565 | /* Clear post code to prevent eventlog entry from unknown code. */ |
| 566 | post_code(0); |
| 567 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 568 | /* Send reset request */ |
| 569 | csr = read_host_csr(); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 570 | csr |= (CSR_RESET | CSR_IG); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 571 | write_host_csr(csr); |
| 572 | |
| 573 | if (wait_heci_ready()) { |
| 574 | /* Device is back on its imaginary feet, clear reset */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 575 | cse_set_host_ready(); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 576 | return 1; |
| 577 | } |
| 578 | |
| 579 | printk(BIOS_CRIT, "HECI: reset failed\n"); |
| 580 | |
| 581 | return 0; |
| 582 | } |
| 583 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 584 | bool is_cse_devfn_visible(unsigned int devfn) |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 585 | { |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 586 | int slot = PCI_SLOT(devfn); |
| 587 | int func = PCI_FUNC(devfn); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 588 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 589 | if (!is_devfn_enabled(devfn)) { |
| 590 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 591 | return false; |
| 592 | } |
| 593 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 594 | if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { |
| 595 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 596 | return false; |
| 597 | } |
| 598 | |
| 599 | return true; |
| 600 | } |
| 601 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 602 | bool is_cse_enabled(void) |
| 603 | { |
| 604 | return is_cse_devfn_visible(PCH_DEVFN_CSE); |
| 605 | } |
| 606 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 607 | uint32_t me_read_config32(int offset) |
| 608 | { |
| 609 | return pci_read_config32(PCH_DEV_CSE, offset); |
| 610 | } |
| 611 | |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 612 | static bool cse_is_global_reset_allowed(void) |
| 613 | { |
| 614 | /* |
| 615 | * Allow sending GLOBAL_RESET command only if: |
| 616 | * - CSE's current working state is Normal and current operation mode is Normal. |
| 617 | * - (or) CSE's current working state is normal and current operation mode can |
| 618 | * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 619 | * Lite. |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 620 | */ |
| 621 | if (!cse_is_hfs1_cws_normal()) |
| 622 | return false; |
| 623 | |
| 624 | if (cse_is_hfs1_com_normal()) |
| 625 | return true; |
| 626 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 627 | if (cse_is_hfs3_fw_sku_lite()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 628 | if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) |
| 629 | return true; |
| 630 | } |
| 631 | return false; |
| 632 | } |
| 633 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 634 | /* |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 635 | * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. |
| 636 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 637 | */ |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 638 | static int cse_request_reset(enum rst_req_type rst_type) |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 639 | { |
| 640 | int status; |
| 641 | struct mkhi_hdr reply; |
| 642 | struct reset_message { |
| 643 | struct mkhi_hdr hdr; |
| 644 | uint8_t req_origin; |
| 645 | uint8_t reset_type; |
| 646 | } __packed; |
| 647 | struct reset_message msg = { |
| 648 | .hdr = { |
| 649 | .group_id = MKHI_GROUP_ID_CBM, |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 650 | .command = MKHI_CBM_GLOBAL_RESET_REQ, |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 651 | }, |
| 652 | .req_origin = GR_ORIGIN_BIOS_POST, |
| 653 | .reset_type = rst_type |
| 654 | }; |
| 655 | size_t reply_size; |
| 656 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 657 | printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 658 | |
Sridhar Siricilla | c2a2d2b | 2020-02-27 17:16:13 +0530 | [diff] [blame] | 659 | if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 660 | printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); |
| 661 | return 0; |
| 662 | } |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 663 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 664 | if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 665 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 666 | return 0; |
| 667 | } |
| 668 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 669 | heci_reset(); |
| 670 | |
| 671 | reply_size = sizeof(reply); |
| 672 | memset(&reply, 0, reply_size); |
| 673 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 674 | if (rst_type == CSE_RESET_ONLY) |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 675 | status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 676 | else |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 677 | status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, |
| 678 | HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 679 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 680 | printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); |
| 681 | return status; |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 682 | } |
| 683 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 684 | int cse_request_global_reset(void) |
| 685 | { |
| 686 | return cse_request_reset(GLOBAL_RESET); |
| 687 | } |
| 688 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 689 | static bool cse_is_hmrfpo_enable_allowed(void) |
| 690 | { |
| 691 | /* |
| 692 | * Allow sending HMRFPO ENABLE command only if: |
| 693 | * - CSE's current working state is Normal and current operation mode is Normal |
| 694 | * - (or) cse's current working state is normal and current operation mode is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 695 | * Soft Temp Disable if CSE's Firmware SKU is Lite |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 696 | */ |
| 697 | if (!cse_is_hfs1_cws_normal()) |
| 698 | return false; |
| 699 | |
| 700 | if (cse_is_hfs1_com_normal()) |
| 701 | return true; |
| 702 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 703 | if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable()) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 704 | return true; |
| 705 | |
| 706 | return false; |
| 707 | } |
| 708 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 709 | /* Sends HMRFPO Enable command to CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 710 | int cse_hmrfpo_enable(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 711 | { |
| 712 | struct hmrfpo_enable_msg { |
| 713 | struct mkhi_hdr hdr; |
| 714 | uint32_t nonce[2]; |
| 715 | } __packed; |
| 716 | |
| 717 | /* HMRFPO Enable message */ |
| 718 | struct hmrfpo_enable_msg msg = { |
| 719 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 720 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 721 | .command = MKHI_HMRFPO_ENABLE, |
| 722 | }, |
| 723 | .nonce = {0}, |
| 724 | }; |
| 725 | |
| 726 | /* HMRFPO Enable response */ |
| 727 | struct hmrfpo_enable_resp { |
| 728 | struct mkhi_hdr hdr; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 729 | /* Base addr for factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 730 | uint32_t fct_base; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 731 | /* Length of factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 732 | uint32_t fct_limit; |
| 733 | uint8_t status; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 734 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 735 | } __packed; |
| 736 | |
| 737 | struct hmrfpo_enable_resp resp; |
| 738 | size_t resp_size = sizeof(struct hmrfpo_enable_resp); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 739 | |
| 740 | printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 741 | |
| 742 | if (!cse_is_hmrfpo_enable_allowed()) { |
| 743 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 744 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 748 | &resp, &resp_size, HECI_MKHI_ADDR)) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 749 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 750 | |
| 751 | if (resp.hdr.result) { |
| 752 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 753 | return 0; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 754 | } |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 755 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 756 | if (resp.status) { |
| 757 | printk(BIOS_ERR, "HECI: HMRFPO_Enable Failed (resp status: %d)\n", resp.status); |
| 758 | return 0; |
| 759 | } |
| 760 | |
| 761 | return 1; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 762 | } |
| 763 | |
| 764 | /* |
| 765 | * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 766 | * The status can be DISABLED/LOCKED/ENABLED |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 767 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 768 | int cse_hmrfpo_get_status(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 769 | { |
| 770 | struct hmrfpo_get_status_msg { |
| 771 | struct mkhi_hdr hdr; |
| 772 | } __packed; |
| 773 | |
| 774 | struct hmrfpo_get_status_resp { |
| 775 | struct mkhi_hdr hdr; |
| 776 | uint8_t status; |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 777 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 778 | } __packed; |
| 779 | |
| 780 | struct hmrfpo_get_status_msg msg = { |
| 781 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 782 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 783 | .command = MKHI_HMRFPO_GET_STATUS, |
| 784 | }, |
| 785 | }; |
| 786 | struct hmrfpo_get_status_resp resp; |
| 787 | size_t resp_size = sizeof(struct hmrfpo_get_status_resp); |
| 788 | |
| 789 | printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); |
| 790 | |
Sridhar Siricilla | 206905c | 2020-02-06 18:48:22 +0530 | [diff] [blame] | 791 | if (!cse_is_hfs1_cws_normal()) { |
| 792 | printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); |
| 793 | return -1; |
| 794 | } |
| 795 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 796 | if (!heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 797 | &resp, &resp_size, HECI_MKHI_ADDR)) { |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 798 | printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); |
| 799 | return -1; |
| 800 | } |
| 801 | |
| 802 | if (resp.hdr.result) { |
| 803 | printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", |
| 804 | resp.hdr.result); |
| 805 | return -1; |
| 806 | } |
| 807 | |
| 808 | return resp.status; |
| 809 | } |
| 810 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 811 | void print_me_fw_version(void *unused) |
| 812 | { |
| 813 | struct version { |
| 814 | uint16_t minor; |
| 815 | uint16_t major; |
| 816 | uint16_t build; |
| 817 | uint16_t hotfix; |
| 818 | } __packed; |
| 819 | |
| 820 | struct fw_ver_resp { |
| 821 | struct mkhi_hdr hdr; |
| 822 | struct version code; |
| 823 | struct version rec; |
| 824 | struct version fitc; |
| 825 | } __packed; |
| 826 | |
| 827 | const struct mkhi_hdr fw_ver_msg = { |
| 828 | .group_id = MKHI_GROUP_ID_GEN, |
| 829 | .command = MKHI_GEN_GET_FW_VERSION, |
| 830 | }; |
| 831 | |
| 832 | struct fw_ver_resp resp; |
| 833 | size_t resp_size = sizeof(resp); |
| 834 | |
| 835 | /* Ignore if UART debugging is disabled */ |
| 836 | if (!CONFIG(CONSOLE_SERIAL)) |
| 837 | return; |
| 838 | |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 839 | /* Ignore if CSE is disabled */ |
| 840 | if (!is_cse_enabled()) |
| 841 | return; |
| 842 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 843 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 844 | * Ignore if ME Firmware SKU type is Lite since |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 845 | * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. |
| 846 | */ |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 847 | if (cse_is_hfs3_fw_sku_lite()) |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 848 | return; |
| 849 | |
| 850 | /* |
| 851 | * Prerequisites: |
| 852 | * 1) HFSTS1 Current Working State is Normal |
| 853 | * 2) HFSTS1 Current Operation Mode is Normal |
| 854 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 855 | * during ramstage |
| 856 | */ |
| 857 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) |
| 858 | goto fail; |
| 859 | |
| 860 | heci_reset(); |
| 861 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 862 | if (!heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), &resp, &resp_size, |
| 863 | HECI_MKHI_ADDR)) |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 864 | goto fail; |
| 865 | |
| 866 | if (resp.hdr.result) |
| 867 | goto fail; |
| 868 | |
| 869 | printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, |
| 870 | resp.code.minor, resp.code.hotfix, resp.code.build); |
| 871 | return; |
| 872 | |
| 873 | fail: |
| 874 | printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); |
| 875 | } |
| 876 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 877 | void cse_trigger_vboot_recovery(enum csme_failure_reason reason) |
| 878 | { |
| 879 | printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " |
| 880 | "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), |
| 881 | me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); |
| 882 | |
| 883 | if (CONFIG(VBOOT)) { |
| 884 | struct vb2_context *ctx = vboot_get_context(); |
| 885 | if (ctx == NULL) |
| 886 | goto failure; |
| 887 | vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, reason); |
| 888 | vboot_save_data(ctx); |
| 889 | vboot_reboot(); |
| 890 | } |
| 891 | failure: |
| 892 | die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); |
| 893 | } |
| 894 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 895 | static bool disable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 896 | { |
| 897 | struct stopwatch sw; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 898 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 899 | dev_idle_ctrl &= ~CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 900 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 901 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 902 | stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 903 | do { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 904 | dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 905 | if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) |
| 906 | return true; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 907 | udelay(HECI_DELAY_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 908 | } while (!stopwatch_expired(&sw)); |
| 909 | |
| 910 | return false; |
| 911 | } |
| 912 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 913 | static void enable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 914 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 915 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 916 | dev_idle_ctrl |= CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 917 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 918 | } |
| 919 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 920 | enum cse_device_state get_cse_device_state(unsigned int devfn) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 921 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 922 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 923 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 924 | if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) |
| 925 | return DEV_IDLE; |
| 926 | |
| 927 | return DEV_ACTIVE; |
| 928 | } |
| 929 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 930 | static enum cse_device_state ensure_cse_active(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 931 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 932 | if (!disable_cse_idle(dev)) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 933 | return DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 934 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 935 | |
| 936 | return DEV_ACTIVE; |
| 937 | } |
| 938 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 939 | static void ensure_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 940 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 941 | enable_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 942 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 943 | pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 944 | } |
| 945 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 946 | bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 947 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 948 | enum cse_device_state current_state = get_cse_device_state(devfn); |
| 949 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 950 | |
| 951 | if (current_state == requested_state) |
| 952 | return true; |
| 953 | |
| 954 | if (requested_state == DEV_ACTIVE) |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 955 | return ensure_cse_active(dev) == requested_state; |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 956 | else |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 957 | ensure_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 958 | |
| 959 | return true; |
| 960 | } |
| 961 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 962 | #if ENV_RAMSTAGE |
| 963 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 964 | static struct device_operations cse_ops = { |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 965 | .set_resources = pci_dev_set_resources, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 966 | .read_resources = pci_dev_read_resources, |
| 967 | .enable_resources = pci_dev_enable_resources, |
| 968 | .init = pci_dev_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 969 | .ops_pci = &pci_dev_ops_pci, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 970 | }; |
| 971 | |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 972 | static const unsigned short pci_device_ids[] = { |
| 973 | PCI_DEVICE_ID_INTEL_APL_CSE0, |
| 974 | PCI_DEVICE_ID_INTEL_GLK_CSE0, |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 975 | PCI_DEVICE_ID_INTEL_CNL_CSE0, |
Subrata Banik | d0586d2 | 2017-11-27 13:28:41 +0530 | [diff] [blame] | 976 | PCI_DEVICE_ID_INTEL_SKL_CSE0, |
Maxim Polyakov | 571d07d | 2019-08-22 13:11:32 +0300 | [diff] [blame] | 977 | PCI_DEVICE_ID_INTEL_LWB_CSE0, |
| 978 | PCI_DEVICE_ID_INTEL_LWB_CSE0_SUPER, |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 979 | PCI_DEVICE_ID_INTEL_CNP_H_CSE0, |
Aamir Bohra | 9eac039 | 2018-06-30 12:07:04 +0530 | [diff] [blame] | 980 | PCI_DEVICE_ID_INTEL_ICL_CSE0, |
Ronak Kanabar | da7ffb48 | 2019-02-05 01:51:13 +0530 | [diff] [blame] | 981 | PCI_DEVICE_ID_INTEL_CMP_CSE0, |
Gaggery Tsai | 12a651c | 2019-12-05 11:23:20 -0800 | [diff] [blame] | 982 | PCI_DEVICE_ID_INTEL_CMP_H_CSE0, |
Ravi Sarawadi | 6b5bf40 | 2019-10-21 22:25:04 -0700 | [diff] [blame] | 983 | PCI_DEVICE_ID_INTEL_TGL_CSE0, |
Jeremy Soller | 191a8d7 | 2021-08-10 14:06:51 -0600 | [diff] [blame] | 984 | PCI_DEVICE_ID_INTEL_TGL_H_CSE0, |
Tan, Lean Sheng | 2613609 | 2020-01-20 19:13:56 -0800 | [diff] [blame] | 985 | PCI_DEVICE_ID_INTEL_MCC_CSE0, |
| 986 | PCI_DEVICE_ID_INTEL_MCC_CSE1, |
| 987 | PCI_DEVICE_ID_INTEL_MCC_CSE2, |
| 988 | PCI_DEVICE_ID_INTEL_MCC_CSE3, |
Meera Ravindranath | 3f4af0d | 2020-02-12 16:01:22 +0530 | [diff] [blame] | 989 | PCI_DEVICE_ID_INTEL_JSP_CSE0, |
| 990 | PCI_DEVICE_ID_INTEL_JSP_CSE1, |
| 991 | PCI_DEVICE_ID_INTEL_JSP_CSE2, |
| 992 | PCI_DEVICE_ID_INTEL_JSP_CSE3, |
Subrata Banik | f672f7f | 2020-08-03 14:29:25 +0530 | [diff] [blame] | 993 | PCI_DEVICE_ID_INTEL_ADP_P_CSE0, |
| 994 | PCI_DEVICE_ID_INTEL_ADP_P_CSE1, |
| 995 | PCI_DEVICE_ID_INTEL_ADP_P_CSE2, |
| 996 | PCI_DEVICE_ID_INTEL_ADP_P_CSE3, |
| 997 | PCI_DEVICE_ID_INTEL_ADP_S_CSE0, |
| 998 | PCI_DEVICE_ID_INTEL_ADP_S_CSE1, |
| 999 | PCI_DEVICE_ID_INTEL_ADP_S_CSE2, |
| 1000 | PCI_DEVICE_ID_INTEL_ADP_S_CSE3, |
Varshit Pandya | f4d98fdd2 | 2021-01-17 18:39:29 +0530 | [diff] [blame] | 1001 | PCI_DEVICE_ID_INTEL_ADP_M_CSE0, |
| 1002 | PCI_DEVICE_ID_INTEL_ADP_M_CSE1, |
| 1003 | PCI_DEVICE_ID_INTEL_ADP_M_CSE2, |
| 1004 | PCI_DEVICE_ID_INTEL_ADP_M_CSE3, |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1005 | 0, |
| 1006 | }; |
| 1007 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1008 | static const struct pci_driver cse_driver __pci_driver = { |
| 1009 | .ops = &cse_ops, |
| 1010 | .vendor = PCI_VENDOR_ID_INTEL, |
| 1011 | /* SoC/chipset needs to provide PCI device ID */ |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 1012 | .devices = pci_device_ids |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1013 | }; |
| 1014 | |
| 1015 | #endif |