Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | |
Elyes HAOUAS | 1a4abb7 | 2018-05-19 16:49:20 +0200 | [diff] [blame] | 18 | #include <device/device.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 19 | #include <device/pci.h> /* device_operations */ |
| 20 | #include <device/pci_ids.h> |
Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 21 | #include <bootstate.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 22 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 23 | #include <device/smbus.h> /* smbus_bus_operations */ |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 24 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame] | 25 | #include <pc80/i8254.h> |
| 26 | #include <pc80/i8259.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 27 | #include <console/console.h> /* printk */ |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Kyösti Mälkki | e2227a2 | 2014-02-05 13:02:55 +0200 | [diff] [blame] | 29 | #include <device/pci_ehci.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 30 | #include "lpc.h" /* lpc_read_resources */ |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame^] | 31 | #include "SBPLATFORM.h" /* Platform Specific Definitions */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 32 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 33 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 34 | #include "sb_cimx.h" /* AMD CIMX wrapper entries */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 35 | #include "smbus.h" |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 36 | #include "fan.h" |
Tobias Diedrich | d8a2c1f | 2017-02-20 02:46:19 +0100 | [diff] [blame] | 37 | #include "pci_devs.h" |
Stefan Reinauer | 13e4182 | 2015-04-27 14:02:36 -0700 | [diff] [blame] | 38 | #include <southbridge/amd/common/amd_pci_util.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 39 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 40 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 41 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 42 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 43 | /** |
| 44 | * @brief Entry point of Southbridge CIMx callout |
| 45 | * |
| 46 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 47 | * |
| 48 | * @param[in] func Southbridge CIMx Function ID. |
| 49 | * @param[in] data Southbridge Input Data. |
Martin Roth | 6355cbf | 2015-01-04 15:22:26 -0700 | [diff] [blame] | 50 | * @param[in] config Southbridge configuration structure pointer. |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 51 | * |
| 52 | */ |
Kyösti Mälkki | 41cd047 | 2015-02-07 11:20:54 +0200 | [diff] [blame] | 53 | static u32 sb800_callout_entry(u32 func, u32 data, void* config) |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 54 | { |
| 55 | u32 ret = 0; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 56 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 57 | switch (func) { |
| 58 | case CB_SBGPP_RESET_ASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 59 | break; |
| 60 | |
| 61 | case CB_SBGPP_RESET_DEASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 62 | break; |
| 63 | |
| 64 | case IMC_FIRMWARE_FAIL: |
| 65 | break; |
| 66 | |
| 67 | default: |
| 68 | break; |
| 69 | } |
| 70 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 71 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 72 | return ret; |
| 73 | } |
| 74 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 75 | #define HOST_CAP 0x00 /* host capabilities */ |
| 76 | #define HOST_CTL 0x04 /* global host control */ |
| 77 | #define HOST_IRQ_STAT 0x08 /* interrupt status */ |
| 78 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
| 79 | |
| 80 | #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ |
| 81 | static void ahci_raid_init(struct device *dev) |
| 82 | { |
| 83 | u8 irq = 0; |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 84 | void *bar5; |
| 85 | u32 caps, ports, val; |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 86 | |
| 87 | val = pci_read_config16(dev, PCI_CLASS_DEVICE); |
| 88 | if (val == PCI_CLASS_STORAGE_SATA) { |
| 89 | printk(BIOS_DEBUG, "AHCI controller "); |
| 90 | } else if (val == PCI_CLASS_STORAGE_RAID) { |
| 91 | printk(BIOS_DEBUG, "RAID controller "); |
| 92 | } else { |
| 93 | printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 98 | bar5 = (void *)(uintptr_t)pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 99 | printk(BIOS_DEBUG, "IOMEM base: %p, IRQ: 0x%X\n", bar5, irq); |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 100 | |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 101 | caps = read32(bar5 + HOST_CAP); |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 102 | caps = (caps & 0x1F) + 1; |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 103 | ports= read32(bar5 + HOST_PORTS_IMPL); |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 104 | printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); |
| 105 | |
| 106 | /* make sure ahci is enabled */ |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 107 | val = read32(bar5 + HOST_CTL); |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 108 | if (!(val & HOST_CTL_AHCI_EN)) { |
Stefan Reinauer | 12bce3f | 2015-06-18 01:17:38 -0700 | [diff] [blame] | 109 | write32(bar5 + HOST_CTL, val | HOST_CTL_AHCI_EN); |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 110 | } |
| 111 | |
| 112 | dev->command |= PCI_COMMAND_MASTER; |
| 113 | pci_write_config8(dev, PCI_COMMAND, dev->command); |
| 114 | printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); |
| 115 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 116 | |
| 117 | static struct pci_operations lops_pci = { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 118 | .set_subsystem = pci_dev_set_subsystem, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 119 | }; |
| 120 | |
Elyes HAOUAS | 1a4abb7 | 2018-05-19 16:49:20 +0200 | [diff] [blame] | 121 | static void lpc_init(struct device *dev) |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 122 | { |
| 123 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); |
| 124 | |
Gabe Black | 03abaee21 | 2014-04-30 21:31:44 -0700 | [diff] [blame] | 125 | cmos_check_update_date(); |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 126 | |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 127 | /* Initialize the real time clock. |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 128 | * The 0 argument tells cmos_init not to |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 129 | * update CMOS unless it is invalid. |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 130 | * 1 tells cmos_init to always initialize the CMOS. |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 131 | */ |
Gabe Black | b3f08c6 | 2014-04-30 17:12:25 -0700 | [diff] [blame] | 132 | cmos_init(0); |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 133 | |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame] | 134 | setup_i8259(); /* Initialize i8259 pic */ |
| 135 | setup_i8254(); /* Initialize i8254 timers */ |
| 136 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 137 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); |
| 138 | } |
| 139 | |
Vladimir Serbinenko | 2a19fb1 | 2014-10-02 20:09:19 +0200 | [diff] [blame] | 140 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 141 | { |
| 142 | /* Just a dummy */ |
| 143 | return current; |
| 144 | } |
| 145 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 146 | static const char *lpc_acpi_name(const struct device *dev) |
Tobias Diedrich | d8a2c1f | 2017-02-20 02:46:19 +0100 | [diff] [blame] | 147 | { |
| 148 | if (dev->path.type != DEVICE_PATH_PCI) |
| 149 | return NULL; |
| 150 | |
| 151 | switch (dev->path.pci.devfn) { |
| 152 | /* DSDT: acpi/lpc.asl */ |
| 153 | case LPC_DEVFN: |
| 154 | return "LIBR"; |
| 155 | } |
| 156 | |
| 157 | return NULL; |
| 158 | } |
| 159 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 160 | static struct device_operations lpc_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 161 | .read_resources = lpc_read_resources, |
| 162 | .set_resources = lpc_set_resources, |
| 163 | .enable_resources = pci_dev_enable_resources, |
Vladimir Serbinenko | 83f81ca | 2014-11-09 13:30:50 +0100 | [diff] [blame] | 164 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Vladimir Serbinenko | 2a19fb1 | 2014-10-02 20:09:19 +0200 | [diff] [blame] | 165 | .write_acpi_tables = acpi_write_hpet, |
| 166 | #endif |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 167 | .init = lpc_init, |
| 168 | .scan_bus = scan_lpc_bus, |
| 169 | .ops_pci = &lops_pci, |
Tobias Diedrich | d8a2c1f | 2017-02-20 02:46:19 +0100 | [diff] [blame] | 170 | .acpi_name = lpc_acpi_name, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 171 | }; |
| 172 | |
| 173 | static const struct pci_driver lpc_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 174 | .ops = &lpc_ops, |
| 175 | .vendor = PCI_VENDOR_ID_ATI, |
| 176 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 177 | }; |
| 178 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 179 | static struct device_operations sata_ops = { |
| 180 | .read_resources = pci_dev_read_resources, |
| 181 | .set_resources = pci_dev_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 182 | .enable_resources = pci_dev_enable_resources, |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 183 | .init = ahci_raid_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 184 | .scan_bus = 0, |
| 185 | .ops_pci = &lops_pci, |
| 186 | }; |
| 187 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 188 | static const struct pci_driver ahci_driver __pci_driver = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 189 | .ops = &sata_ops, |
| 190 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 191 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 192 | }; |
| 193 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 194 | static const struct pci_driver raid_driver __pci_driver = { |
| 195 | .ops = &sata_ops, |
| 196 | .vendor = PCI_VENDOR_ID_ATI, |
| 197 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, |
| 198 | }; |
| 199 | static const struct pci_driver raid5_driver __pci_driver = { |
| 200 | .ops = &sata_ops, |
| 201 | .vendor = PCI_VENDOR_ID_ATI, |
| 202 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, |
| 203 | }; |
| 204 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 205 | static struct device_operations usb_ops = { |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame] | 206 | .read_resources = pci_ehci_read_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 207 | .set_resources = pci_dev_set_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 208 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 209 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 210 | .scan_bus = 0, |
| 211 | .ops_pci = &lops_pci, |
| 212 | }; |
| 213 | |
| 214 | /* |
| 215 | * The pci id of usb ctrl 0 and 1 are the same. |
| 216 | */ |
| 217 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 218 | .ops = &usb_ops, |
| 219 | .vendor = PCI_VENDOR_ID_ATI, |
| 220 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 221 | }; |
| 222 | |
| 223 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 224 | .ops = &usb_ops, |
| 225 | .vendor = PCI_VENDOR_ID_ATI, |
| 226 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 227 | }; |
| 228 | |
| 229 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 230 | .ops = &usb_ops, |
| 231 | .vendor = PCI_VENDOR_ID_ATI, |
| 232 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 233 | }; |
| 234 | |
| 235 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 236 | static struct device_operations azalia_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 237 | .read_resources = pci_dev_read_resources, |
| 238 | .set_resources = pci_dev_set_resources, |
| 239 | .enable_resources = pci_dev_enable_resources, |
| 240 | .init = 0, |
| 241 | .scan_bus = 0, |
| 242 | .ops_pci = &lops_pci, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 243 | }; |
| 244 | |
| 245 | static const struct pci_driver azalia_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 246 | .ops = &azalia_ops, |
| 247 | .vendor = PCI_VENDOR_ID_ATI, |
| 248 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 249 | }; |
| 250 | |
| 251 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 252 | static struct device_operations gec_ops = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 253 | .read_resources = pci_dev_read_resources, |
| 254 | .set_resources = pci_dev_set_resources, |
| 255 | .enable_resources = pci_dev_enable_resources, |
| 256 | .init = 0, |
| 257 | .scan_bus = 0, |
| 258 | .ops_pci = &lops_pci, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 259 | }; |
| 260 | |
| 261 | static const struct pci_driver gec_driver __pci_driver = { |
Elyes HAOUAS | ba28e8d | 2016-08-31 19:22:16 +0200 | [diff] [blame] | 262 | .ops = &gec_ops, |
| 263 | .vendor = PCI_VENDOR_ID_ATI, |
| 264 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 265 | }; |
| 266 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 267 | /** |
Kyösti Mälkki | 41cd047 | 2015-02-07 11:20:54 +0200 | [diff] [blame] | 268 | * Fill build time defaults. |
| 269 | */ |
| 270 | static void sb800_init(void *chip_info) |
| 271 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 272 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
Kyösti Mälkki | 41cd047 | 2015-02-07 11:20:54 +0200 | [diff] [blame] | 273 | sb_config->StdHeader.CALLBACK.CalloutPtr = sb800_callout_entry; |
| 274 | sb800_cimx_config(sb_config); |
Kyösti Mälkki | 24501ca | 2015-02-07 17:38:45 +0200 | [diff] [blame] | 275 | |
Paul Menzel | 114a948 | 2015-10-25 22:27:42 +0100 | [diff] [blame] | 276 | /* Initially enable all GPP ports 0 to 3 */ |
Kyösti Mälkki | 24501ca | 2015-02-07 17:38:45 +0200 | [diff] [blame] | 277 | abcfg_reg(0xc0, 0x01FF, 0x0F4); |
Kyösti Mälkki | 41cd047 | 2015-02-07 11:20:54 +0200 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | /** |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 281 | * South Bridge CIMx ramstage entry point wrapper. |
| 282 | */ |
| 283 | void sb_Before_Pci_Init(void) |
| 284 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 285 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 286 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 287 | AmdSbDispatcher(sb_config); |
| 288 | } |
| 289 | |
| 290 | void sb_After_Pci_Init(void) |
| 291 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 292 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 293 | sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; |
| 294 | AmdSbDispatcher(sb_config); |
| 295 | } |
| 296 | |
| 297 | void sb_Mid_Post_Init(void) |
| 298 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 299 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 300 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 301 | AmdSbDispatcher(sb_config); |
| 302 | } |
| 303 | |
| 304 | void sb_Late_Post(void) |
| 305 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 306 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 307 | sb_config->StdHeader.Func = SB_LATE_POST_INIT; |
| 308 | AmdSbDispatcher(sb_config); |
| 309 | } |
| 310 | |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 311 | void sb_Before_Pci_Restore_Init(void) |
| 312 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 313 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 314 | sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; |
| 315 | AmdSbDispatcher(sb_config); |
| 316 | } |
| 317 | |
| 318 | void sb_After_Pci_Restore_Init(void) |
| 319 | { |
Kyösti Mälkki | 1498efe | 2017-03-09 16:25:24 +0200 | [diff] [blame] | 320 | printk(BIOS_DEBUG, "SB800: %s\n", __func__); |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 321 | sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; |
| 322 | AmdSbDispatcher(sb_config); |
| 323 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 324 | |
Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 325 | /* |
| 326 | * Update the PCI devices with a valid IRQ number |
| 327 | * that is set in the mainboard PCI_IRQ structures. |
| 328 | */ |
| 329 | static void set_pci_irqs(void *unused) |
| 330 | { |
| 331 | /* Write PCI_INTR regs 0xC00/0xC01 */ |
| 332 | write_pci_int_table(); |
| 333 | |
| 334 | /* Write IRQs for all devicetree enabled devices */ |
| 335 | write_pci_cfg_irqs(); |
| 336 | } |
| 337 | |
| 338 | /* |
| 339 | * Hook this function into the PCI state machine |
| 340 | * on entry into BS_DEV_ENABLE. |
| 341 | */ |
Aaron Durbin | 9ef9d85 | 2015-03-16 17:30:09 -0500 | [diff] [blame] | 342 | BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); |
Mike Loptien | c93a75a | 2014-06-06 15:16:29 -0600 | [diff] [blame] | 343 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 344 | /** |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 345 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 346 | */ |
Elyes HAOUAS | 1a4abb7 | 2018-05-19 16:49:20 +0200 | [diff] [blame] | 347 | static void sb800_enable(struct device *dev) |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 348 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 349 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 350 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 351 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 352 | switch (dev->path.pci.devfn) { |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 353 | case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 354 | if (dev->enabled) { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame^] | 355 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 356 | if (1 == sb_chip->boot_switch_sata_ide) |
| 357 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 358 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 359 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 360 | } else { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame^] | 361 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 362 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 363 | break; |
| 364 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 365 | case PCI_DEVFN(0x14, 0): /* 0:14:0 SMBUS */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 366 | clear_ioapic(VIO_APIC_VADDR); |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 367 | #if IS_ENABLED(CONFIG_CPU_AMD_AGESA) |
Kyösti Mälkki | 35546de | 2014-04-17 15:07:32 +0300 | [diff] [blame] | 368 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 369 | setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); |
Kyösti Mälkki | 35546de | 2014-04-17 15:07:32 +0300 | [diff] [blame] | 370 | #else |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 371 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 372 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 373 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 374 | setup_ioapic(VIO_APIC_VADDR, |
| 375 | CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 376 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
| 377 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 378 | setup_ioapic(VIO_APIC_VADDR, 0); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 379 | #else |
| 380 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 381 | #endif |
Kyösti Mälkki | 35546de | 2014-04-17 15:07:32 +0300 | [diff] [blame] | 382 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 383 | break; |
| 384 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 385 | case PCI_DEVFN(0x14, 1): /* 0:14:1 IDE */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 386 | break; |
| 387 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 388 | case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 389 | if (dev->enabled) { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame^] | 390 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 391 | sb_config->AzaliaController = AZALIA_AUTO; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 392 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 393 | } else { |
Elyes HAOUAS | b0f1988 | 2018-06-09 11:59:00 +0200 | [diff] [blame^] | 394 | sb_config->AzaliaController = AZALIA_DISABLE; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 395 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 396 | break; |
| 397 | |
| 398 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 399 | case PCI_DEVFN(0x14, 3): /* 0:14:3 LPC */ |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 400 | /* Initialize the fans */ |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 401 | #if IS_ENABLED(CONFIG_SB800_IMC_FAN_CONTROL) |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 402 | init_sb800_IMC_fans(dev); |
Martin Roth | 083504b | 2017-06-24 21:30:14 -0600 | [diff] [blame] | 403 | #elif IS_ENABLED(CONFIG_SB800_MANUAL_FAN_CONTROL) |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 404 | init_sb800_MANUAL_fans(dev); |
| 405 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 406 | break; |
| 407 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 408 | case PCI_DEVFN(0x14, 4): /* 0:14:4 PCI */ |
Kyösti Mälkki | 486c05f | 2015-01-17 18:08:40 +0200 | [diff] [blame] | 409 | /* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 410 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 411 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 412 | * to function as GPIO {GPIO 35:0}. |
| 413 | */ |
Kyösti Mälkki | 0b87bb7 | 2014-11-11 17:22:23 +0200 | [diff] [blame] | 414 | if (!sb_chip->disconnect_pcib && dev->enabled) |
Kyösti Mälkki | 486c05f | 2015-01-17 18:08:40 +0200 | [diff] [blame] | 415 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 416 | else |
| 417 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, BIT0); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 418 | break; |
| 419 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 420 | case PCI_DEVFN(0x14, 6): /* 0:14:6 GEC */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 421 | if (dev->enabled) { |
| 422 | sb_config->GecConfig = 0; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 423 | } else { |
| 424 | sb_config->GecConfig = 1; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 425 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 426 | break; |
| 427 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 428 | case PCI_DEVFN(0x15, 0): /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 429 | { |
Elyes HAOUAS | 1a4abb7 | 2018-05-19 16:49:20 +0200 | [diff] [blame] | 430 | struct device *device; |
Paul Menzel | e4a016f | 2013-03-01 13:05:04 +0100 | [diff] [blame] | 431 | for (device = dev; device; device = device->sibling) { |
| 432 | if ((device->path.pci.devfn & ~3) != PCI_DEVFN(0x15,0)) break; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 433 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 434 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 435 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 436 | /* |
| 437 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 438 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 439 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 440 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 441 | */ |
| 442 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 443 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 444 | break; |
| 445 | |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 446 | case PCI_DEVFN(0x12, 0): /* 0:12:0 OHCI-USB1 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 447 | sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; |
| 448 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 449 | case PCI_DEVFN(0x12, 2): /* 0:12:2 EHCI-USB1 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 450 | sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; |
| 451 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 452 | case PCI_DEVFN(0x13, 0): /* 0:13:0 OHCI-USB2 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 453 | sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; |
| 454 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 455 | case PCI_DEVFN(0x13, 2): /* 0:13:2 EHCI-USB2 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 456 | sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; |
| 457 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 458 | case PCI_DEVFN(0x14, 5): /* 0:14:5 OHCI-USB4 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 459 | sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; |
| 460 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 461 | case PCI_DEVFN(0x16, 0): /* 0:16:0 OHCI-USB3 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 462 | sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; |
| 463 | break; |
Kyösti Mälkki | dda0fc4 | 2018-05-20 14:17:19 +0300 | [diff] [blame] | 464 | case PCI_DEVFN(0x16, 2): /* 0:16:2 EHCI-USB3 */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 465 | sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; |
| 466 | |
Kyösti Mälkki | 9de8ab9 | 2017-09-09 16:51:34 +0300 | [diff] [blame] | 467 | /* FIXME: Find better callsites for these. |
| 468 | * call the CIMX entry at the last sb800 device, |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame] | 469 | * so make sure the mainboard devicetree is complete |
| 470 | */ |
Kyösti Mälkki | c551caa | 2014-06-20 12:31:23 +0300 | [diff] [blame] | 471 | if (!acpi_is_wakeup_s3()) |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 472 | sb_Before_Pci_Init(); |
| 473 | else |
| 474 | sb_Before_Pci_Restore_Init(); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 475 | break; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 476 | |
| 477 | default: |
| 478 | break; |
| 479 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 480 | } |
| 481 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 482 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 483 | CHIP_NAME("ATI SB800") |
Kyösti Mälkki | 41cd047 | 2015-02-07 11:20:54 +0200 | [diff] [blame] | 484 | .init = sb800_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 485 | .enable_dev = sb800_enable, |
| 486 | }; |