Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <device/device.h> /* device_t */ |
| 22 | #include <device/pci.h> /* device_operations */ |
| 23 | #include <device/pci_ids.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 24 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | #include <device/smbus.h> /* smbus_bus_operations */ |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame^] | 27 | #include <pc80/i8254.h> |
| 28 | #include <pc80/i8259.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 29 | #include <console/console.h> /* printk */ |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 30 | #include <arch/acpi.h> |
Kyösti Mälkki | e2227a2 | 2014-02-05 13:02:55 +0200 | [diff] [blame] | 31 | #include <device/pci_ehci.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 32 | #include "lpc.h" /* lpc_read_resources */ |
| 33 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
| 34 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 35 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 36 | #include "sb_cimx.h" /* AMD CIMX wrapper entries */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 37 | #include "smbus.h" |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 38 | #include "fan.h" |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 39 | |
| 40 | /*implement in mainboard.c*/ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 41 | void set_pcie_reset(void); |
| 42 | void set_pcie_dereset(void); |
| 43 | |
| 44 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 45 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 46 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 47 | |
| 48 | |
| 49 | /** |
| 50 | * @brief Entry point of Southbridge CIMx callout |
| 51 | * |
| 52 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 53 | * |
| 54 | * @param[in] func Southbridge CIMx Function ID. |
| 55 | * @param[in] data Southbridge Input Data. |
| 56 | * @param[in] sb_config Southbridge configuration structure pointer. |
| 57 | * |
| 58 | */ |
| 59 | u32 sb800_callout_entry(u32 func, u32 data, void* config) |
| 60 | { |
| 61 | u32 ret = 0; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 62 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 63 | switch (func) { |
| 64 | case CB_SBGPP_RESET_ASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 65 | set_pcie_reset(); |
| 66 | break; |
| 67 | |
| 68 | case CB_SBGPP_RESET_DEASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 69 | set_pcie_dereset(); |
| 70 | break; |
| 71 | |
| 72 | case IMC_FIRMWARE_FAIL: |
| 73 | break; |
| 74 | |
| 75 | default: |
| 76 | break; |
| 77 | } |
| 78 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 79 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 80 | return ret; |
| 81 | } |
| 82 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 83 | #define HOST_CAP 0x00 /* host capabilities */ |
| 84 | #define HOST_CTL 0x04 /* global host control */ |
| 85 | #define HOST_IRQ_STAT 0x08 /* interrupt status */ |
| 86 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
| 87 | |
| 88 | #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ |
| 89 | static void ahci_raid_init(struct device *dev) |
| 90 | { |
| 91 | u8 irq = 0; |
| 92 | u32 bar5, caps, ports, val; |
| 93 | |
| 94 | val = pci_read_config16(dev, PCI_CLASS_DEVICE); |
| 95 | if (val == PCI_CLASS_STORAGE_SATA) { |
| 96 | printk(BIOS_DEBUG, "AHCI controller "); |
| 97 | } else if (val == PCI_CLASS_STORAGE_RAID) { |
| 98 | printk(BIOS_DEBUG, "RAID controller "); |
| 99 | } else { |
| 100 | printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); |
| 101 | return; |
| 102 | } |
| 103 | |
| 104 | irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); |
| 105 | bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 106 | printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); |
| 107 | |
| 108 | caps = *(volatile u32 *)(bar5 + HOST_CAP); |
| 109 | caps = (caps & 0x1F) + 1; |
| 110 | ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); |
| 111 | printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); |
| 112 | |
| 113 | /* make sure ahci is enabled */ |
| 114 | val = *(volatile u32 *)(bar5 + HOST_CTL); |
| 115 | if (!(val & HOST_CTL_AHCI_EN)) { |
| 116 | *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; |
| 117 | } |
| 118 | |
| 119 | dev->command |= PCI_COMMAND_MASTER; |
| 120 | pci_write_config8(dev, PCI_COMMAND, dev->command); |
| 121 | printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); |
| 122 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 123 | |
| 124 | static struct pci_operations lops_pci = { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 125 | .set_subsystem = pci_dev_set_subsystem, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 126 | }; |
| 127 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 128 | static void lpc_init(device_t dev) |
| 129 | { |
| 130 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); |
| 131 | |
| 132 | rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); |
| 133 | |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 134 | /* Initialize the real time clock. |
| 135 | * The 0 argument tells rtc_init not to |
| 136 | * update CMOS unless it is invalid. |
| 137 | * 1 tells rtc_init to always initialize the CMOS. |
| 138 | */ |
| 139 | rtc_init(0); |
| 140 | |
Edward O'Callaghan | e61dd0f | 2014-05-06 23:53:09 +1000 | [diff] [blame^] | 141 | setup_i8259(); /* Initialize i8259 pic */ |
| 142 | setup_i8254(); /* Initialize i8254 timers */ |
| 143 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); |
| 145 | } |
| 146 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 147 | static struct device_operations lpc_ops = { |
| 148 | .read_resources = lpc_read_resources, |
| 149 | .set_resources = lpc_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 150 | .enable_resources = pci_dev_enable_resources, |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 151 | .init = lpc_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 152 | .scan_bus = scan_static_bus, |
| 153 | .ops_pci = &lops_pci, |
| 154 | }; |
| 155 | |
| 156 | static const struct pci_driver lpc_driver __pci_driver = { |
| 157 | .ops = &lpc_ops, |
| 158 | .vendor = PCI_VENDOR_ID_ATI, |
| 159 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
| 160 | }; |
| 161 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 162 | static struct device_operations sata_ops = { |
| 163 | .read_resources = pci_dev_read_resources, |
| 164 | .set_resources = pci_dev_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 165 | .enable_resources = pci_dev_enable_resources, |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 166 | .init = ahci_raid_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 167 | .scan_bus = 0, |
| 168 | .ops_pci = &lops_pci, |
| 169 | }; |
| 170 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 171 | static const struct pci_driver ahci_driver __pci_driver = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 172 | .ops = &sata_ops, |
| 173 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 174 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 175 | }; |
| 176 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 177 | static const struct pci_driver raid_driver __pci_driver = { |
| 178 | .ops = &sata_ops, |
| 179 | .vendor = PCI_VENDOR_ID_ATI, |
| 180 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, |
| 181 | }; |
| 182 | static const struct pci_driver raid5_driver __pci_driver = { |
| 183 | .ops = &sata_ops, |
| 184 | .vendor = PCI_VENDOR_ID_ATI, |
| 185 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, |
| 186 | }; |
| 187 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 188 | static struct device_operations usb_ops = { |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame] | 189 | .read_resources = pci_ehci_read_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 190 | .set_resources = pci_dev_set_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 191 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 192 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 193 | .scan_bus = 0, |
| 194 | .ops_pci = &lops_pci, |
| 195 | }; |
| 196 | |
| 197 | /* |
| 198 | * The pci id of usb ctrl 0 and 1 are the same. |
| 199 | */ |
| 200 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 201 | .ops = &usb_ops, |
| 202 | .vendor = PCI_VENDOR_ID_ATI, |
| 203 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 204 | }; |
| 205 | |
| 206 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 207 | .ops = &usb_ops, |
| 208 | .vendor = PCI_VENDOR_ID_ATI, |
| 209 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 210 | }; |
| 211 | |
| 212 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 213 | .ops = &usb_ops, |
| 214 | .vendor = PCI_VENDOR_ID_ATI, |
| 215 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 216 | }; |
| 217 | |
| 218 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 219 | static struct device_operations azalia_ops = { |
| 220 | .read_resources = pci_dev_read_resources, |
| 221 | .set_resources = pci_dev_set_resources, |
| 222 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 223 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 224 | .scan_bus = 0, |
| 225 | .ops_pci = &lops_pci, |
| 226 | }; |
| 227 | |
| 228 | static const struct pci_driver azalia_driver __pci_driver = { |
| 229 | .ops = &azalia_ops, |
| 230 | .vendor = PCI_VENDOR_ID_ATI, |
| 231 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
| 232 | }; |
| 233 | |
| 234 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 235 | static struct device_operations gec_ops = { |
| 236 | .read_resources = pci_dev_read_resources, |
| 237 | .set_resources = pci_dev_set_resources, |
| 238 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 239 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 240 | .scan_bus = 0, |
| 241 | .ops_pci = &lops_pci, |
| 242 | }; |
| 243 | |
| 244 | static const struct pci_driver gec_driver __pci_driver = { |
| 245 | .ops = &gec_ops, |
| 246 | .vendor = PCI_VENDOR_ID_ATI, |
| 247 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
| 248 | }; |
| 249 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 250 | /** |
| 251 | * @brief Enable PCI Bridge |
| 252 | * |
| 253 | * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 254 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 255 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 256 | * to function as GPIO {GPIO 35:0}. |
| 257 | */ |
| 258 | static void pci_init(device_t dev) |
| 259 | { |
| 260 | /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, |
| 261 | * but actually was disabled in some platform, so I have to enabled it. |
| 262 | */ |
| 263 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 264 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 265 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 266 | |
| 267 | static struct device_operations pci_ops = { |
| 268 | .read_resources = pci_bus_read_resources, |
| 269 | .set_resources = pci_dev_set_resources, |
| 270 | .enable_resources = pci_bus_enable_resources, |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 271 | .init = pci_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 272 | .scan_bus = pci_scan_bridge, |
| 273 | .reset_bus = pci_bus_reset, |
| 274 | .ops_pci = &lops_pci, |
| 275 | }; |
| 276 | |
| 277 | static const struct pci_driver pci_driver __pci_driver = { |
| 278 | .ops = &pci_ops, |
| 279 | .vendor = PCI_VENDOR_ID_ATI, |
| 280 | .device = PCI_DEVICE_ID_ATI_SB800_PCI, |
| 281 | }; |
| 282 | |
| 283 | |
| 284 | struct device_operations bridge_ops = { |
| 285 | .read_resources = pci_bus_read_resources, |
| 286 | .set_resources = pci_dev_set_resources, |
| 287 | .enable_resources = pci_bus_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 288 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 289 | .scan_bus = pci_scan_bridge, |
| 290 | .enable = 0, |
| 291 | .reset_bus = pci_bus_reset, |
| 292 | .ops_pci = &lops_pci, |
| 293 | }; |
| 294 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 295 | /** |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 296 | * South Bridge CIMx ramstage entry point wrapper. |
| 297 | */ |
| 298 | void sb_Before_Pci_Init(void) |
| 299 | { |
| 300 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 301 | AmdSbDispatcher(sb_config); |
| 302 | } |
| 303 | |
| 304 | void sb_After_Pci_Init(void) |
| 305 | { |
| 306 | sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; |
| 307 | AmdSbDispatcher(sb_config); |
| 308 | } |
| 309 | |
| 310 | void sb_Mid_Post_Init(void) |
| 311 | { |
| 312 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 313 | AmdSbDispatcher(sb_config); |
| 314 | } |
| 315 | |
| 316 | void sb_Late_Post(void) |
| 317 | { |
| 318 | sb_config->StdHeader.Func = SB_LATE_POST_INIT; |
| 319 | AmdSbDispatcher(sb_config); |
| 320 | } |
| 321 | |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 322 | void sb_Before_Pci_Restore_Init(void) |
| 323 | { |
| 324 | sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; |
| 325 | AmdSbDispatcher(sb_config); |
| 326 | } |
| 327 | |
| 328 | void sb_After_Pci_Restore_Init(void) |
| 329 | { |
| 330 | sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; |
| 331 | AmdSbDispatcher(sb_config); |
| 332 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 333 | |
| 334 | /** |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 335 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 336 | */ |
| 337 | static void sb800_enable(device_t dev) |
| 338 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 339 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 340 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 341 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 342 | printk(BIOS_DEBUG, "sb800_enable() "); |
| 343 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 344 | switch (dev->path.pci.devfn) { |
| 345 | case (0x11 << 3) | 0: /* 0:11.0 SATA */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 346 | /* the first sb800 device */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 347 | switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ |
| 348 | case GPP_CFGMODE_X2200: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 349 | abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 350 | break; |
| 351 | case GPP_CFGMODE_X2110: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 352 | abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 353 | break; |
| 354 | case GPP_CFGMODE_X1111: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 355 | abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 356 | break; |
| 357 | case GPP_CFGMODE_X4000: |
| 358 | default: |
| 359 | abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ |
| 360 | break; |
| 361 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 362 | sb800_cimx_config(sb_config); |
| 363 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 364 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 365 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 366 | if (1 == sb_chip->boot_switch_sata_ide) |
| 367 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 368 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 369 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 370 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 371 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 372 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 373 | break; |
| 374 | |
| 375 | case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 376 | printk(BIOS_INFO, "sm_init().\n"); |
| 377 | clear_ioapic(IO_APIC_ADDR); |
Kyösti Mälkki | 35546de | 2014-04-17 15:07:32 +0300 | [diff] [blame] | 378 | #if CONFIG_CPU_AMD_AGESA |
| 379 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 380 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS); |
| 381 | #else |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 382 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 383 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 384 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 385 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
| 386 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
| 387 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
| 388 | setup_ioapic(IO_APIC_ADDR, 0); |
| 389 | #else |
| 390 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 391 | #endif |
Kyösti Mälkki | 35546de | 2014-04-17 15:07:32 +0300 | [diff] [blame] | 392 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 393 | break; |
| 394 | |
| 395 | case (0x14 << 3) | 1: /* 0:14:1 IDE */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 396 | break; |
| 397 | |
| 398 | case (0x14 << 3) | 2: /* 0:14:2 HDA */ |
| 399 | if (dev->enabled) { |
| 400 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 401 | sb_config->AzaliaController = AZALIA_AUTO; |
| 402 | } |
| 403 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 404 | } else { |
| 405 | sb_config->AzaliaController = AZALIA_DISABLE; |
| 406 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 407 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 408 | break; |
| 409 | |
| 410 | |
| 411 | case (0x14 << 3) | 3: /* 0:14:3 LPC */ |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 412 | /* Initialize the fans */ |
| 413 | #if CONFIG_SB800_IMC_FAN_CONTROL |
| 414 | init_sb800_IMC_fans(dev); |
| 415 | #elif CONFIG_SB800_MANUAL_FAN_CONTROL |
| 416 | init_sb800_MANUAL_fans(dev); |
| 417 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 418 | break; |
| 419 | |
| 420 | case (0x14 << 3) | 4: /* 0:14:4 PCI */ |
| 421 | break; |
| 422 | |
| 423 | case (0x14 << 3) | 6: /* 0:14:6 GEC */ |
| 424 | if (dev->enabled) { |
| 425 | sb_config->GecConfig = 0; |
| 426 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 427 | } else { |
| 428 | sb_config->GecConfig = 1; |
| 429 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 430 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 431 | break; |
| 432 | |
| 433 | case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 434 | { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 435 | device_t device; |
| 436 | for (device = dev; device; device = device->next) { |
| 437 | if (dev->path.type != DEVICE_PATH_PCI) continue; |
| 438 | if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; |
| 439 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 440 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 441 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 442 | /* |
| 443 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 444 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 445 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 446 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 447 | */ |
| 448 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 449 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 450 | break; |
| 451 | |
| 452 | case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ |
| 453 | sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; |
| 454 | break; |
| 455 | case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ |
| 456 | sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; |
| 457 | break; |
| 458 | case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ |
| 459 | sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; |
| 460 | break; |
| 461 | case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ |
| 462 | sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; |
| 463 | break; |
| 464 | case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ |
| 465 | sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; |
| 466 | break; |
| 467 | case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ |
| 468 | sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; |
| 469 | break; |
| 470 | case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ |
| 471 | sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; |
| 472 | |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame] | 473 | /* call the CIMX entry at the last sb800 device, |
| 474 | * so make sure the mainboard devicetree is complete |
| 475 | */ |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 476 | #if CONFIG_HAVE_ACPI_RESUME |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 477 | if (acpi_slp_type != 3) |
| 478 | sb_Before_Pci_Init(); |
| 479 | else |
| 480 | sb_Before_Pci_Restore_Init(); |
| 481 | #else |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 482 | sb_Before_Pci_Init(); |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 483 | #endif |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 484 | break; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 485 | |
| 486 | default: |
| 487 | break; |
| 488 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 489 | } |
| 490 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 491 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 492 | CHIP_NAME("ATI SB800") |
| 493 | .enable_dev = sb800_enable, |
| 494 | }; |