commit 9bcdbf8eaa0c73d130ba555163f89fa1759c8c99
author zbao <fishbaozi@gmail.com> Thu Apr 05 13:18:49 2012 +0800
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Thu Apr 12 00:14:58 2012 +0200
tree c8d480f7e75444037a5ba491ea3987282e2faa21
parent 2c2e78d845cd28eb3b11c87fa3feafaf836cda7a

Add Southbridge support for S3.

1. Add some CIMX call for S3.
2. Detect sleep type.

Change-Id: I62888e8d8a03987ca88f5c935fa660f6b49a4fe9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/621
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/southbridge/amd/cimx/sb800/late.c

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 8c7abdb..c69782b 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -24,6 +24,7 @@
 #include <arch/ioapic.h>
 #include <device/smbus.h>	/* smbus_bus_operations */
 #include <console/console.h>	/* printk */
+#include <arch/acpi.h>
 #include "lpc.h"		/* lpc_read_resources */
 #include "SBPLATFORM.h" 	/* Platfrom Specific Definitions */
 #include "cfg.h"		/* sb800 Cimx configuration */
@@ -351,6 +352,17 @@
 	AmdSbDispatcher(sb_config);
 }
 
+void sb_Before_Pci_Restore_Init(void)
+{
+	sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT;
+	AmdSbDispatcher(sb_config);
+}
+
+void sb_After_Pci_Restore_Init(void)
+{
+	sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT;
+	AmdSbDispatcher(sb_config);
+}
 
 /**
  * @brief SB Cimx entry point sbBeforePciInit wrapper
@@ -468,7 +480,14 @@
 		/* call the CIMX entry at the last sb800 device,
 		 * so make sure the mainboard devicetree is complete
 		 */
+#if CONFIG_HAVE_ACPI_RESUME == 1
+		if (acpi_slp_type != 3)
+			sb_Before_Pci_Init();
+		else
+			sb_Before_Pci_Restore_Init();
+#else
 		sb_Before_Pci_Init();
+#endif
 		break;
 
 	default: