commit 3e706b63c03b4d1d64a21f4c26eaa12fc88cb1f8
author Kerry She <shekairui@gmail.com> Fri Jun 24 22:52:15 2011 +0800
committer Stefan Reinauer <stefan.reinauer@coreboot.org> Wed Jun 29 00:22:16 2011 +0200
tree 534b511aee308d98f3d1be3946ab1cd3383637a0
parent 770b877796c1b4632b00191458dbc153226c6bee

amd southbirdge sb800 wrapper, pci bridge fix

sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.

Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/southbridge/amd/cimx/sb800/late.c

diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 7367a18..b16bc50 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -248,6 +248,21 @@
         .device = PCI_DEVICE_ID_ATI_SB800_GEC,
 };
 
+/**
+ * @brief Enable PCI Bridge
+ *
+ * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
+ * 'PCIDisable' set to 0 to enable P2P bridge.
+ * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
+ *              to function as GPIO {GPIO 35:0}.
+ */
+static void pci_init(device_t dev)
+{
+	/* PCI Bridge SHOULD be enabled by default according to SB800 rrg,
+	 * but actually was disabled in some platform, so I have to enabled it.
+	 */
+	RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
+}
 
 static void pcie_init(device_t dev)
 {
@@ -258,7 +273,7 @@
         .read_resources = pci_bus_read_resources,
         .set_resources = pci_dev_set_resources,
         .enable_resources = pci_bus_enable_resources,
-        .init = pcie_init,
+        .init = pci_init,
         .scan_bus = pci_scan_bridge,
         .reset_bus = pci_bus_reset,
         .ops_pci = &lops_pci,