Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <device/device.h> /* device_t */ |
| 22 | #include <device/pci.h> /* device_operations */ |
| 23 | #include <device/pci_ids.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 24 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | #include <device/smbus.h> /* smbus_bus_operations */ |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 27 | #include <console/console.h> /* printk */ |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 29 | #include "lpc.h" /* lpc_read_resources */ |
| 30 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
| 31 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 32 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 33 | #include "sb_cimx.h" /* AMD CIMX wrapper entries */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 34 | #include "smbus.h" |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 35 | #include "fan.h" |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 36 | |
| 37 | /*implement in mainboard.c*/ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 38 | void set_pcie_reset(void); |
| 39 | void set_pcie_dereset(void); |
| 40 | |
| 41 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 42 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 43 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 44 | |
| 45 | |
| 46 | /** |
| 47 | * @brief Entry point of Southbridge CIMx callout |
| 48 | * |
| 49 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 50 | * |
| 51 | * @param[in] func Southbridge CIMx Function ID. |
| 52 | * @param[in] data Southbridge Input Data. |
| 53 | * @param[in] sb_config Southbridge configuration structure pointer. |
| 54 | * |
| 55 | */ |
| 56 | u32 sb800_callout_entry(u32 func, u32 data, void* config) |
| 57 | { |
| 58 | u32 ret = 0; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 59 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 60 | switch (func) { |
| 61 | case CB_SBGPP_RESET_ASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 62 | set_pcie_reset(); |
| 63 | break; |
| 64 | |
| 65 | case CB_SBGPP_RESET_DEASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 66 | set_pcie_dereset(); |
| 67 | break; |
| 68 | |
| 69 | case IMC_FIRMWARE_FAIL: |
| 70 | break; |
| 71 | |
| 72 | default: |
| 73 | break; |
| 74 | } |
| 75 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 76 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 77 | return ret; |
| 78 | } |
| 79 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 80 | #define HOST_CAP 0x00 /* host capabilities */ |
| 81 | #define HOST_CTL 0x04 /* global host control */ |
| 82 | #define HOST_IRQ_STAT 0x08 /* interrupt status */ |
| 83 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
| 84 | |
| 85 | #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ |
| 86 | static void ahci_raid_init(struct device *dev) |
| 87 | { |
| 88 | u8 irq = 0; |
| 89 | u32 bar5, caps, ports, val; |
| 90 | |
| 91 | val = pci_read_config16(dev, PCI_CLASS_DEVICE); |
| 92 | if (val == PCI_CLASS_STORAGE_SATA) { |
| 93 | printk(BIOS_DEBUG, "AHCI controller "); |
| 94 | } else if (val == PCI_CLASS_STORAGE_RAID) { |
| 95 | printk(BIOS_DEBUG, "RAID controller "); |
| 96 | } else { |
| 97 | printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); |
| 98 | return; |
| 99 | } |
| 100 | |
| 101 | irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); |
| 102 | bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 103 | printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); |
| 104 | |
| 105 | caps = *(volatile u32 *)(bar5 + HOST_CAP); |
| 106 | caps = (caps & 0x1F) + 1; |
| 107 | ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); |
| 108 | printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); |
| 109 | |
| 110 | /* make sure ahci is enabled */ |
| 111 | val = *(volatile u32 *)(bar5 + HOST_CTL); |
| 112 | if (!(val & HOST_CTL_AHCI_EN)) { |
| 113 | *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; |
| 114 | } |
| 115 | |
| 116 | dev->command |= PCI_COMMAND_MASTER; |
| 117 | pci_write_config8(dev, PCI_COMMAND, dev->command); |
| 118 | printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); |
| 119 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 120 | |
| 121 | static struct pci_operations lops_pci = { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 122 | .set_subsystem = pci_dev_set_subsystem, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 123 | }; |
| 124 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 125 | static void lpc_init(device_t dev) |
| 126 | { |
| 127 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); |
| 128 | |
| 129 | rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); |
| 130 | |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame^] | 131 | /* Initialize the real time clock. |
| 132 | * The 0 argument tells rtc_init not to |
| 133 | * update CMOS unless it is invalid. |
| 134 | * 1 tells rtc_init to always initialize the CMOS. |
| 135 | */ |
| 136 | rtc_init(0); |
| 137 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 138 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); |
| 139 | } |
| 140 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 141 | static struct device_operations lpc_ops = { |
| 142 | .read_resources = lpc_read_resources, |
| 143 | .set_resources = lpc_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 144 | .enable_resources = pci_dev_enable_resources, |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 145 | .init = lpc_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 146 | .scan_bus = scan_static_bus, |
| 147 | .ops_pci = &lops_pci, |
| 148 | }; |
| 149 | |
| 150 | static const struct pci_driver lpc_driver __pci_driver = { |
| 151 | .ops = &lpc_ops, |
| 152 | .vendor = PCI_VENDOR_ID_ATI, |
| 153 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
| 154 | }; |
| 155 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 156 | static struct device_operations sata_ops = { |
| 157 | .read_resources = pci_dev_read_resources, |
| 158 | .set_resources = pci_dev_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 159 | .enable_resources = pci_dev_enable_resources, |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 160 | .init = ahci_raid_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 161 | .scan_bus = 0, |
| 162 | .ops_pci = &lops_pci, |
| 163 | }; |
| 164 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 165 | static const struct pci_driver ahci_driver __pci_driver = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 166 | .ops = &sata_ops, |
| 167 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 168 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 169 | }; |
| 170 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 171 | static const struct pci_driver raid_driver __pci_driver = { |
| 172 | .ops = &sata_ops, |
| 173 | .vendor = PCI_VENDOR_ID_ATI, |
| 174 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, |
| 175 | }; |
| 176 | static const struct pci_driver raid5_driver __pci_driver = { |
| 177 | .ops = &sata_ops, |
| 178 | .vendor = PCI_VENDOR_ID_ATI, |
| 179 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, |
| 180 | }; |
| 181 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 182 | #if CONFIG_USBDEBUG |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 183 | static void usb_set_resources(struct device *dev) |
| 184 | { |
| 185 | struct resource *res; |
| 186 | u32 base; |
| 187 | u32 old_debug; |
| 188 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 190 | old_debug = get_ehci_debug(); |
| 191 | set_ehci_debug(0); |
| 192 | |
| 193 | pci_dev_set_resources(dev); |
| 194 | |
| 195 | res = find_resource(dev, 0x10); |
| 196 | set_ehci_debug(old_debug); |
| 197 | if (!res) |
| 198 | return; |
| 199 | base = res->base; |
| 200 | set_ehci_base(base); |
| 201 | report_resource_stored(dev, res, ""); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 202 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 203 | } |
| 204 | #endif |
| 205 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 206 | static struct device_operations usb_ops = { |
| 207 | .read_resources = pci_dev_read_resources, |
| 208 | #if CONFIG_USBDEBUG |
| 209 | .set_resources = usb_set_resources, |
| 210 | #else |
| 211 | .set_resources = pci_dev_set_resources, |
| 212 | #endif |
| 213 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 214 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 215 | .scan_bus = 0, |
| 216 | .ops_pci = &lops_pci, |
| 217 | }; |
| 218 | |
| 219 | /* |
| 220 | * The pci id of usb ctrl 0 and 1 are the same. |
| 221 | */ |
| 222 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 223 | .ops = &usb_ops, |
| 224 | .vendor = PCI_VENDOR_ID_ATI, |
| 225 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 226 | }; |
| 227 | |
| 228 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 229 | .ops = &usb_ops, |
| 230 | .vendor = PCI_VENDOR_ID_ATI, |
| 231 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 232 | }; |
| 233 | |
| 234 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 235 | .ops = &usb_ops, |
| 236 | .vendor = PCI_VENDOR_ID_ATI, |
| 237 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 238 | }; |
| 239 | |
| 240 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 241 | static struct device_operations azalia_ops = { |
| 242 | .read_resources = pci_dev_read_resources, |
| 243 | .set_resources = pci_dev_set_resources, |
| 244 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 245 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 246 | .scan_bus = 0, |
| 247 | .ops_pci = &lops_pci, |
| 248 | }; |
| 249 | |
| 250 | static const struct pci_driver azalia_driver __pci_driver = { |
| 251 | .ops = &azalia_ops, |
| 252 | .vendor = PCI_VENDOR_ID_ATI, |
| 253 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
| 254 | }; |
| 255 | |
| 256 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 257 | static struct device_operations gec_ops = { |
| 258 | .read_resources = pci_dev_read_resources, |
| 259 | .set_resources = pci_dev_set_resources, |
| 260 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 261 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 262 | .scan_bus = 0, |
| 263 | .ops_pci = &lops_pci, |
| 264 | }; |
| 265 | |
| 266 | static const struct pci_driver gec_driver __pci_driver = { |
| 267 | .ops = &gec_ops, |
| 268 | .vendor = PCI_VENDOR_ID_ATI, |
| 269 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
| 270 | }; |
| 271 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 272 | /** |
| 273 | * @brief Enable PCI Bridge |
| 274 | * |
| 275 | * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 276 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 277 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 278 | * to function as GPIO {GPIO 35:0}. |
| 279 | */ |
| 280 | static void pci_init(device_t dev) |
| 281 | { |
| 282 | /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, |
| 283 | * but actually was disabled in some platform, so I have to enabled it. |
| 284 | */ |
| 285 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 286 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 287 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 288 | |
| 289 | static struct device_operations pci_ops = { |
| 290 | .read_resources = pci_bus_read_resources, |
| 291 | .set_resources = pci_dev_set_resources, |
| 292 | .enable_resources = pci_bus_enable_resources, |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 293 | .init = pci_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 294 | .scan_bus = pci_scan_bridge, |
| 295 | .reset_bus = pci_bus_reset, |
| 296 | .ops_pci = &lops_pci, |
| 297 | }; |
| 298 | |
| 299 | static const struct pci_driver pci_driver __pci_driver = { |
| 300 | .ops = &pci_ops, |
| 301 | .vendor = PCI_VENDOR_ID_ATI, |
| 302 | .device = PCI_DEVICE_ID_ATI_SB800_PCI, |
| 303 | }; |
| 304 | |
| 305 | |
| 306 | struct device_operations bridge_ops = { |
| 307 | .read_resources = pci_bus_read_resources, |
| 308 | .set_resources = pci_dev_set_resources, |
| 309 | .enable_resources = pci_bus_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 310 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 311 | .scan_bus = pci_scan_bridge, |
| 312 | .enable = 0, |
| 313 | .reset_bus = pci_bus_reset, |
| 314 | .ops_pci = &lops_pci, |
| 315 | }; |
| 316 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 317 | /** |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 318 | * South Bridge CIMx ramstage entry point wrapper. |
| 319 | */ |
| 320 | void sb_Before_Pci_Init(void) |
| 321 | { |
| 322 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 323 | AmdSbDispatcher(sb_config); |
| 324 | } |
| 325 | |
| 326 | void sb_After_Pci_Init(void) |
| 327 | { |
| 328 | sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; |
| 329 | AmdSbDispatcher(sb_config); |
| 330 | } |
| 331 | |
| 332 | void sb_Mid_Post_Init(void) |
| 333 | { |
| 334 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 335 | AmdSbDispatcher(sb_config); |
| 336 | } |
| 337 | |
| 338 | void sb_Late_Post(void) |
| 339 | { |
| 340 | sb_config->StdHeader.Func = SB_LATE_POST_INIT; |
| 341 | AmdSbDispatcher(sb_config); |
| 342 | } |
| 343 | |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 344 | void sb_Before_Pci_Restore_Init(void) |
| 345 | { |
| 346 | sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; |
| 347 | AmdSbDispatcher(sb_config); |
| 348 | } |
| 349 | |
| 350 | void sb_After_Pci_Restore_Init(void) |
| 351 | { |
| 352 | sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; |
| 353 | AmdSbDispatcher(sb_config); |
| 354 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 355 | |
| 356 | /** |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 357 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 358 | */ |
| 359 | static void sb800_enable(device_t dev) |
| 360 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 361 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 362 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 363 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 364 | printk(BIOS_DEBUG, "sb800_enable() "); |
| 365 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 366 | switch (dev->path.pci.devfn) { |
| 367 | case (0x11 << 3) | 0: /* 0:11.0 SATA */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 368 | /* the first sb800 device */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 369 | switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ |
| 370 | case GPP_CFGMODE_X2200: |
| 371 | abcfg_reg(0xc0, 0x01FF, 0x030); /* x2 Port_0, x2 Port_1 */ |
| 372 | break; |
| 373 | case GPP_CFGMODE_X2110: |
| 374 | abcfg_reg(0xc0, 0x01FF, 0x070); /* x2 Port_0, x1 Port_1&2 */ |
| 375 | break; |
| 376 | case GPP_CFGMODE_X1111: |
| 377 | abcfg_reg(0xc0, 0x01FF, 0x0F0); /* x1 Port_0&1&2&3 */ |
| 378 | break; |
| 379 | case GPP_CFGMODE_X4000: |
| 380 | default: |
| 381 | abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ |
| 382 | break; |
| 383 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 384 | sb800_cimx_config(sb_config); |
| 385 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 386 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 387 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 388 | if (1 == sb_chip->boot_switch_sata_ide) |
| 389 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 390 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 391 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 392 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 393 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 394 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 395 | break; |
| 396 | |
| 397 | case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 398 | printk(BIOS_INFO, "sm_init().\n"); |
| 399 | clear_ioapic(IO_APIC_ADDR); |
| 400 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 401 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 402 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 403 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
| 404 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
| 405 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
| 406 | setup_ioapic(IO_APIC_ADDR, 0); |
| 407 | #else |
| 408 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 409 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 410 | break; |
| 411 | |
| 412 | case (0x14 << 3) | 1: /* 0:14:1 IDE */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 413 | break; |
| 414 | |
| 415 | case (0x14 << 3) | 2: /* 0:14:2 HDA */ |
| 416 | if (dev->enabled) { |
| 417 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 418 | sb_config->AzaliaController = AZALIA_AUTO; |
| 419 | } |
| 420 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 421 | } else { |
| 422 | sb_config->AzaliaController = AZALIA_DISABLE; |
| 423 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 424 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 425 | break; |
| 426 | |
| 427 | |
| 428 | case (0x14 << 3) | 3: /* 0:14:3 LPC */ |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 429 | /* Initialize the fans */ |
| 430 | #if CONFIG_SB800_IMC_FAN_CONTROL |
| 431 | init_sb800_IMC_fans(dev); |
| 432 | #elif CONFIG_SB800_MANUAL_FAN_CONTROL |
| 433 | init_sb800_MANUAL_fans(dev); |
| 434 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 435 | break; |
| 436 | |
| 437 | case (0x14 << 3) | 4: /* 0:14:4 PCI */ |
| 438 | break; |
| 439 | |
| 440 | case (0x14 << 3) | 6: /* 0:14:6 GEC */ |
| 441 | if (dev->enabled) { |
| 442 | sb_config->GecConfig = 0; |
| 443 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 444 | } else { |
| 445 | sb_config->GecConfig = 1; |
| 446 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 447 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 448 | break; |
| 449 | |
| 450 | case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 451 | { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 452 | device_t device; |
| 453 | for (device = dev; device; device = device->next) { |
| 454 | if (dev->path.type != DEVICE_PATH_PCI) continue; |
| 455 | if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; |
| 456 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 457 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 458 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 459 | /* |
| 460 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 461 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 462 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 463 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 464 | */ |
| 465 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 466 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 467 | break; |
| 468 | |
| 469 | case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ |
| 470 | sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; |
| 471 | break; |
| 472 | case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ |
| 473 | sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; |
| 474 | break; |
| 475 | case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ |
| 476 | sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; |
| 477 | break; |
| 478 | case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ |
| 479 | sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; |
| 480 | break; |
| 481 | case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ |
| 482 | sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; |
| 483 | break; |
| 484 | case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ |
| 485 | sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; |
| 486 | break; |
| 487 | case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ |
| 488 | sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; |
| 489 | |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame] | 490 | /* call the CIMX entry at the last sb800 device, |
| 491 | * so make sure the mainboard devicetree is complete |
| 492 | */ |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 493 | #if CONFIG_HAVE_ACPI_RESUME |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 494 | if (acpi_slp_type != 3) |
| 495 | sb_Before_Pci_Init(); |
| 496 | else |
| 497 | sb_Before_Pci_Restore_Init(); |
| 498 | #else |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 499 | sb_Before_Pci_Init(); |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 500 | #endif |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 501 | break; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 502 | |
| 503 | default: |
| 504 | break; |
| 505 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 506 | } |
| 507 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 508 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 509 | CHIP_NAME("ATI SB800") |
| 510 | .enable_dev = sb800_enable, |
| 511 | }; |