Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <device/device.h> /* device_t */ |
| 22 | #include <device/pci.h> /* device_operations */ |
| 23 | #include <device/pci_ids.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 24 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | #include <device/smbus.h> /* smbus_bus_operations */ |
| 26 | #include <console/console.h> /* printk */ |
| 27 | #include "lpc.h" /* lpc_read_resources */ |
| 28 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
| 29 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 30 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 31 | #include "sb_cimx.h" /* AMD CIMX wrapper entries */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 32 | |
| 33 | |
| 34 | /*implement in mainboard.c*/ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 35 | void set_pcie_reset(void); |
| 36 | void set_pcie_dereset(void); |
| 37 | |
| 38 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 39 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 40 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 41 | |
| 42 | |
| 43 | /** |
| 44 | * @brief Entry point of Southbridge CIMx callout |
| 45 | * |
| 46 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 47 | * |
| 48 | * @param[in] func Southbridge CIMx Function ID. |
| 49 | * @param[in] data Southbridge Input Data. |
| 50 | * @param[in] sb_config Southbridge configuration structure pointer. |
| 51 | * |
| 52 | */ |
| 53 | u32 sb800_callout_entry(u32 func, u32 data, void* config) |
| 54 | { |
| 55 | u32 ret = 0; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 56 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 57 | switch (func) { |
| 58 | case CB_SBGPP_RESET_ASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 59 | set_pcie_reset(); |
| 60 | break; |
| 61 | |
| 62 | case CB_SBGPP_RESET_DEASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 63 | set_pcie_dereset(); |
| 64 | break; |
| 65 | |
| 66 | case IMC_FIRMWARE_FAIL: |
| 67 | break; |
| 68 | |
| 69 | default: |
| 70 | break; |
| 71 | } |
| 72 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 73 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 74 | return ret; |
| 75 | } |
| 76 | |
| 77 | |
| 78 | static struct pci_operations lops_pci = { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 79 | .set_subsystem = pci_dev_set_subsystem, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 80 | }; |
| 81 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 82 | static struct device_operations lpc_ops = { |
| 83 | .read_resources = lpc_read_resources, |
| 84 | .set_resources = lpc_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 85 | .enable_resources = pci_dev_enable_resources, |
| 86 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 87 | .scan_bus = scan_static_bus, |
| 88 | .ops_pci = &lops_pci, |
| 89 | }; |
| 90 | |
| 91 | static const struct pci_driver lpc_driver __pci_driver = { |
| 92 | .ops = &lpc_ops, |
| 93 | .vendor = PCI_VENDOR_ID_ATI, |
| 94 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
| 95 | }; |
| 96 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 97 | static struct device_operations sata_ops = { |
| 98 | .read_resources = pci_dev_read_resources, |
| 99 | .set_resources = pci_dev_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 100 | .enable_resources = pci_dev_enable_resources, |
| 101 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 102 | .scan_bus = 0, |
| 103 | .ops_pci = &lops_pci, |
| 104 | }; |
| 105 | |
| 106 | static const struct pci_driver sata_driver __pci_driver = { |
| 107 | .ops = &sata_ops, |
| 108 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 109 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 110 | }; |
| 111 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 112 | #if CONFIG_USBDEBUG == 1 |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 113 | static void usb_set_resources(struct device *dev) |
| 114 | { |
| 115 | struct resource *res; |
| 116 | u32 base; |
| 117 | u32 old_debug; |
| 118 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 119 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 120 | old_debug = get_ehci_debug(); |
| 121 | set_ehci_debug(0); |
| 122 | |
| 123 | pci_dev_set_resources(dev); |
| 124 | |
| 125 | res = find_resource(dev, 0x10); |
| 126 | set_ehci_debug(old_debug); |
| 127 | if (!res) |
| 128 | return; |
| 129 | base = res->base; |
| 130 | set_ehci_base(base); |
| 131 | report_resource_stored(dev, res, ""); |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 132 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 133 | } |
| 134 | #endif |
| 135 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 136 | static struct device_operations usb_ops = { |
| 137 | .read_resources = pci_dev_read_resources, |
| 138 | #if CONFIG_USBDEBUG |
| 139 | .set_resources = usb_set_resources, |
| 140 | #else |
| 141 | .set_resources = pci_dev_set_resources, |
| 142 | #endif |
| 143 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 144 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 145 | .scan_bus = 0, |
| 146 | .ops_pci = &lops_pci, |
| 147 | }; |
| 148 | |
| 149 | /* |
| 150 | * The pci id of usb ctrl 0 and 1 are the same. |
| 151 | */ |
| 152 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 153 | .ops = &usb_ops, |
| 154 | .vendor = PCI_VENDOR_ID_ATI, |
| 155 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 156 | }; |
| 157 | |
| 158 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 159 | .ops = &usb_ops, |
| 160 | .vendor = PCI_VENDOR_ID_ATI, |
| 161 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 162 | }; |
| 163 | |
| 164 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 165 | .ops = &usb_ops, |
| 166 | .vendor = PCI_VENDOR_ID_ATI, |
| 167 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 168 | }; |
| 169 | |
| 170 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 171 | static struct device_operations azalia_ops = { |
| 172 | .read_resources = pci_dev_read_resources, |
| 173 | .set_resources = pci_dev_set_resources, |
| 174 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 175 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 176 | .scan_bus = 0, |
| 177 | .ops_pci = &lops_pci, |
| 178 | }; |
| 179 | |
| 180 | static const struct pci_driver azalia_driver __pci_driver = { |
| 181 | .ops = &azalia_ops, |
| 182 | .vendor = PCI_VENDOR_ID_ATI, |
| 183 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
| 184 | }; |
| 185 | |
| 186 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 187 | static struct device_operations gec_ops = { |
| 188 | .read_resources = pci_dev_read_resources, |
| 189 | .set_resources = pci_dev_set_resources, |
| 190 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 191 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 192 | .scan_bus = 0, |
| 193 | .ops_pci = &lops_pci, |
| 194 | }; |
| 195 | |
| 196 | static const struct pci_driver gec_driver __pci_driver = { |
| 197 | .ops = &gec_ops, |
| 198 | .vendor = PCI_VENDOR_ID_ATI, |
| 199 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
| 200 | }; |
| 201 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 202 | /** |
| 203 | * @brief Enable PCI Bridge |
| 204 | * |
| 205 | * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 206 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 207 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 208 | * to function as GPIO {GPIO 35:0}. |
| 209 | */ |
| 210 | static void pci_init(device_t dev) |
| 211 | { |
| 212 | /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, |
| 213 | * but actually was disabled in some platform, so I have to enabled it. |
| 214 | */ |
| 215 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 216 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 217 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 218 | |
| 219 | static struct device_operations pci_ops = { |
| 220 | .read_resources = pci_bus_read_resources, |
| 221 | .set_resources = pci_dev_set_resources, |
| 222 | .enable_resources = pci_bus_enable_resources, |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 223 | .init = pci_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 224 | .scan_bus = pci_scan_bridge, |
| 225 | .reset_bus = pci_bus_reset, |
| 226 | .ops_pci = &lops_pci, |
| 227 | }; |
| 228 | |
| 229 | static const struct pci_driver pci_driver __pci_driver = { |
| 230 | .ops = &pci_ops, |
| 231 | .vendor = PCI_VENDOR_ID_ATI, |
| 232 | .device = PCI_DEVICE_ID_ATI_SB800_PCI, |
| 233 | }; |
| 234 | |
| 235 | |
| 236 | struct device_operations bridge_ops = { |
| 237 | .read_resources = pci_bus_read_resources, |
| 238 | .set_resources = pci_dev_set_resources, |
| 239 | .enable_resources = pci_bus_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 240 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 241 | .scan_bus = pci_scan_bridge, |
| 242 | .enable = 0, |
| 243 | .reset_bus = pci_bus_reset, |
| 244 | .ops_pci = &lops_pci, |
| 245 | }; |
| 246 | |
| 247 | /* 0:15:0 PCIe PortA */ |
| 248 | static const struct pci_driver PORTA_driver __pci_driver = { |
| 249 | .ops = &bridge_ops, |
| 250 | .vendor = PCI_VENDOR_ID_ATI, |
| 251 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEA, |
| 252 | }; |
| 253 | |
| 254 | /* 0:15:1 PCIe PortB */ |
| 255 | static const struct pci_driver PORTB_driver __pci_driver = { |
| 256 | .ops = &bridge_ops, |
| 257 | .vendor = PCI_VENDOR_ID_ATI, |
| 258 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEB, |
| 259 | }; |
| 260 | |
| 261 | /* 0:15:2 PCIe PortC */ |
| 262 | static const struct pci_driver PORTC_driver __pci_driver = { |
| 263 | .ops = &bridge_ops, |
| 264 | .vendor = PCI_VENDOR_ID_ATI, |
| 265 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEC, |
| 266 | }; |
| 267 | |
| 268 | /* 0:15:3 PCIe PortD */ |
| 269 | static const struct pci_driver PORTD_driver __pci_driver = { |
| 270 | .ops = &bridge_ops, |
| 271 | .vendor = PCI_VENDOR_ID_ATI, |
| 272 | .device = PCI_DEVICE_ID_ATI_SB800_PCIED, |
| 273 | }; |
| 274 | |
| 275 | |
| 276 | /** |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 277 | * South Bridge CIMx ramstage entry point wrapper. |
| 278 | */ |
| 279 | void sb_Before_Pci_Init(void) |
| 280 | { |
| 281 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 282 | AmdSbDispatcher(sb_config); |
| 283 | } |
| 284 | |
| 285 | void sb_After_Pci_Init(void) |
| 286 | { |
| 287 | sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; |
| 288 | AmdSbDispatcher(sb_config); |
| 289 | } |
| 290 | |
| 291 | void sb_Mid_Post_Init(void) |
| 292 | { |
| 293 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 294 | AmdSbDispatcher(sb_config); |
| 295 | } |
| 296 | |
| 297 | void sb_Late_Post(void) |
| 298 | { |
| 299 | sb_config->StdHeader.Func = SB_LATE_POST_INIT; |
| 300 | AmdSbDispatcher(sb_config); |
| 301 | } |
| 302 | |
| 303 | |
| 304 | /** |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 305 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 306 | */ |
| 307 | static void sb800_enable(device_t dev) |
| 308 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 309 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 310 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 311 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 312 | printk(BIOS_DEBUG, "sb800_enable() "); |
| 313 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 314 | switch (dev->path.pci.devfn) { |
| 315 | case (0x11 << 3) | 0: /* 0:11.0 SATA */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 316 | /* the first sb800 device */ |
| 317 | sb800_cimx_config(sb_config); |
| 318 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 319 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 320 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 321 | if (1 == sb_chip->boot_switch_sata_ide) |
| 322 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 323 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 324 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 325 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 326 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 327 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 328 | break; |
| 329 | |
| 330 | case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 331 | printk(BIOS_INFO, "sm_init().\n"); |
| 332 | clear_ioapic(IO_APIC_ADDR); |
| 333 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 334 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 335 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 336 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
| 337 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
| 338 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
| 339 | setup_ioapic(IO_APIC_ADDR, 0); |
| 340 | #else |
| 341 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 342 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 343 | break; |
| 344 | |
| 345 | case (0x14 << 3) | 1: /* 0:14:1 IDE */ |
| 346 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 347 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 348 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 349 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 350 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 351 | break; |
| 352 | |
| 353 | case (0x14 << 3) | 2: /* 0:14:2 HDA */ |
| 354 | if (dev->enabled) { |
| 355 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 356 | sb_config->AzaliaController = AZALIA_AUTO; |
| 357 | } |
| 358 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 359 | } else { |
| 360 | sb_config->AzaliaController = AZALIA_DISABLE; |
| 361 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 362 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 363 | break; |
| 364 | |
| 365 | |
| 366 | case (0x14 << 3) | 3: /* 0:14:3 LPC */ |
| 367 | break; |
| 368 | |
| 369 | case (0x14 << 3) | 4: /* 0:14:4 PCI */ |
| 370 | break; |
| 371 | |
| 372 | case (0x14 << 3) | 6: /* 0:14:6 GEC */ |
| 373 | if (dev->enabled) { |
| 374 | sb_config->GecConfig = 0; |
| 375 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 376 | } else { |
| 377 | sb_config->GecConfig = 1; |
| 378 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 379 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 380 | break; |
| 381 | |
| 382 | case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 383 | { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 384 | device_t device; |
| 385 | for (device = dev; device; device = device->next) { |
| 386 | if (dev->path.type != DEVICE_PATH_PCI) continue; |
| 387 | if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; |
| 388 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 389 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 390 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 391 | /* |
| 392 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 393 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 394 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 395 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 396 | */ |
| 397 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 398 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 399 | break; |
| 400 | |
| 401 | case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ |
| 402 | sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; |
| 403 | break; |
| 404 | case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ |
| 405 | sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; |
| 406 | break; |
| 407 | case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ |
| 408 | sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; |
| 409 | break; |
| 410 | case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ |
| 411 | sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; |
| 412 | break; |
| 413 | case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ |
| 414 | sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; |
| 415 | break; |
| 416 | case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ |
| 417 | sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; |
| 418 | break; |
| 419 | case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ |
| 420 | sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; |
| 421 | |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame^] | 422 | /* call the CIMX entry at the last sb800 device, |
| 423 | * so make sure the mainboard devicetree is complete |
| 424 | */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 425 | sb_Before_Pci_Init(); |
| 426 | break; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 427 | |
| 428 | default: |
| 429 | break; |
| 430 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 431 | } |
| 432 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 433 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 434 | CHIP_NAME("ATI SB800") |
| 435 | .enable_dev = sb800_enable, |
| 436 | }; |