Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <device/device.h> /* device_t */ |
| 22 | #include <device/pci.h> /* device_operations */ |
| 23 | #include <device/pci_ids.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 24 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | #include <device/smbus.h> /* smbus_bus_operations */ |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 26 | #include <pc80/mc146818rtc.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 27 | #include <console/console.h> /* printk */ |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame^] | 29 | #include <usbdebug.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 30 | #include "lpc.h" /* lpc_read_resources */ |
| 31 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
| 32 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 33 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 34 | #include "sb_cimx.h" /* AMD CIMX wrapper entries */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 35 | #include "smbus.h" |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 36 | #include "fan.h" |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 37 | |
| 38 | /*implement in mainboard.c*/ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 39 | void set_pcie_reset(void); |
| 40 | void set_pcie_dereset(void); |
| 41 | |
| 42 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 43 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 44 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 45 | |
| 46 | |
| 47 | /** |
| 48 | * @brief Entry point of Southbridge CIMx callout |
| 49 | * |
| 50 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 51 | * |
| 52 | * @param[in] func Southbridge CIMx Function ID. |
| 53 | * @param[in] data Southbridge Input Data. |
| 54 | * @param[in] sb_config Southbridge configuration structure pointer. |
| 55 | * |
| 56 | */ |
| 57 | u32 sb800_callout_entry(u32 func, u32 data, void* config) |
| 58 | { |
| 59 | u32 ret = 0; |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 60 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - Start.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 61 | switch (func) { |
| 62 | case CB_SBGPP_RESET_ASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 63 | set_pcie_reset(); |
| 64 | break; |
| 65 | |
| 66 | case CB_SBGPP_RESET_DEASSERT: |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 67 | set_pcie_dereset(); |
| 68 | break; |
| 69 | |
| 70 | case IMC_FIRMWARE_FAIL: |
| 71 | break; |
| 72 | |
| 73 | default: |
| 74 | break; |
| 75 | } |
| 76 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 77 | printk(BIOS_DEBUG, "SB800 - Late.c - %s - End.\n", __func__); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 78 | return ret; |
| 79 | } |
| 80 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 81 | #define HOST_CAP 0x00 /* host capabilities */ |
| 82 | #define HOST_CTL 0x04 /* global host control */ |
| 83 | #define HOST_IRQ_STAT 0x08 /* interrupt status */ |
| 84 | #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */ |
| 85 | |
| 86 | #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */ |
| 87 | static void ahci_raid_init(struct device *dev) |
| 88 | { |
| 89 | u8 irq = 0; |
| 90 | u32 bar5, caps, ports, val; |
| 91 | |
| 92 | val = pci_read_config16(dev, PCI_CLASS_DEVICE); |
| 93 | if (val == PCI_CLASS_STORAGE_SATA) { |
| 94 | printk(BIOS_DEBUG, "AHCI controller "); |
| 95 | } else if (val == PCI_CLASS_STORAGE_RAID) { |
| 96 | printk(BIOS_DEBUG, "RAID controller "); |
| 97 | } else { |
| 98 | printk(BIOS_WARNING, "device class:%x, neither in ahci or raid mode\n", val); |
| 99 | return; |
| 100 | } |
| 101 | |
| 102 | irq = pci_read_config8(dev, PCI_INTERRUPT_LINE); |
| 103 | bar5 = pci_read_config32(dev, PCI_BASE_ADDRESS_5); |
| 104 | printk(BIOS_DEBUG, "IOMEM base: 0x%X, IRQ: 0x%X\n", bar5, irq); |
| 105 | |
| 106 | caps = *(volatile u32 *)(bar5 + HOST_CAP); |
| 107 | caps = (caps & 0x1F) + 1; |
| 108 | ports= *(volatile u32 *)(bar5 + HOST_PORTS_IMPL); |
| 109 | printk(BIOS_DEBUG, "Number of Ports: 0x%x, Port implemented(bit map): 0x%x\n", caps, ports); |
| 110 | |
| 111 | /* make sure ahci is enabled */ |
| 112 | val = *(volatile u32 *)(bar5 + HOST_CTL); |
| 113 | if (!(val & HOST_CTL_AHCI_EN)) { |
| 114 | *(volatile u32 *)(bar5 + HOST_CTL) = val | HOST_CTL_AHCI_EN; |
| 115 | } |
| 116 | |
| 117 | dev->command |= PCI_COMMAND_MASTER; |
| 118 | pci_write_config8(dev, PCI_COMMAND, dev->command); |
| 119 | printk(BIOS_DEBUG, "AHCI/RAID controller initialized\n"); |
| 120 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 121 | |
| 122 | static struct pci_operations lops_pci = { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 123 | .set_subsystem = pci_dev_set_subsystem, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 124 | }; |
| 125 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 126 | static void lpc_init(device_t dev) |
| 127 | { |
| 128 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n"); |
| 129 | |
| 130 | rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); |
| 131 | |
Mike Loptien | ac529b1 | 2013-02-22 13:18:31 -0700 | [diff] [blame] | 132 | /* Initialize the real time clock. |
| 133 | * The 0 argument tells rtc_init not to |
| 134 | * update CMOS unless it is invalid. |
| 135 | * 1 tells rtc_init to always initialize the CMOS. |
| 136 | */ |
| 137 | rtc_init(0); |
| 138 | |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 139 | printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); |
| 140 | } |
| 141 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 142 | static struct device_operations lpc_ops = { |
| 143 | .read_resources = lpc_read_resources, |
| 144 | .set_resources = lpc_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 145 | .enable_resources = pci_dev_enable_resources, |
zbao | 366f0fc | 2012-08-03 16:58:53 +0800 | [diff] [blame] | 146 | .init = lpc_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 147 | .scan_bus = scan_static_bus, |
| 148 | .ops_pci = &lops_pci, |
| 149 | }; |
| 150 | |
| 151 | static const struct pci_driver lpc_driver __pci_driver = { |
| 152 | .ops = &lpc_ops, |
| 153 | .vendor = PCI_VENDOR_ID_ATI, |
| 154 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
| 155 | }; |
| 156 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 157 | static struct device_operations sata_ops = { |
| 158 | .read_resources = pci_dev_read_resources, |
| 159 | .set_resources = pci_dev_set_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 160 | .enable_resources = pci_dev_enable_resources, |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 161 | .init = ahci_raid_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 162 | .scan_bus = 0, |
| 163 | .ops_pci = &lops_pci, |
| 164 | }; |
| 165 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 166 | static const struct pci_driver ahci_driver __pci_driver = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 167 | .ops = &sata_ops, |
| 168 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 169 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 170 | }; |
| 171 | |
Kerry Sheh | 0e6344e | 2011-10-12 11:42:59 +0800 | [diff] [blame] | 172 | static const struct pci_driver raid_driver __pci_driver = { |
| 173 | .ops = &sata_ops, |
| 174 | .vendor = PCI_VENDOR_ID_ATI, |
| 175 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID, |
| 176 | }; |
| 177 | static const struct pci_driver raid5_driver __pci_driver = { |
| 178 | .ops = &sata_ops, |
| 179 | .vendor = PCI_VENDOR_ID_ATI, |
| 180 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_RAID5, |
| 181 | }; |
| 182 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 183 | static struct device_operations usb_ops = { |
Kyösti Mälkki | fb387df | 2013-06-07 22:16:52 +0300 | [diff] [blame^] | 184 | .read_resources = pci_ehci_read_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 185 | .set_resources = pci_dev_set_resources, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 186 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 187 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 188 | .scan_bus = 0, |
| 189 | .ops_pci = &lops_pci, |
| 190 | }; |
| 191 | |
| 192 | /* |
| 193 | * The pci id of usb ctrl 0 and 1 are the same. |
| 194 | */ |
| 195 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 196 | .ops = &usb_ops, |
| 197 | .vendor = PCI_VENDOR_ID_ATI, |
| 198 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 199 | }; |
| 200 | |
| 201 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 202 | .ops = &usb_ops, |
| 203 | .vendor = PCI_VENDOR_ID_ATI, |
| 204 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 205 | }; |
| 206 | |
| 207 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 208 | .ops = &usb_ops, |
| 209 | .vendor = PCI_VENDOR_ID_ATI, |
| 210 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 211 | }; |
| 212 | |
| 213 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 214 | static struct device_operations azalia_ops = { |
| 215 | .read_resources = pci_dev_read_resources, |
| 216 | .set_resources = pci_dev_set_resources, |
| 217 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 218 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 219 | .scan_bus = 0, |
| 220 | .ops_pci = &lops_pci, |
| 221 | }; |
| 222 | |
| 223 | static const struct pci_driver azalia_driver __pci_driver = { |
| 224 | .ops = &azalia_ops, |
| 225 | .vendor = PCI_VENDOR_ID_ATI, |
| 226 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
| 227 | }; |
| 228 | |
| 229 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 230 | static struct device_operations gec_ops = { |
| 231 | .read_resources = pci_dev_read_resources, |
| 232 | .set_resources = pci_dev_set_resources, |
| 233 | .enable_resources = pci_dev_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 234 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 235 | .scan_bus = 0, |
| 236 | .ops_pci = &lops_pci, |
| 237 | }; |
| 238 | |
| 239 | static const struct pci_driver gec_driver __pci_driver = { |
| 240 | .ops = &gec_ops, |
| 241 | .vendor = PCI_VENDOR_ID_ATI, |
| 242 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
| 243 | }; |
| 244 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 245 | /** |
| 246 | * @brief Enable PCI Bridge |
| 247 | * |
| 248 | * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 249 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 250 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 251 | * to function as GPIO {GPIO 35:0}. |
| 252 | */ |
| 253 | static void pci_init(device_t dev) |
| 254 | { |
| 255 | /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, |
| 256 | * but actually was disabled in some platform, so I have to enabled it. |
| 257 | */ |
| 258 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 259 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 260 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 261 | |
| 262 | static struct device_operations pci_ops = { |
| 263 | .read_resources = pci_bus_read_resources, |
| 264 | .set_resources = pci_dev_set_resources, |
| 265 | .enable_resources = pci_bus_enable_resources, |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame] | 266 | .init = pci_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 267 | .scan_bus = pci_scan_bridge, |
| 268 | .reset_bus = pci_bus_reset, |
| 269 | .ops_pci = &lops_pci, |
| 270 | }; |
| 271 | |
| 272 | static const struct pci_driver pci_driver __pci_driver = { |
| 273 | .ops = &pci_ops, |
| 274 | .vendor = PCI_VENDOR_ID_ATI, |
| 275 | .device = PCI_DEVICE_ID_ATI_SB800_PCI, |
| 276 | }; |
| 277 | |
| 278 | |
| 279 | struct device_operations bridge_ops = { |
| 280 | .read_resources = pci_bus_read_resources, |
| 281 | .set_resources = pci_dev_set_resources, |
| 282 | .enable_resources = pci_bus_enable_resources, |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 283 | .init = 0, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 284 | .scan_bus = pci_scan_bridge, |
| 285 | .enable = 0, |
| 286 | .reset_bus = pci_bus_reset, |
| 287 | .ops_pci = &lops_pci, |
| 288 | }; |
| 289 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 290 | /** |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 291 | * South Bridge CIMx ramstage entry point wrapper. |
| 292 | */ |
| 293 | void sb_Before_Pci_Init(void) |
| 294 | { |
| 295 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 296 | AmdSbDispatcher(sb_config); |
| 297 | } |
| 298 | |
| 299 | void sb_After_Pci_Init(void) |
| 300 | { |
| 301 | sb_config->StdHeader.Func = SB_AFTER_PCI_INIT; |
| 302 | AmdSbDispatcher(sb_config); |
| 303 | } |
| 304 | |
| 305 | void sb_Mid_Post_Init(void) |
| 306 | { |
| 307 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 308 | AmdSbDispatcher(sb_config); |
| 309 | } |
| 310 | |
| 311 | void sb_Late_Post(void) |
| 312 | { |
| 313 | sb_config->StdHeader.Func = SB_LATE_POST_INIT; |
| 314 | AmdSbDispatcher(sb_config); |
| 315 | } |
| 316 | |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 317 | void sb_Before_Pci_Restore_Init(void) |
| 318 | { |
| 319 | sb_config->StdHeader.Func = SB_BEFORE_PCI_RESTORE_INIT; |
| 320 | AmdSbDispatcher(sb_config); |
| 321 | } |
| 322 | |
| 323 | void sb_After_Pci_Restore_Init(void) |
| 324 | { |
| 325 | sb_config->StdHeader.Func = SB_AFTER_PCI_RESTORE_INIT; |
| 326 | AmdSbDispatcher(sb_config); |
| 327 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 328 | |
| 329 | /** |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 330 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 331 | */ |
| 332 | static void sb800_enable(device_t dev) |
| 333 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 334 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 335 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 336 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 337 | printk(BIOS_DEBUG, "sb800_enable() "); |
| 338 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 339 | switch (dev->path.pci.devfn) { |
| 340 | case (0x11 << 3) | 0: /* 0:11.0 SATA */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 341 | /* the first sb800 device */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 342 | switch (GPP_CFGMODE) { /* config the GPP PCIe ports */ |
| 343 | case GPP_CFGMODE_X2200: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 344 | abcfg_reg(0xc0, 0x01FF, 0x032); /* x2 Port_0, x2 Port_1 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 345 | break; |
| 346 | case GPP_CFGMODE_X2110: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 347 | abcfg_reg(0xc0, 0x01FF, 0x073); /* x2 Port_0, x1 Port_1&2 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 348 | break; |
| 349 | case GPP_CFGMODE_X1111: |
Dave Frodin | 8a6f7a7 | 2013-04-17 18:21:09 -0600 | [diff] [blame] | 350 | abcfg_reg(0xc0, 0x01FF, 0x0F4); /* x1 Port_0&1&2&3 */ |
Dave Frodin | 23023a5 | 2012-11-13 07:09:12 -0700 | [diff] [blame] | 351 | break; |
| 352 | case GPP_CFGMODE_X4000: |
| 353 | default: |
| 354 | abcfg_reg(0xc0, 0x01FF, 0x010); /* x4 Port_0 */ |
| 355 | break; |
| 356 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 357 | sb800_cimx_config(sb_config); |
| 358 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 359 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 360 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 361 | if (1 == sb_chip->boot_switch_sata_ide) |
| 362 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 363 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 364 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 365 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 366 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 367 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 368 | break; |
| 369 | |
| 370 | case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 371 | printk(BIOS_INFO, "sm_init().\n"); |
| 372 | clear_ioapic(IO_APIC_ADDR); |
| 373 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 374 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 375 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 376 | setup_ioapic(IO_APIC_ADDR, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
| 377 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
| 378 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
| 379 | setup_ioapic(IO_APIC_ADDR, 0); |
| 380 | #else |
| 381 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 382 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 383 | break; |
| 384 | |
| 385 | case (0x14 << 3) | 1: /* 0:14:1 IDE */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 386 | break; |
| 387 | |
| 388 | case (0x14 << 3) | 2: /* 0:14:2 HDA */ |
| 389 | if (dev->enabled) { |
| 390 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 391 | sb_config->AzaliaController = AZALIA_AUTO; |
| 392 | } |
| 393 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 394 | } else { |
| 395 | sb_config->AzaliaController = AZALIA_DISABLE; |
| 396 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 397 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 398 | break; |
| 399 | |
| 400 | |
| 401 | case (0x14 << 3) | 3: /* 0:14:3 LPC */ |
Martin Roth | e899e51 | 2012-12-05 16:07:11 -0700 | [diff] [blame] | 402 | /* Initialize the fans */ |
| 403 | #if CONFIG_SB800_IMC_FAN_CONTROL |
| 404 | init_sb800_IMC_fans(dev); |
| 405 | #elif CONFIG_SB800_MANUAL_FAN_CONTROL |
| 406 | init_sb800_MANUAL_fans(dev); |
| 407 | #endif |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 408 | break; |
| 409 | |
| 410 | case (0x14 << 3) | 4: /* 0:14:4 PCI */ |
| 411 | break; |
| 412 | |
| 413 | case (0x14 << 3) | 6: /* 0:14:6 GEC */ |
| 414 | if (dev->enabled) { |
| 415 | sb_config->GecConfig = 0; |
| 416 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 417 | } else { |
| 418 | sb_config->GecConfig = 1; |
| 419 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 420 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 421 | break; |
| 422 | |
| 423 | case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 424 | { |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 425 | device_t device; |
| 426 | for (device = dev; device; device = device->next) { |
| 427 | if (dev->path.type != DEVICE_PATH_PCI) continue; |
| 428 | if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; |
| 429 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 430 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 431 | |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 432 | /* |
| 433 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 434 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 435 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 436 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 437 | */ |
| 438 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 439 | } |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 440 | break; |
| 441 | |
| 442 | case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ |
| 443 | sb_config->USBMODE.UsbMode.Ohci1 = dev->enabled; |
| 444 | break; |
| 445 | case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ |
| 446 | sb_config->USBMODE.UsbMode.Ehci1 = dev->enabled; |
| 447 | break; |
| 448 | case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ |
| 449 | sb_config->USBMODE.UsbMode.Ohci2 = dev->enabled; |
| 450 | break; |
| 451 | case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ |
| 452 | sb_config->USBMODE.UsbMode.Ehci2 = dev->enabled; |
| 453 | break; |
| 454 | case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ |
| 455 | sb_config->USBMODE.UsbMode.Ohci4 = dev->enabled; |
| 456 | break; |
| 457 | case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ |
| 458 | sb_config->USBMODE.UsbMode.Ohci3 = dev->enabled; |
| 459 | break; |
| 460 | case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ |
| 461 | sb_config->USBMODE.UsbMode.Ehci3 = dev->enabled; |
| 462 | |
Kerry Sheh | 75df106 | 2011-10-10 19:19:46 +0800 | [diff] [blame] | 463 | /* call the CIMX entry at the last sb800 device, |
| 464 | * so make sure the mainboard devicetree is complete |
| 465 | */ |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 466 | #if CONFIG_HAVE_ACPI_RESUME |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 467 | if (acpi_slp_type != 3) |
| 468 | sb_Before_Pci_Init(); |
| 469 | else |
| 470 | sb_Before_Pci_Restore_Init(); |
| 471 | #else |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 472 | sb_Before_Pci_Init(); |
zbao | 9bcdbf8 | 2012-04-05 13:18:49 +0800 | [diff] [blame] | 473 | #endif |
Kerry She | feed329 | 2011-08-18 18:03:44 +0800 | [diff] [blame] | 474 | break; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 475 | |
| 476 | default: |
| 477 | break; |
| 478 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 479 | } |
| 480 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 481 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 482 | CHIP_NAME("ATI SB800") |
| 483 | .enable_dev = sb800_enable, |
| 484 | }; |