Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <device/device.h> /* device_t */ |
| 22 | #include <device/pci.h> /* device_operations */ |
| 23 | #include <device/pci_ids.h> |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 24 | #include <arch/ioapic.h> |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 25 | #include <device/smbus.h> /* smbus_bus_operations */ |
| 26 | #include <console/console.h> /* printk */ |
| 27 | #include "lpc.h" /* lpc_read_resources */ |
| 28 | #include "SBPLATFORM.h" /* Platfrom Specific Definitions */ |
| 29 | #include "cfg.h" /* sb800 Cimx configuration */ |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 30 | #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 31 | |
| 32 | |
| 33 | /*implement in mainboard.c*/ |
| 34 | //void set_pcie_assert(void); |
| 35 | //void set_pcie_deassert(void); |
| 36 | void set_pcie_reset(void); |
| 37 | void set_pcie_dereset(void); |
| 38 | |
| 39 | |
| 40 | #ifndef _RAMSTAGE_ |
| 41 | #define _RAMSTAGE_ |
| 42 | #endif |
| 43 | static AMDSBCFG sb_late_cfg; //global, init in sb800_cimx_config |
| 44 | static AMDSBCFG *sb_config = &sb_late_cfg; |
| 45 | |
| 46 | |
| 47 | /** |
| 48 | * @brief Entry point of Southbridge CIMx callout |
| 49 | * |
| 50 | * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig) |
| 51 | * |
| 52 | * @param[in] func Southbridge CIMx Function ID. |
| 53 | * @param[in] data Southbridge Input Data. |
| 54 | * @param[in] sb_config Southbridge configuration structure pointer. |
| 55 | * |
| 56 | */ |
| 57 | u32 sb800_callout_entry(u32 func, u32 data, void* config) |
| 58 | { |
| 59 | u32 ret = 0; |
| 60 | |
| 61 | switch (func) { |
| 62 | case CB_SBGPP_RESET_ASSERT: |
| 63 | //set_pcie_assert(); |
| 64 | set_pcie_reset(); |
| 65 | break; |
| 66 | |
| 67 | case CB_SBGPP_RESET_DEASSERT: |
| 68 | //set_pcie_deassert(); |
| 69 | set_pcie_dereset(); |
| 70 | break; |
| 71 | |
| 72 | case IMC_FIRMWARE_FAIL: |
| 73 | break; |
| 74 | |
| 75 | default: |
| 76 | break; |
| 77 | } |
| 78 | |
| 79 | return ret; |
| 80 | } |
| 81 | |
| 82 | |
| 83 | static struct pci_operations lops_pci = { |
| 84 | .set_subsystem = 0, |
| 85 | }; |
| 86 | |
| 87 | static void lpc_enable_resources(device_t dev) |
| 88 | { |
| 89 | |
| 90 | pci_dev_enable_resources(dev); |
| 91 | //lpc_enable_childrens_resources(dev); |
| 92 | } |
| 93 | |
| 94 | static void lpc_init(device_t dev) |
| 95 | { |
| 96 | /* SB Configure HPET base and enable bit */ |
| 97 | hpetInit(sb_config, &(sb_config->BuildParameters)); |
| 98 | } |
| 99 | |
| 100 | static struct device_operations lpc_ops = { |
| 101 | .read_resources = lpc_read_resources, |
| 102 | .set_resources = lpc_set_resources, |
| 103 | .enable_resources = lpc_enable_resources, |
| 104 | .init = lpc_init, |
| 105 | .scan_bus = scan_static_bus, |
| 106 | .ops_pci = &lops_pci, |
| 107 | }; |
| 108 | |
| 109 | static const struct pci_driver lpc_driver __pci_driver = { |
| 110 | .ops = &lpc_ops, |
| 111 | .vendor = PCI_VENDOR_ID_ATI, |
| 112 | .device = PCI_DEVICE_ID_ATI_SB800_LPC, |
| 113 | }; |
| 114 | |
| 115 | |
| 116 | static void sata_enable_resources(struct device *dev) |
| 117 | { |
| 118 | sataInitAfterPciEnum(sb_config); |
| 119 | pci_dev_enable_resources(dev); |
| 120 | } |
| 121 | |
| 122 | static void sata_init(struct device *dev) |
| 123 | { |
| 124 | sb_config->StdHeader.Func = SB_MID_POST_INIT; |
| 125 | AmdSbDispatcher(sb_config); //sataInitMidPost only |
| 126 | commonInitLateBoot(sb_config); |
| 127 | sataInitLatePost(sb_config); |
| 128 | } |
| 129 | |
| 130 | static struct device_operations sata_ops = { |
| 131 | .read_resources = pci_dev_read_resources, |
| 132 | .set_resources = pci_dev_set_resources, |
| 133 | .enable_resources = sata_enable_resources, //pci_dev_enable_resources, |
| 134 | .init = sata_init, |
| 135 | .scan_bus = 0, |
| 136 | .ops_pci = &lops_pci, |
| 137 | }; |
| 138 | |
| 139 | static const struct pci_driver sata_driver __pci_driver = { |
| 140 | .ops = &sata_ops, |
| 141 | .vendor = PCI_VENDOR_ID_ATI, |
Scott Duplichan | f191c72 | 2011-05-15 21:38:08 +0000 | [diff] [blame] | 142 | .device = PCI_DEVICE_ID_ATI_SB800_SATA_AHCI, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 143 | }; |
| 144 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 145 | #if CONFIG_USBDEBUG |
| 146 | static void usb_set_resources(struct device *dev) |
| 147 | { |
| 148 | struct resource *res; |
| 149 | u32 base; |
| 150 | u32 old_debug; |
| 151 | |
| 152 | old_debug = get_ehci_debug(); |
| 153 | set_ehci_debug(0); |
| 154 | |
| 155 | pci_dev_set_resources(dev); |
| 156 | |
| 157 | res = find_resource(dev, 0x10); |
| 158 | set_ehci_debug(old_debug); |
| 159 | if (!res) |
| 160 | return; |
| 161 | base = res->base; |
| 162 | set_ehci_base(base); |
| 163 | report_resource_stored(dev, res, ""); |
| 164 | } |
| 165 | #endif |
| 166 | |
| 167 | static void usb_init(struct device *dev) |
| 168 | { |
| 169 | usbInitAfterPciInit(sb_config); |
| 170 | commonInitLateBoot(sb_config); |
| 171 | } |
| 172 | |
| 173 | static struct device_operations usb_ops = { |
| 174 | .read_resources = pci_dev_read_resources, |
| 175 | #if CONFIG_USBDEBUG |
| 176 | .set_resources = usb_set_resources, |
| 177 | #else |
| 178 | .set_resources = pci_dev_set_resources, |
| 179 | #endif |
| 180 | .enable_resources = pci_dev_enable_resources, |
| 181 | .init = usb_init, |
| 182 | .scan_bus = 0, |
| 183 | .ops_pci = &lops_pci, |
| 184 | }; |
| 185 | |
| 186 | /* |
| 187 | * The pci id of usb ctrl 0 and 1 are the same. |
| 188 | */ |
| 189 | static const struct pci_driver usb_ohci123_driver __pci_driver = { |
| 190 | .ops = &usb_ops, |
| 191 | .vendor = PCI_VENDOR_ID_ATI, |
| 192 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */ |
| 193 | }; |
| 194 | |
| 195 | static const struct pci_driver usb_ehci123_driver __pci_driver = { |
| 196 | .ops = &usb_ops, |
| 197 | .vendor = PCI_VENDOR_ID_ATI, |
| 198 | .device = PCI_DEVICE_ID_ATI_SB800_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */ |
| 199 | }; |
| 200 | |
| 201 | static const struct pci_driver usb_ohci4_driver __pci_driver = { |
| 202 | .ops = &usb_ops, |
| 203 | .vendor = PCI_VENDOR_ID_ATI, |
| 204 | .device = PCI_DEVICE_ID_ATI_SB800_USB_20_5, /* OHCI-USB4 */ |
| 205 | }; |
| 206 | |
| 207 | |
| 208 | static void azalia_init(struct device *dev) |
| 209 | { |
| 210 | azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio |
| 211 | } |
| 212 | |
| 213 | static struct device_operations azalia_ops = { |
| 214 | .read_resources = pci_dev_read_resources, |
| 215 | .set_resources = pci_dev_set_resources, |
| 216 | .enable_resources = pci_dev_enable_resources, |
| 217 | .init = azalia_init, |
| 218 | .scan_bus = 0, |
| 219 | .ops_pci = &lops_pci, |
| 220 | }; |
| 221 | |
| 222 | static const struct pci_driver azalia_driver __pci_driver = { |
| 223 | .ops = &azalia_ops, |
| 224 | .vendor = PCI_VENDOR_ID_ATI, |
| 225 | .device = PCI_DEVICE_ID_ATI_SB800_HDA, |
| 226 | }; |
| 227 | |
| 228 | |
| 229 | static void gec_init(struct device *dev) |
| 230 | { |
| 231 | gecInitAfterPciEnum(sb_config); |
| 232 | gecInitLatePost(sb_config); |
| 233 | printk(BIOS_DEBUG, "gec hda enabled\n"); |
| 234 | } |
| 235 | |
| 236 | static struct device_operations gec_ops = { |
| 237 | .read_resources = pci_dev_read_resources, |
| 238 | .set_resources = pci_dev_set_resources, |
| 239 | .enable_resources = pci_dev_enable_resources, |
| 240 | .init = gec_init, |
| 241 | .scan_bus = 0, |
| 242 | .ops_pci = &lops_pci, |
| 243 | }; |
| 244 | |
| 245 | static const struct pci_driver gec_driver __pci_driver = { |
| 246 | .ops = &gec_ops, |
| 247 | .vendor = PCI_VENDOR_ID_ATI, |
| 248 | .device = PCI_DEVICE_ID_ATI_SB800_GEC, |
| 249 | }; |
| 250 | |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame^] | 251 | /** |
| 252 | * @brief Enable PCI Bridge |
| 253 | * |
| 254 | * PcibConfig [PM_Reg: EAh], PCIDisable [Bit0] |
| 255 | * 'PCIDisable' set to 0 to enable P2P bridge. |
| 256 | * 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins |
| 257 | * to function as GPIO {GPIO 35:0}. |
| 258 | */ |
| 259 | static void pci_init(device_t dev) |
| 260 | { |
| 261 | /* PCI Bridge SHOULD be enabled by default according to SB800 rrg, |
| 262 | * but actually was disabled in some platform, so I have to enabled it. |
| 263 | */ |
| 264 | RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0); |
| 265 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 266 | |
| 267 | static void pcie_init(device_t dev) |
| 268 | { |
| 269 | sbPcieGppLateInit(sb_config); |
| 270 | } |
| 271 | |
| 272 | static struct device_operations pci_ops = { |
| 273 | .read_resources = pci_bus_read_resources, |
| 274 | .set_resources = pci_dev_set_resources, |
| 275 | .enable_resources = pci_bus_enable_resources, |
Kerry She | 3e706b6 | 2011-06-24 22:52:15 +0800 | [diff] [blame^] | 276 | .init = pci_init, |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 277 | .scan_bus = pci_scan_bridge, |
| 278 | .reset_bus = pci_bus_reset, |
| 279 | .ops_pci = &lops_pci, |
| 280 | }; |
| 281 | |
| 282 | static const struct pci_driver pci_driver __pci_driver = { |
| 283 | .ops = &pci_ops, |
| 284 | .vendor = PCI_VENDOR_ID_ATI, |
| 285 | .device = PCI_DEVICE_ID_ATI_SB800_PCI, |
| 286 | }; |
| 287 | |
| 288 | |
| 289 | struct device_operations bridge_ops = { |
| 290 | .read_resources = pci_bus_read_resources, |
| 291 | .set_resources = pci_dev_set_resources, |
| 292 | .enable_resources = pci_bus_enable_resources, |
| 293 | .init = pcie_init, |
| 294 | .scan_bus = pci_scan_bridge, |
| 295 | .enable = 0, |
| 296 | .reset_bus = pci_bus_reset, |
| 297 | .ops_pci = &lops_pci, |
| 298 | }; |
| 299 | |
| 300 | /* 0:15:0 PCIe PortA */ |
| 301 | static const struct pci_driver PORTA_driver __pci_driver = { |
| 302 | .ops = &bridge_ops, |
| 303 | .vendor = PCI_VENDOR_ID_ATI, |
| 304 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEA, |
| 305 | }; |
| 306 | |
| 307 | /* 0:15:1 PCIe PortB */ |
| 308 | static const struct pci_driver PORTB_driver __pci_driver = { |
| 309 | .ops = &bridge_ops, |
| 310 | .vendor = PCI_VENDOR_ID_ATI, |
| 311 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEB, |
| 312 | }; |
| 313 | |
| 314 | /* 0:15:2 PCIe PortC */ |
| 315 | static const struct pci_driver PORTC_driver __pci_driver = { |
| 316 | .ops = &bridge_ops, |
| 317 | .vendor = PCI_VENDOR_ID_ATI, |
| 318 | .device = PCI_DEVICE_ID_ATI_SB800_PCIEC, |
| 319 | }; |
| 320 | |
| 321 | /* 0:15:3 PCIe PortD */ |
| 322 | static const struct pci_driver PORTD_driver __pci_driver = { |
| 323 | .ops = &bridge_ops, |
| 324 | .vendor = PCI_VENDOR_ID_ATI, |
| 325 | .device = PCI_DEVICE_ID_ATI_SB800_PCIED, |
| 326 | }; |
| 327 | |
| 328 | |
| 329 | /** |
| 330 | * @brief SB Cimx entry point sbBeforePciInit wrapper |
| 331 | */ |
| 332 | static void sb800_enable(device_t dev) |
| 333 | { |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 334 | struct southbridge_amd_cimx_sb800_config *sb_chip = |
| 335 | (struct southbridge_amd_cimx_sb800_config *)(dev->chip_info); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 336 | |
| 337 | sb800_cimx_config(sb_config); |
| 338 | printk(BIOS_DEBUG, "sb800_enable() "); |
| 339 | |
| 340 | /* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/ |
| 341 | commonInitEarlyBoot(sb_config); |
| 342 | commonInitEarlyPost(sb_config); |
| 343 | |
| 344 | switch (dev->path.pci.devfn) { |
| 345 | case (0x11 << 3) | 0: /* 0:11.0 SATA */ |
| 346 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 347 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 348 | if (1 == sb_chip->boot_switch_sata_ide) |
| 349 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. |
| 350 | else if (0 == sb_chip->boot_switch_sata_ide) |
| 351 | sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. |
| 352 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 353 | sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY |
| 357 | break; |
| 358 | |
| 359 | case (0x12 << 3) | 0: /* 0:12:0 OHCI-USB1 */ |
| 360 | case (0x12 << 3) | 2: /* 0:12:2 EHCI-USB1 */ |
| 361 | case (0x13 << 3) | 0: /* 0:13:0 OHCI-USB2 */ |
| 362 | case (0x13 << 3) | 2: /* 0:13:2 EHCI-USB2 */ |
| 363 | case (0x14 << 3) | 5: /* 0:14:5 OHCI-USB4 */ |
| 364 | case (0x16 << 3) | 0: /* 0:16:0 OHCI-USB3 */ |
| 365 | case (0x16 << 3) | 2: /* 0:16:2 EHCI-USB3 */ |
| 366 | usbInitBeforePciEnum(sb_config); // USB POST TIME Only |
| 367 | break; |
| 368 | |
| 369 | case (0x14 << 3) | 0: /* 0:14:0 SMBUS */ |
Scott Duplichan | be8fae1 | 2011-05-15 21:41:00 +0000 | [diff] [blame] | 370 | { |
Scott Duplichan | be8fae1 | 2011-05-15 21:41:00 +0000 | [diff] [blame] | 371 | u32 ioapic_base; |
| 372 | |
| 373 | printk(BIOS_INFO, "sm_init().\n"); |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 374 | ioapic_base = IO_APIC_ADDR; |
Scott Duplichan | be8fae1 | 2011-05-15 21:41:00 +0000 | [diff] [blame] | 375 | clear_ioapic(ioapic_base); |
| 376 | /* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */ |
| 377 | #if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS < 16) |
| 378 | /* Assign the ioapic ID the next available number after the processor core local APIC IDs */ |
| 379 | setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS); |
| 380 | #elif (CONFIG_APIC_ID_OFFSET > 0) |
Kerry She | 76d53b2 | 2011-06-01 02:00:30 +0000 | [diff] [blame] | 381 | /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */ |
Scott Duplichan | be8fae1 | 2011-05-15 21:41:00 +0000 | [diff] [blame] | 382 | setup_ioapic(ioapic_base, 0); |
| 383 | #else |
| 384 | #error "The processor APIC IDs must be lifted to make room for the I/O APIC ID" |
| 385 | #endif |
| 386 | } |
| 387 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 388 | break; |
| 389 | |
| 390 | case (0x14 << 3) | 1: /* 0:14:1 IDE */ |
| 391 | if (dev->enabled) { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 392 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_ENABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 393 | } else { |
Kerry She | 991f880 | 2011-06-01 01:56:49 +0000 | [diff] [blame] | 394 | sb_config->SATAMODE.SataMode.SataIdeCombinedMode = CIMX_OPTION_DISABLED; |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 395 | } |
| 396 | sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY |
| 397 | break; |
| 398 | |
| 399 | case (0x14 << 3) | 2: /* 0:14:2 HDA */ |
| 400 | if (dev->enabled) { |
| 401 | if (AZALIA_DISABLE == sb_config->AzaliaController) { |
| 402 | sb_config->AzaliaController = AZALIA_AUTO; |
| 403 | } |
| 404 | printk(BIOS_DEBUG, "hda enabled\n"); |
| 405 | } else { |
| 406 | sb_config->AzaliaController = AZALIA_DISABLE; |
| 407 | printk(BIOS_DEBUG, "hda disabled\n"); |
| 408 | } |
| 409 | azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio |
| 410 | break; |
| 411 | |
| 412 | |
| 413 | case (0x14 << 3) | 3: /* 0:14:3 LPC */ |
| 414 | break; |
| 415 | |
| 416 | case (0x14 << 3) | 4: /* 0:14:4 PCI */ |
| 417 | break; |
| 418 | |
| 419 | case (0x14 << 3) | 6: /* 0:14:6 GEC */ |
| 420 | if (dev->enabled) { |
| 421 | sb_config->GecConfig = 0; |
| 422 | printk(BIOS_DEBUG, "gec enabled\n"); |
| 423 | } else { |
| 424 | sb_config->GecConfig = 1; |
| 425 | printk(BIOS_DEBUG, "gec disabled\n"); |
| 426 | } |
| 427 | gecInitBeforePciEnum(sb_config); // Init GEC |
| 428 | break; |
| 429 | |
| 430 | case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 431 | { |
| 432 | device_t device; |
| 433 | for (device = dev; device; device = device->next) { |
| 434 | if (dev->path.type != DEVICE_PATH_PCI) continue; |
| 435 | if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break; |
| 436 | sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled; |
| 437 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 438 | |
| 439 | /* |
| 440 | * GPP_CFGMODE_X4000: PortA Lanes[3:0] |
| 441 | * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] |
| 442 | * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 |
| 443 | * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 |
| 444 | */ |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 445 | sb_config->GppLinkConfig = sb_chip->gpp_configuration; |
| 446 | sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; |
| 447 | AmdSbDispatcher(sb_config); |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 448 | break; |
Scott Duplichan | 8fed77a | 2011-06-18 10:46:45 -0500 | [diff] [blame] | 449 | } |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 450 | |
| 451 | default: |
| 452 | break; |
| 453 | } |
| 454 | |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 455 | } |
| 456 | |
efdesign98 | 05a89ab | 2011-06-20 17:38:49 -0700 | [diff] [blame] | 457 | struct chip_operations southbridge_amd_cimx_sb800_ops = { |
Frank Vibrans | 63e62b0 | 2011-02-14 18:38:14 +0000 | [diff] [blame] | 458 | CHIP_NAME("ATI SB800") |
| 459 | .enable_dev = sb800_enable, |
| 460 | }; |