Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 2 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 5 | #include <assert.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 6 | #include <commonlib/helpers.h> |
| 7 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 8 | #include <device/mmio.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 9 | #include <delay.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
| 12 | #include <device/pci_ops.h> |
| 13 | #include <intelblocks/cse.h> |
Subrata Banik | 80c9289 | 2022-02-01 00:26:55 +0530 | [diff] [blame] | 14 | #include <intelblocks/pmclib.h> |
Martin Roth | 8c97450 | 2022-11-20 17:56:44 -0700 | [diff] [blame] | 15 | #include <intelblocks/post_codes.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 16 | #include <option.h> |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 17 | #include <security/vboot/misc.h> |
| 18 | #include <security/vboot/vboot_common.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 19 | #include <soc/intel/common/reset.h> |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 20 | #include <soc/iomap.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 21 | #include <soc/pci_devs.h> |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 22 | #include <soc/me.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 23 | #include <string.h> |
| 24 | #include <timer.h> |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 25 | #include <types.h> |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 26 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 27 | #define HECI_BASE_SIZE (4 * KiB) |
| 28 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 29 | #define MAX_HECI_MESSAGE_RETRY_COUNT 5 |
| 30 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 31 | /* Wait up to 15 sec for HECI to get ready */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 32 | #define HECI_DELAY_READY_MS (15 * 1000) |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 33 | /* Wait up to 100 usec between circular buffer polls */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 34 | #define HECI_DELAY_US 100 |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 35 | /* Wait up to 5 sec for CSE to chew something we sent */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 36 | #define HECI_SEND_TIMEOUT_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 37 | /* Wait up to 5 sec for CSE to blurp a reply */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 38 | #define HECI_READ_TIMEOUT_MS (5 * 1000) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 39 | /* Wait up to 1 ms for CSE CIP */ |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 40 | #define HECI_CIP_TIMEOUT_US 1000 |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 41 | /* Wait up to 5 seconds for CSE to boot from RO(BP1) */ |
| 42 | #define CSE_DELAY_BOOT_TO_RO_MS (5 * 1000) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 43 | |
| 44 | #define SLOT_SIZE sizeof(uint32_t) |
| 45 | |
| 46 | #define MMIO_CSE_CB_WW 0x00 |
| 47 | #define MMIO_HOST_CSR 0x04 |
| 48 | #define MMIO_CSE_CB_RW 0x08 |
| 49 | #define MMIO_CSE_CSR 0x0c |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 50 | #define MMIO_CSE_DEVIDLE 0x800 |
| 51 | #define CSE_DEV_IDLE (1 << 2) |
| 52 | #define CSE_DEV_CIP (1 << 0) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 53 | |
| 54 | #define CSR_IE (1 << 0) |
| 55 | #define CSR_IS (1 << 1) |
| 56 | #define CSR_IG (1 << 2) |
| 57 | #define CSR_READY (1 << 3) |
| 58 | #define CSR_RESET (1 << 4) |
| 59 | #define CSR_RP_START 8 |
| 60 | #define CSR_RP (((1 << 8) - 1) << CSR_RP_START) |
| 61 | #define CSR_WP_START 16 |
| 62 | #define CSR_WP (((1 << 8) - 1) << CSR_WP_START) |
| 63 | #define CSR_CBD_START 24 |
| 64 | #define CSR_CBD (((1 << 8) - 1) << CSR_CBD_START) |
| 65 | |
| 66 | #define MEI_HDR_IS_COMPLETE (1 << 31) |
| 67 | #define MEI_HDR_LENGTH_START 16 |
| 68 | #define MEI_HDR_LENGTH_SIZE 9 |
| 69 | #define MEI_HDR_LENGTH (((1 << MEI_HDR_LENGTH_SIZE) - 1) \ |
| 70 | << MEI_HDR_LENGTH_START) |
| 71 | #define MEI_HDR_HOST_ADDR_START 8 |
| 72 | #define MEI_HDR_HOST_ADDR (((1 << 8) - 1) << MEI_HDR_HOST_ADDR_START) |
| 73 | #define MEI_HDR_CSE_ADDR_START 0 |
| 74 | #define MEI_HDR_CSE_ADDR (((1 << 8) - 1) << MEI_HDR_CSE_ADDR_START) |
| 75 | |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 76 | /* Get HECI BAR 0 from PCI configuration space */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 77 | static uintptr_t get_cse_bar(pci_devfn_t dev) |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 78 | { |
| 79 | uintptr_t bar; |
| 80 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 81 | bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 82 | assert(bar != 0); |
| 83 | /* |
| 84 | * Bits 31-12 are the base address as per EDS for SPI, |
| 85 | * Don't care about 0-11 bit |
| 86 | */ |
| 87 | return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; |
| 88 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 89 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 90 | static void heci_assign_resource(pci_devfn_t dev, uintptr_t tempbar) |
| 91 | { |
| 92 | u16 pcireg; |
| 93 | |
| 94 | /* Assign Resources */ |
| 95 | /* Clear BIT 1-2 of Command Register */ |
| 96 | pcireg = pci_read_config16(dev, PCI_COMMAND); |
| 97 | pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 98 | pci_write_config16(dev, PCI_COMMAND, pcireg); |
| 99 | |
| 100 | /* Program Temporary BAR for HECI device */ |
| 101 | pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); |
| 102 | pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); |
| 103 | |
| 104 | /* Enable Bus Master and MMIO Space */ |
| 105 | pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 106 | } |
| 107 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 108 | /* |
Subrata Banik | 0b92aa6 | 2022-06-01 06:54:44 +0000 | [diff] [blame] | 109 | * Initialize the CSE device with provided temporary BAR. If BAR is 0 use a |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 110 | * default. This is intended for pre-mem usage only where BARs haven't been |
| 111 | * assigned yet and devices are not enabled. |
| 112 | */ |
Subrata Banik | 0b92aa6 | 2022-06-01 06:54:44 +0000 | [diff] [blame] | 113 | void cse_init(uintptr_t tempbar) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 114 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 115 | pci_devfn_t dev = PCH_DEV_CSE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 116 | |
Matt DeVillier | f711bf0 | 2022-01-25 19:48:38 -0600 | [diff] [blame] | 117 | /* Check if device enabled */ |
| 118 | if (!is_cse_enabled()) |
| 119 | return; |
| 120 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 121 | /* Assume it is already initialized, nothing else to do */ |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 122 | if (get_cse_bar(dev)) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 123 | return; |
| 124 | |
| 125 | /* Use default pre-ram bar */ |
| 126 | if (!tempbar) |
| 127 | tempbar = HECI1_BASE_ADDRESS; |
| 128 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 129 | /* Assign HECI resource and enable the resource */ |
| 130 | heci_assign_resource(dev, tempbar); |
Sridhar Siricilla | cb2fd20 | 2021-06-09 19:27:06 +0530 | [diff] [blame] | 131 | |
| 132 | /* Trigger HECI Reset and make Host ready for communication with CSE */ |
| 133 | heci_reset(); |
Subrata Banik | 05e06cd | 2017-11-09 15:04:09 +0530 | [diff] [blame] | 134 | } |
| 135 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 136 | static uint32_t read_bar(pci_devfn_t dev, uint32_t offset) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 137 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 138 | return read32p(get_cse_bar(dev) + offset); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 139 | } |
| 140 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 141 | static void write_bar(pci_devfn_t dev, uint32_t offset, uint32_t val) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 142 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 143 | return write32p(get_cse_bar(dev) + offset, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 144 | } |
| 145 | |
| 146 | static uint32_t read_cse_csr(void) |
| 147 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 148 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | static uint32_t read_host_csr(void) |
| 152 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 153 | return read_bar(PCH_DEV_CSE, MMIO_HOST_CSR); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | static void write_host_csr(uint32_t data) |
| 157 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 158 | write_bar(PCH_DEV_CSE, MMIO_HOST_CSR, data); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 159 | } |
| 160 | |
| 161 | static size_t filled_slots(uint32_t data) |
| 162 | { |
| 163 | uint8_t wp, rp; |
| 164 | rp = data >> CSR_RP_START; |
| 165 | wp = data >> CSR_WP_START; |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 166 | return (uint8_t)(wp - rp); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static size_t cse_filled_slots(void) |
| 170 | { |
| 171 | return filled_slots(read_cse_csr()); |
| 172 | } |
| 173 | |
| 174 | static size_t host_empty_slots(void) |
| 175 | { |
| 176 | uint32_t csr; |
| 177 | csr = read_host_csr(); |
| 178 | |
| 179 | return ((csr & CSR_CBD) >> CSR_CBD_START) - filled_slots(csr); |
| 180 | } |
| 181 | |
| 182 | static void clear_int(void) |
| 183 | { |
| 184 | uint32_t csr; |
| 185 | csr = read_host_csr(); |
| 186 | csr |= CSR_IS; |
| 187 | write_host_csr(csr); |
| 188 | } |
| 189 | |
| 190 | static uint32_t read_slot(void) |
| 191 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 192 | return read_bar(PCH_DEV_CSE, MMIO_CSE_CB_RW); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static void write_slot(uint32_t val) |
| 196 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 197 | write_bar(PCH_DEV_CSE, MMIO_CSE_CB_WW, val); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 198 | } |
| 199 | |
| 200 | static int wait_write_slots(size_t cnt) |
| 201 | { |
| 202 | struct stopwatch sw; |
| 203 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 204 | stopwatch_init_msecs_expire(&sw, HECI_SEND_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 205 | while (host_empty_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 206 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 207 | if (stopwatch_expired(&sw)) { |
| 208 | printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); |
| 209 | return 0; |
| 210 | } |
| 211 | } |
| 212 | return 1; |
| 213 | } |
| 214 | |
| 215 | static int wait_read_slots(size_t cnt) |
| 216 | { |
| 217 | struct stopwatch sw; |
| 218 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 219 | stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 220 | while (cse_filled_slots() < cnt) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 221 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 222 | if (stopwatch_expired(&sw)) { |
| 223 | printk(BIOS_ERR, "HECI: timed out reading answer!\n"); |
| 224 | return 0; |
| 225 | } |
| 226 | } |
| 227 | return 1; |
| 228 | } |
| 229 | |
| 230 | /* get number of full 4-byte slots */ |
| 231 | static size_t bytes_to_slots(size_t bytes) |
| 232 | { |
| 233 | return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; |
| 234 | } |
| 235 | |
| 236 | static int cse_ready(void) |
| 237 | { |
| 238 | uint32_t csr; |
| 239 | csr = read_cse_csr(); |
| 240 | return csr & CSR_READY; |
| 241 | } |
| 242 | |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 243 | static bool cse_check_hfs1_com(int mode) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 244 | { |
| 245 | union me_hfsts1 hfs1; |
| 246 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 247 | return hfs1.fields.operation_mode == mode; |
| 248 | } |
| 249 | |
| 250 | bool cse_is_hfs1_cws_normal(void) |
| 251 | { |
| 252 | union me_hfsts1 hfs1; |
| 253 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 254 | if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL) |
| 255 | return true; |
| 256 | return false; |
| 257 | } |
| 258 | |
| 259 | bool cse_is_hfs1_com_normal(void) |
| 260 | { |
| 261 | return cse_check_hfs1_com(ME_HFS1_COM_NORMAL); |
| 262 | } |
| 263 | |
| 264 | bool cse_is_hfs1_com_secover_mei_msg(void) |
| 265 | { |
| 266 | return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); |
| 267 | } |
| 268 | |
| 269 | bool cse_is_hfs1_com_soft_temp_disable(void) |
| 270 | { |
| 271 | return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 272 | } |
| 273 | |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 274 | /* |
Sridhar Siricilla | 90a4393 | 2022-09-12 10:37:17 +0530 | [diff] [blame] | 275 | * Starting from TGL platform, HFSTS1.spi_protection_mode replaces mfg_mode to indicate |
| 276 | * SPI protection status as well as end-of-manufacturing(EOM) status where EOM flow is |
| 277 | * triggered in single staged operation (either through first boot with required MFIT |
| 278 | * configuratin or FPT /CLOSEMANUF). |
| 279 | * In staged manufacturing flow, spi_protection_mode alone doesn't indicate the EOM status. |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 280 | * |
Sridhar Siricilla | 90a4393 | 2022-09-12 10:37:17 +0530 | [diff] [blame] | 281 | * HFSTS1.spi_protection_mode description: |
| 282 | * mfg_mode = 0 means SPI protection is on. |
Subrata Banik | e74ebcd | 2021-12-27 10:49:19 +0000 | [diff] [blame] | 283 | * mfg_mode = 1 means SPI is unprotected. |
| 284 | */ |
| 285 | bool cse_is_hfs1_spi_protected(void) |
| 286 | { |
| 287 | union me_hfsts1 hfs1; |
| 288 | hfs1.data = me_read_config32(PCI_ME_HFSTS1); |
| 289 | return !hfs1.fields.mfg_mode; |
| 290 | } |
| 291 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 292 | bool cse_is_hfs3_fw_sku_lite(void) |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 293 | { |
| 294 | union me_hfsts3 hfs3; |
| 295 | hfs3.data = me_read_config32(PCI_ME_HFSTS3); |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 296 | return hfs3.fields.fw_sku == ME_HFS3_FW_SKU_LITE; |
Sridhar Siricilla | 3465d27 | 2020-02-06 15:31:04 +0530 | [diff] [blame] | 297 | } |
| 298 | |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 299 | /* Makes the host ready to communicate with CSE */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 300 | void cse_set_host_ready(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 301 | { |
| 302 | uint32_t csr; |
| 303 | csr = read_host_csr(); |
| 304 | csr &= ~CSR_RESET; |
| 305 | csr |= (CSR_IG | CSR_READY); |
| 306 | write_host_csr(csr); |
| 307 | } |
| 308 | |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 309 | /* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */ |
| 310 | uint8_t cse_wait_sec_override_mode(void) |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 311 | { |
| 312 | struct stopwatch sw; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 313 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Sridhar Siricilla | 8e46545 | 2019-09-23 20:59:38 +0530 | [diff] [blame] | 314 | while (!cse_is_hfs1_com_secover_mei_msg()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 315 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 316 | if (stopwatch_expired(&sw)) { |
| 317 | printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n"); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 318 | return 0; |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 319 | } |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 320 | } |
Rob Barnes | d522f38 | 2022-09-12 06:31:47 -0600 | [diff] [blame] | 321 | printk(BIOS_DEBUG, "HECI: CSE took %lld ms to enter security override mode\n", |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 322 | stopwatch_duration_msecs(&sw)); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 323 | return 1; |
| 324 | } |
| 325 | |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 326 | /* |
| 327 | * Polls for CSE's current operation mode 'Soft Temporary Disable'. |
| 328 | * The CSE enters the current operation mode when it boots from RO(BP1). |
| 329 | */ |
| 330 | uint8_t cse_wait_com_soft_temp_disable(void) |
| 331 | { |
| 332 | struct stopwatch sw; |
Subrata Banik | f576581 | 2021-09-30 13:37:10 +0530 | [diff] [blame] | 333 | stopwatch_init_msecs_expire(&sw, CSE_DELAY_BOOT_TO_RO_MS); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 334 | while (!cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 335 | udelay(HECI_DELAY_US); |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 336 | if (stopwatch_expired(&sw)) { |
| 337 | printk(BIOS_ERR, "HECI: Timed out waiting for CSE to boot from RO!\n"); |
| 338 | return 0; |
| 339 | } |
| 340 | } |
Rob Barnes | d522f38 | 2022-09-12 06:31:47 -0600 | [diff] [blame] | 341 | printk(BIOS_SPEW, "HECI: CSE took %lld ms to boot from RO\n", |
Sridhar Siricilla | 09ea371 | 2019-11-12 23:35:50 +0530 | [diff] [blame] | 342 | stopwatch_duration_msecs(&sw)); |
| 343 | return 1; |
| 344 | } |
| 345 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 346 | static int wait_heci_ready(void) |
| 347 | { |
| 348 | struct stopwatch sw; |
| 349 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 350 | stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY_MS); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 351 | while (!cse_ready()) { |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 352 | udelay(HECI_DELAY_US); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 353 | if (stopwatch_expired(&sw)) |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | return 1; |
| 358 | } |
| 359 | |
| 360 | static void host_gen_interrupt(void) |
| 361 | { |
| 362 | uint32_t csr; |
| 363 | csr = read_host_csr(); |
| 364 | csr |= CSR_IG; |
| 365 | write_host_csr(csr); |
| 366 | } |
| 367 | |
| 368 | static size_t hdr_get_length(uint32_t hdr) |
| 369 | { |
| 370 | return (hdr & MEI_HDR_LENGTH) >> MEI_HDR_LENGTH_START; |
| 371 | } |
| 372 | |
| 373 | static int |
| 374 | send_one_message(uint32_t hdr, const void *buff) |
| 375 | { |
| 376 | size_t pend_len, pend_slots, remainder, i; |
| 377 | uint32_t tmp; |
| 378 | const uint32_t *p = buff; |
| 379 | |
| 380 | /* Get space for the header */ |
| 381 | if (!wait_write_slots(1)) |
| 382 | return 0; |
| 383 | |
| 384 | /* First, write header */ |
| 385 | write_slot(hdr); |
| 386 | |
| 387 | pend_len = hdr_get_length(hdr); |
| 388 | pend_slots = bytes_to_slots(pend_len); |
| 389 | |
| 390 | if (!wait_write_slots(pend_slots)) |
| 391 | return 0; |
| 392 | |
| 393 | /* Write the body in whole slots */ |
| 394 | i = 0; |
| 395 | while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { |
| 396 | write_slot(*p++); |
| 397 | i += SLOT_SIZE; |
| 398 | } |
| 399 | |
| 400 | remainder = pend_len % SLOT_SIZE; |
| 401 | /* Pad to 4 bytes not touching caller's buffer */ |
| 402 | if (remainder) { |
| 403 | memcpy(&tmp, p, remainder); |
| 404 | write_slot(tmp); |
| 405 | } |
| 406 | |
| 407 | host_gen_interrupt(); |
| 408 | |
| 409 | /* Make sure nothing bad happened during transmission */ |
| 410 | if (!cse_ready()) |
| 411 | return 0; |
| 412 | |
| 413 | return pend_len; |
| 414 | } |
| 415 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 416 | /* |
| 417 | * Send message msg of size len to host from host_addr to cse_addr. |
Sridhar Siricilla | c760e41a | 2022-08-15 21:10:58 +0530 | [diff] [blame] | 418 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 419 | * Also, in case of errors, heci_reset() is triggered. |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 420 | */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 421 | static enum cse_tx_rx_status |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 422 | heci_send(const void *msg, size_t len, uint8_t host_addr, uint8_t client_addr) |
| 423 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 424 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 425 | uint32_t csr, hdr; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 426 | size_t sent, remaining, cb_size, max_length; |
| 427 | const uint8_t *p; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 428 | |
| 429 | if (!msg || !len) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 430 | return CSE_TX_ERR_INPUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 431 | |
| 432 | clear_int(); |
| 433 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 434 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 435 | p = msg; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 436 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 437 | if (!wait_heci_ready()) { |
| 438 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 439 | continue; |
| 440 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 441 | |
Subrata Banik | 4a722f5 | 2017-11-13 14:56:42 +0530 | [diff] [blame] | 442 | csr = read_host_csr(); |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 443 | cb_size = ((csr & CSR_CBD) >> CSR_CBD_START) * SLOT_SIZE; |
| 444 | /* |
| 445 | * Reserve one slot for the header. Limit max message |
| 446 | * length by 9 bits that are available in the header. |
| 447 | */ |
| 448 | max_length = MIN(cb_size, (1 << MEI_HDR_LENGTH_SIZE) - 1) |
| 449 | - SLOT_SIZE; |
| 450 | remaining = len; |
| 451 | |
| 452 | /* |
| 453 | * Fragment the message into smaller messages not exceeding |
Jonathan Neuschäfer | 5268b76 | 2018-02-12 12:24:25 +0100 | [diff] [blame] | 454 | * useful circular buffer length. Mark last message complete. |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 455 | */ |
| 456 | do { |
| 457 | hdr = MIN(max_length, remaining) |
| 458 | << MEI_HDR_LENGTH_START; |
| 459 | hdr |= client_addr << MEI_HDR_CSE_ADDR_START; |
| 460 | hdr |= host_addr << MEI_HDR_HOST_ADDR_START; |
| 461 | hdr |= (MIN(max_length, remaining) == remaining) ? |
Lee Leahy | 68ab0b5 | 2017-03-10 13:42:34 -0800 | [diff] [blame] | 462 | MEI_HDR_IS_COMPLETE : 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 463 | sent = send_one_message(hdr, p); |
| 464 | p += sent; |
| 465 | remaining -= sent; |
| 466 | } while (remaining > 0 && sent != 0); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 467 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 468 | if (!remaining) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 469 | return CSE_TX_RX_SUCCESS; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 470 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 471 | |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 472 | printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n"); |
| 473 | heci_reset(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 474 | return CSE_TX_ERR_CSE_NOT_READY; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 475 | } |
| 476 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 477 | static enum cse_tx_rx_status |
| 478 | recv_one_message(uint32_t *hdr, void *buff, size_t maxlen, size_t *recv_len) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 479 | { |
| 480 | uint32_t reg, *p = buff; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 481 | size_t recv_slots, remainder, i; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 482 | |
| 483 | /* first get the header */ |
| 484 | if (!wait_read_slots(1)) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 485 | return CSE_RX_ERR_TIMEOUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 486 | |
| 487 | *hdr = read_slot(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 488 | *recv_len = hdr_get_length(*hdr); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 489 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 490 | if (!*recv_len) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 491 | printk(BIOS_WARNING, "HECI: message is zero-sized\n"); |
| 492 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 493 | recv_slots = bytes_to_slots(*recv_len); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 494 | |
| 495 | i = 0; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 496 | if (*recv_len > maxlen) { |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 497 | printk(BIOS_ERR, "HECI: response is too big\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 498 | return CSE_RX_ERR_RESP_LEN_MISMATCH; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | /* wait for the rest of messages to arrive */ |
| 502 | wait_read_slots(recv_slots); |
| 503 | |
| 504 | /* fetch whole slots first */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 505 | while (i < ALIGN_DOWN(*recv_len, SLOT_SIZE)) { |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 506 | *p++ = read_slot(); |
| 507 | i += SLOT_SIZE; |
| 508 | } |
| 509 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 510 | /* |
| 511 | * If ME is not ready, something went wrong and |
| 512 | * we received junk |
| 513 | */ |
| 514 | if (!cse_ready()) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 515 | return CSE_RX_ERR_CSE_NOT_READY; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 516 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 517 | remainder = *recv_len % SLOT_SIZE; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 518 | |
| 519 | if (remainder) { |
| 520 | reg = read_slot(); |
| 521 | memcpy(p, ®, remainder); |
| 522 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 523 | return CSE_TX_RX_SUCCESS; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 524 | } |
| 525 | |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 526 | /* |
| 527 | * Receive message into buff not exceeding maxlen. Message is considered |
| 528 | * successfully received if a 'complete' indication is read from ME side |
| 529 | * and there was enough space in the buffer to fit that message. maxlen |
Sridhar Siricilla | c760e41a | 2022-08-15 21:10:58 +0530 | [diff] [blame] | 530 | * is updated with size of message that was received. |
| 531 | * Returns CSE_TX_RX_SUCCESS on success and other enum values on failure scenarios. |
| 532 | * Also, in case of errors, heci_reset() is triggered. |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 533 | */ |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 534 | static enum cse_tx_rx_status heci_receive(void *buff, size_t *maxlen) |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 535 | { |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 536 | uint8_t retry; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 537 | size_t left, received; |
| 538 | uint32_t hdr = 0; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 539 | uint8_t *p; |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 540 | enum cse_tx_rx_status ret = CSE_RX_ERR_TIMEOUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 541 | |
| 542 | if (!buff || !maxlen || !*maxlen) |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 543 | return CSE_RX_ERR_INPUT; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 544 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 545 | clear_int(); |
| 546 | |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 547 | for (retry = 0; retry < MAX_HECI_MESSAGE_RETRY_COUNT; retry++) { |
| 548 | p = buff; |
| 549 | left = *maxlen; |
| 550 | |
| 551 | if (!wait_heci_ready()) { |
| 552 | printk(BIOS_ERR, "HECI: not ready\n"); |
| 553 | continue; |
| 554 | } |
| 555 | |
| 556 | /* |
| 557 | * Receive multiple packets until we meet one marked |
| 558 | * complete or we run out of space in caller-provided buffer. |
| 559 | */ |
| 560 | do { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 561 | ret = recv_one_message(&hdr, p, left, &received); |
| 562 | if (ret) { |
Elyes HAOUAS | 3d45000 | 2018-08-09 18:55:58 +0200 | [diff] [blame] | 563 | printk(BIOS_ERR, "HECI: Failed to receive!\n"); |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 564 | goto CSE_RX_ERR_HANDLE; |
Lijian Zhao | c50296d | 2017-12-15 19:10:18 -0800 | [diff] [blame] | 565 | } |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 566 | left -= received; |
| 567 | p += received; |
| 568 | /* If we read out everything ping to send more */ |
| 569 | if (!(hdr & MEI_HDR_IS_COMPLETE) && !cse_filled_slots()) |
| 570 | host_gen_interrupt(); |
| 571 | } while (received && !(hdr & MEI_HDR_IS_COMPLETE) && left > 0); |
| 572 | |
| 573 | if ((hdr & MEI_HDR_IS_COMPLETE) && received) { |
Elyes Haouas | 9018dee | 2022-11-18 15:07:33 +0100 | [diff] [blame] | 574 | *maxlen = p - (uint8_t *)buff; |
Johnny Lin | a3e68c9 | 2022-08-09 15:36:30 +0800 | [diff] [blame] | 575 | if (CONFIG(SOC_INTEL_CSE_SERVER_SKU)) |
| 576 | clear_int(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 577 | return CSE_TX_RX_SUCCESS; |
Subrata Banik | 5c08c73 | 2017-11-13 14:54:37 +0530 | [diff] [blame] | 578 | } |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 579 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 580 | |
Sridhar Siricilla | 1506b77 | 2022-03-05 10:02:25 +0530 | [diff] [blame] | 581 | CSE_RX_ERR_HANDLE: |
| 582 | printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n"); |
| 583 | heci_reset(); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 584 | return CSE_RX_ERR_CSE_NOT_READY; |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 585 | } |
| 586 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 587 | enum cse_tx_rx_status heci_send_receive(const void *snd_msg, size_t snd_sz, void *rcv_msg, |
| 588 | size_t *rcv_sz, uint8_t cse_addr) |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 589 | { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 590 | enum cse_tx_rx_status ret; |
| 591 | |
| 592 | ret = heci_send(snd_msg, snd_sz, BIOS_HOST_ADDR, cse_addr); |
| 593 | if (ret) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 594 | printk(BIOS_ERR, "HECI: send Failed\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 595 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 596 | } |
| 597 | |
| 598 | if (rcv_msg != NULL) { |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 599 | ret = heci_receive(rcv_msg, rcv_sz); |
| 600 | if (ret) { |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 601 | printk(BIOS_ERR, "HECI: receive Failed\n"); |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 602 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 603 | } |
| 604 | } |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 605 | return ret; |
Sridhar Siricilla | a5208f5 | 2019-08-30 17:10:24 +0530 | [diff] [blame] | 606 | } |
| 607 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 608 | /* |
| 609 | * Attempt to reset the device. This is useful when host and ME are out |
| 610 | * of sync during transmission or ME didn't understand the message. |
| 611 | */ |
| 612 | int heci_reset(void) |
| 613 | { |
| 614 | uint32_t csr; |
| 615 | |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 616 | /* Clear post code to prevent eventlog entry from unknown code. */ |
Martin Roth | 8c97450 | 2022-11-20 17:56:44 -0700 | [diff] [blame] | 617 | post_code(POST_CODE_ZERO); |
Duncan Laurie | 15ca903 | 2020-11-05 10:09:07 -0800 | [diff] [blame] | 618 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 619 | /* Send reset request */ |
| 620 | csr = read_host_csr(); |
Sridhar Siricilla | b9d075b | 2019-08-31 11:38:33 +0530 | [diff] [blame] | 621 | csr |= (CSR_RESET | CSR_IG); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 622 | write_host_csr(csr); |
| 623 | |
| 624 | if (wait_heci_ready()) { |
| 625 | /* Device is back on its imaginary feet, clear reset */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 626 | cse_set_host_ready(); |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 627 | return 1; |
| 628 | } |
| 629 | |
| 630 | printk(BIOS_CRIT, "HECI: reset failed\n"); |
| 631 | |
| 632 | return 0; |
| 633 | } |
| 634 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 635 | bool is_cse_devfn_visible(unsigned int devfn) |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 636 | { |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 637 | int slot = PCI_SLOT(devfn); |
| 638 | int func = PCI_FUNC(devfn); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 639 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 640 | if (!is_devfn_enabled(devfn)) { |
| 641 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is disabled\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 642 | return false; |
| 643 | } |
| 644 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 645 | if (pci_read_config16(PCI_DEV(0, slot, func), PCI_VENDOR_ID) == 0xFFFF) { |
| 646 | printk(BIOS_WARNING, "HECI: CSE device %02x.%01x is hidden\n", slot, func); |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 647 | return false; |
| 648 | } |
| 649 | |
| 650 | return true; |
| 651 | } |
| 652 | |
Subrata Banik | 3710e99 | 2021-09-30 16:59:09 +0530 | [diff] [blame] | 653 | bool is_cse_enabled(void) |
| 654 | { |
| 655 | return is_cse_devfn_visible(PCH_DEVFN_CSE); |
| 656 | } |
| 657 | |
Sridhar Siricilla | 2cc6691 | 2019-08-31 11:20:34 +0530 | [diff] [blame] | 658 | uint32_t me_read_config32(int offset) |
| 659 | { |
| 660 | return pci_read_config32(PCH_DEV_CSE, offset); |
| 661 | } |
| 662 | |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 663 | static bool cse_is_global_reset_allowed(void) |
| 664 | { |
| 665 | /* |
| 666 | * Allow sending GLOBAL_RESET command only if: |
| 667 | * - CSE's current working state is Normal and current operation mode is Normal. |
| 668 | * - (or) CSE's current working state is normal and current operation mode can |
| 669 | * be Soft Temp Disable or Security Override Mode if CSE's Firmware SKU is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 670 | * Lite. |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 671 | */ |
| 672 | if (!cse_is_hfs1_cws_normal()) |
| 673 | return false; |
| 674 | |
| 675 | if (cse_is_hfs1_com_normal()) |
| 676 | return true; |
| 677 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 678 | if (cse_is_hfs3_fw_sku_lite()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 679 | if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg()) |
| 680 | return true; |
| 681 | } |
| 682 | return false; |
| 683 | } |
| 684 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 685 | /* |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 686 | * Sends GLOBAL_RESET_REQ cmd to CSE with reset type GLOBAL_RESET. |
| 687 | * Returns 0 on failure and 1 on success. |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 688 | */ |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 689 | static int cse_request_reset(enum rst_req_type rst_type) |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 690 | { |
| 691 | int status; |
| 692 | struct mkhi_hdr reply; |
| 693 | struct reset_message { |
| 694 | struct mkhi_hdr hdr; |
| 695 | uint8_t req_origin; |
| 696 | uint8_t reset_type; |
| 697 | } __packed; |
| 698 | struct reset_message msg = { |
| 699 | .hdr = { |
| 700 | .group_id = MKHI_GROUP_ID_CBM, |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 701 | .command = MKHI_CBM_GLOBAL_RESET_REQ, |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 702 | }, |
| 703 | .req_origin = GR_ORIGIN_BIOS_POST, |
| 704 | .reset_type = rst_type |
| 705 | }; |
| 706 | size_t reply_size; |
| 707 | |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 708 | printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 709 | |
Sridhar Siricilla | c2a2d2b | 2020-02-27 17:16:13 +0530 | [diff] [blame] | 710 | if (!(rst_type == GLOBAL_RESET || rst_type == CSE_RESET_ONLY)) { |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 711 | printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); |
| 712 | return 0; |
| 713 | } |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 714 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 715 | if (!cse_is_global_reset_allowed() || !is_cse_enabled()) { |
Sridhar Siricilla | 59c7cb7d | 2020-02-07 11:59:30 +0530 | [diff] [blame] | 716 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
| 717 | return 0; |
| 718 | } |
| 719 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 720 | heci_reset(); |
| 721 | |
| 722 | reply_size = sizeof(reply); |
| 723 | memset(&reply, 0, reply_size); |
| 724 | |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 725 | if (rst_type == CSE_RESET_ONLY) |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 726 | status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 727 | else |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 728 | status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size, |
| 729 | HECI_MKHI_ADDR); |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 730 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 731 | printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", !status ? "success" : "failure"); |
Sridhar Siricilla | f2eb687 | 2019-12-05 19:54:16 +0530 | [diff] [blame] | 732 | return status; |
Sridhar Siricilla | d415c20 | 2019-08-31 14:54:57 +0530 | [diff] [blame] | 733 | } |
| 734 | |
Subrata Banik | f463dc0 | 2020-09-14 19:04:03 +0530 | [diff] [blame] | 735 | int cse_request_global_reset(void) |
| 736 | { |
| 737 | return cse_request_reset(GLOBAL_RESET); |
| 738 | } |
| 739 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 740 | static bool cse_is_hmrfpo_enable_allowed(void) |
| 741 | { |
| 742 | /* |
| 743 | * Allow sending HMRFPO ENABLE command only if: |
| 744 | * - CSE's current working state is Normal and current operation mode is Normal |
| 745 | * - (or) cse's current working state is normal and current operation mode is |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 746 | * Soft Temp Disable if CSE's Firmware SKU is Lite |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 747 | */ |
| 748 | if (!cse_is_hfs1_cws_normal()) |
| 749 | return false; |
| 750 | |
| 751 | if (cse_is_hfs1_com_normal()) |
| 752 | return true; |
| 753 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 754 | if (cse_is_hfs3_fw_sku_lite() && cse_is_hfs1_com_soft_temp_disable()) |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 755 | return true; |
| 756 | |
| 757 | return false; |
| 758 | } |
| 759 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 760 | /* Sends HMRFPO Enable command to CSE */ |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 761 | enum cb_err cse_hmrfpo_enable(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 762 | { |
| 763 | struct hmrfpo_enable_msg { |
| 764 | struct mkhi_hdr hdr; |
| 765 | uint32_t nonce[2]; |
| 766 | } __packed; |
| 767 | |
| 768 | /* HMRFPO Enable message */ |
| 769 | struct hmrfpo_enable_msg msg = { |
| 770 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 771 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 772 | .command = MKHI_HMRFPO_ENABLE, |
| 773 | }, |
| 774 | .nonce = {0}, |
| 775 | }; |
| 776 | |
| 777 | /* HMRFPO Enable response */ |
| 778 | struct hmrfpo_enable_resp { |
| 779 | struct mkhi_hdr hdr; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 780 | /* Base addr for factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 781 | uint32_t fct_base; |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 782 | /* Length of factory data area, not relevant for client SKUs */ |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 783 | uint32_t fct_limit; |
| 784 | uint8_t status; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 785 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 786 | } __packed; |
| 787 | |
| 788 | struct hmrfpo_enable_resp resp; |
| 789 | size_t resp_size = sizeof(struct hmrfpo_enable_resp); |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 790 | |
Sridhar Siricilla | 49c25f2 | 2021-11-27 19:56:47 +0530 | [diff] [blame] | 791 | if (cse_is_hfs1_com_secover_mei_msg()) { |
| 792 | printk(BIOS_DEBUG, "HECI: CSE is already in security override mode, " |
| 793 | "skip sending HMRFPO_ENABLE command to CSE\n"); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 794 | return CB_SUCCESS; |
Sridhar Siricilla | 49c25f2 | 2021-11-27 19:56:47 +0530 | [diff] [blame] | 795 | } |
| 796 | |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 797 | printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 798 | |
| 799 | if (!cse_is_hmrfpo_enable_allowed()) { |
| 800 | printk(BIOS_ERR, "HECI: CSE does not meet required prerequisites\n"); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 801 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 802 | } |
| 803 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 804 | if (heci_send_receive(&msg, sizeof(struct hmrfpo_enable_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 805 | &resp, &resp_size, HECI_MKHI_ADDR)) |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 806 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 807 | |
| 808 | if (resp.hdr.result) { |
| 809 | printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 810 | return CB_ERR; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 811 | } |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 812 | |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 813 | if (resp.status) { |
| 814 | printk(BIOS_ERR, "HECI: HMRFPO_Enable Failed (resp status: %d)\n", resp.status); |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 815 | return CB_ERR; |
Sridhar Siricilla | d16187e | 2019-11-27 16:02:47 +0530 | [diff] [blame] | 816 | } |
| 817 | |
Sridhar Siricilla | ad6d312 | 2023-01-10 14:59:35 +0530 | [diff] [blame] | 818 | return CB_SUCCESS; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 819 | } |
| 820 | |
| 821 | /* |
| 822 | * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 823 | * The status can be DISABLED/LOCKED/ENABLED |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 824 | */ |
Sridhar Siricilla | ff072e6 | 2019-11-27 14:55:16 +0530 | [diff] [blame] | 825 | int cse_hmrfpo_get_status(void) |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 826 | { |
| 827 | struct hmrfpo_get_status_msg { |
| 828 | struct mkhi_hdr hdr; |
| 829 | } __packed; |
| 830 | |
| 831 | struct hmrfpo_get_status_resp { |
| 832 | struct mkhi_hdr hdr; |
| 833 | uint8_t status; |
Sridhar Siricilla | 63be918 | 2020-01-19 12:38:56 +0530 | [diff] [blame] | 834 | uint8_t reserved[3]; |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 835 | } __packed; |
| 836 | |
| 837 | struct hmrfpo_get_status_msg msg = { |
| 838 | .hdr = { |
Sridhar Siricilla | e202e67 | 2020-01-07 23:36:40 +0530 | [diff] [blame] | 839 | .group_id = MKHI_GROUP_ID_HMRFPO, |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 840 | .command = MKHI_HMRFPO_GET_STATUS, |
| 841 | }, |
| 842 | }; |
| 843 | struct hmrfpo_get_status_resp resp; |
| 844 | size_t resp_size = sizeof(struct hmrfpo_get_status_resp); |
| 845 | |
| 846 | printk(BIOS_INFO, "HECI: Sending Get HMRFPO Status Command\n"); |
| 847 | |
Sridhar Siricilla | 206905c | 2020-02-06 18:48:22 +0530 | [diff] [blame] | 848 | if (!cse_is_hfs1_cws_normal()) { |
| 849 | printk(BIOS_ERR, "HECI: CSE's current working state is not Normal\n"); |
| 850 | return -1; |
| 851 | } |
| 852 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 853 | if (heci_send_receive(&msg, sizeof(struct hmrfpo_get_status_msg), |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 854 | &resp, &resp_size, HECI_MKHI_ADDR)) { |
Sridhar Siricilla | e30a0e6 | 2019-08-31 16:12:21 +0530 | [diff] [blame] | 855 | printk(BIOS_ERR, "HECI: HMRFPO send/receive fail\n"); |
| 856 | return -1; |
| 857 | } |
| 858 | |
| 859 | if (resp.hdr.result) { |
| 860 | printk(BIOS_ERR, "HECI: HMRFPO Resp Failed:%d\n", |
| 861 | resp.hdr.result); |
| 862 | return -1; |
| 863 | } |
| 864 | |
| 865 | return resp.status; |
| 866 | } |
| 867 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 868 | void print_me_fw_version(void *unused) |
| 869 | { |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 870 | struct me_fw_ver_resp resp = {0}; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 871 | |
| 872 | /* Ignore if UART debugging is disabled */ |
| 873 | if (!CONFIG(CONSOLE_SERIAL)) |
| 874 | return; |
| 875 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 876 | if (get_me_fw_version(&resp) == CB_SUCCESS) { |
| 877 | printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, |
| 878 | resp.code.minor, resp.code.hotfix, resp.code.build); |
| 879 | return; |
| 880 | } |
| 881 | printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); |
| 882 | } |
| 883 | |
| 884 | enum cb_err get_me_fw_version(struct me_fw_ver_resp *resp) |
| 885 | { |
| 886 | const struct mkhi_hdr fw_ver_msg = { |
| 887 | .group_id = MKHI_GROUP_ID_GEN, |
| 888 | .command = MKHI_GEN_GET_FW_VERSION, |
| 889 | }; |
| 890 | |
| 891 | if (resp == NULL) { |
| 892 | printk(BIOS_ERR, "%s failed, null pointer parameter\n", __func__); |
| 893 | return CB_ERR; |
| 894 | } |
| 895 | size_t resp_size = sizeof(*resp); |
| 896 | |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 897 | /* Ignore if CSE is disabled */ |
| 898 | if (!is_cse_enabled()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 899 | return CB_ERR; |
Wim Vervoorn | 8602fb7 | 2020-03-30 12:17:54 +0200 | [diff] [blame] | 900 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 901 | /* |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 902 | * Ignore if ME Firmware SKU type is Lite since |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 903 | * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. |
| 904 | */ |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 905 | if (cse_is_hfs3_fw_sku_lite()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 906 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 907 | |
| 908 | /* |
| 909 | * Prerequisites: |
| 910 | * 1) HFSTS1 Current Working State is Normal |
| 911 | * 2) HFSTS1 Current Operation Mode is Normal |
| 912 | * 3) It's after DRAM INIT DONE message (taken care of by calling it |
| 913 | * during ramstage |
| 914 | */ |
| 915 | if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 916 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 917 | |
| 918 | heci_reset(); |
| 919 | |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 920 | if (heci_send_receive(&fw_ver_msg, sizeof(fw_ver_msg), resp, &resp_size, |
Rizwan Qureshi | 957857d | 2021-08-30 16:43:57 +0530 | [diff] [blame] | 921 | HECI_MKHI_ADDR)) |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 922 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 923 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 924 | if (resp->hdr.result) |
| 925 | return CB_ERR; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 926 | |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 927 | |
Johnny Lin | 72e7667 | 2021-10-09 12:35:35 +0800 | [diff] [blame] | 928 | return CB_SUCCESS; |
Sridhar Siricilla | 24a974a | 2020-02-19 14:41:36 +0530 | [diff] [blame] | 929 | } |
| 930 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 931 | void cse_trigger_vboot_recovery(enum csme_failure_reason reason) |
| 932 | { |
| 933 | printk(BIOS_DEBUG, "cse: CSE status registers: HFSTS1: 0x%x, HFSTS2: 0x%x " |
| 934 | "HFSTS3: 0x%x\n", me_read_config32(PCI_ME_HFSTS1), |
| 935 | me_read_config32(PCI_ME_HFSTS2), me_read_config32(PCI_ME_HFSTS3)); |
| 936 | |
Jakub Czapiga | 605f793 | 2022-11-04 12:18:04 +0000 | [diff] [blame] | 937 | if (CONFIG(VBOOT)) |
| 938 | vboot_fail_and_reboot(vboot_get_context(), VB2_RECOVERY_INTEL_CSE_LITE_SKU, |
| 939 | reason); |
| 940 | |
Tim Wawrzynczak | 09635f4 | 2021-06-18 10:08:47 -0600 | [diff] [blame] | 941 | die("cse: Failed to trigger recovery mode(recovery subcode:%d)\n", reason); |
| 942 | } |
| 943 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 944 | static bool disable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 945 | { |
| 946 | struct stopwatch sw; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 947 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 948 | dev_idle_ctrl &= ~CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 949 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 950 | |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 951 | stopwatch_init_usecs_expire(&sw, HECI_CIP_TIMEOUT_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 952 | do { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 953 | dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 954 | if ((dev_idle_ctrl & CSE_DEV_CIP) == CSE_DEV_CIP) |
| 955 | return true; |
Subrata Banik | 03aef28 | 2021-09-28 18:10:24 +0530 | [diff] [blame] | 956 | udelay(HECI_DELAY_US); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 957 | } while (!stopwatch_expired(&sw)); |
| 958 | |
| 959 | return false; |
| 960 | } |
| 961 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 962 | static void enable_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 963 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 964 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 965 | dev_idle_ctrl |= CSE_DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 966 | write_bar(dev, MMIO_CSE_DEVIDLE, dev_idle_ctrl); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 967 | } |
| 968 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 969 | enum cse_device_state get_cse_device_state(unsigned int devfn) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 970 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 971 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 972 | uint32_t dev_idle_ctrl = read_bar(dev, MMIO_CSE_DEVIDLE); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 973 | if ((dev_idle_ctrl & CSE_DEV_IDLE) == CSE_DEV_IDLE) |
| 974 | return DEV_IDLE; |
| 975 | |
| 976 | return DEV_ACTIVE; |
| 977 | } |
| 978 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 979 | static enum cse_device_state ensure_cse_active(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 980 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 981 | if (!disable_cse_idle(dev)) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 982 | return DEV_IDLE; |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 983 | pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 984 | |
| 985 | return DEV_ACTIVE; |
| 986 | } |
| 987 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 988 | static void ensure_cse_idle(pci_devfn_t dev) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 989 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 990 | enable_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 991 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 992 | pci_and_config32(dev, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 993 | } |
| 994 | |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 995 | bool set_cse_device_state(unsigned int devfn, enum cse_device_state requested_state) |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 996 | { |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 997 | enum cse_device_state current_state = get_cse_device_state(devfn); |
| 998 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 999 | |
| 1000 | if (current_state == requested_state) |
| 1001 | return true; |
| 1002 | |
| 1003 | if (requested_state == DEV_ACTIVE) |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1004 | return ensure_cse_active(dev) == requested_state; |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1005 | else |
Subrata Banik | c6e2552 | 2021-09-30 18:14:09 +0530 | [diff] [blame] | 1006 | ensure_cse_idle(dev); |
Subrata Banik | a219edb | 2021-09-25 15:02:37 +0530 | [diff] [blame] | 1007 | |
| 1008 | return true; |
| 1009 | } |
| 1010 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1011 | void cse_set_to_d0i3(void) |
| 1012 | { |
| 1013 | if (!is_cse_devfn_visible(PCH_DEVFN_CSE)) |
| 1014 | return; |
| 1015 | |
| 1016 | set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE); |
| 1017 | } |
| 1018 | |
| 1019 | /* Function to set D0I3 for all HECI devices */ |
| 1020 | void heci_set_to_d0i3(void) |
| 1021 | { |
| 1022 | for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { |
Subrata Banik | 5790956 | 2022-06-02 00:25:36 +0530 | [diff] [blame] | 1023 | unsigned int devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); |
Subrata Banik | 01bf002 | 2022-04-06 18:59:37 +0530 | [diff] [blame] | 1024 | if (!is_cse_devfn_visible(devfn)) |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1025 | continue; |
| 1026 | |
Subrata Banik | 01bf002 | 2022-04-06 18:59:37 +0530 | [diff] [blame] | 1027 | set_cse_device_state(devfn, DEV_IDLE); |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 1028 | } |
| 1029 | } |
| 1030 | |
Subrata Banik | 801dbf4 | 2022-06-01 07:56:40 +0000 | [diff] [blame] | 1031 | /* Initialize the HECI devices. */ |
| 1032 | void heci_init(void) |
| 1033 | { |
| 1034 | for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) { |
| 1035 | unsigned int devfn = PCI_DEVFN(PCH_DEV_SLOT_CSE, i); |
| 1036 | pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); |
| 1037 | |
| 1038 | if (!is_cse_devfn_visible(devfn)) |
| 1039 | continue; |
| 1040 | |
| 1041 | /* Assume it is already initialized, nothing else to do */ |
| 1042 | if (get_cse_bar(dev)) |
| 1043 | return; |
| 1044 | |
| 1045 | heci_assign_resource(dev, HECI1_BASE_ADDRESS + (i * HECI_BASE_SIZE)); |
| 1046 | |
| 1047 | ensure_cse_active(dev); |
| 1048 | } |
| 1049 | /* Trigger HECI Reset and make Host ready for communication with CSE */ |
| 1050 | heci_reset(); |
| 1051 | } |
| 1052 | |
Subrata Banik | 80c9289 | 2022-02-01 00:26:55 +0530 | [diff] [blame] | 1053 | void cse_control_global_reset_lock(void) |
| 1054 | { |
| 1055 | /* |
| 1056 | * As per ME BWG recommendation the BIOS should not lock down CF9GR bit during |
| 1057 | * manufacturing and re-manufacturing environment if HFSTS1 [4] is set. Note: |
| 1058 | * this recommendation is not applicable for CSE-Lite SKUs where BIOS should set |
| 1059 | * CF9LOCK bit irrespectively. |
| 1060 | * |
| 1061 | * Other than that, make sure payload/OS can't trigger global reset. |
| 1062 | * |
| 1063 | * BIOS must also ensure that CF9GR is cleared and locked (Bit31 of ETR3) |
| 1064 | * prior to transferring control to the OS. |
| 1065 | */ |
| 1066 | if (CONFIG(SOC_INTEL_CSE_LITE_SKU) || cse_is_hfs1_spi_protected()) |
| 1067 | pmc_global_reset_disable_and_lock(); |
| 1068 | else |
| 1069 | pmc_global_reset_enable(false); |
| 1070 | } |
| 1071 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1072 | #if ENV_RAMSTAGE |
| 1073 | |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1074 | /* |
| 1075 | * Disable the Intel (CS)Management Engine via HECI based on a cmos value |
| 1076 | * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working) |
| 1077 | * and value of `1` will result in a (CS)ME state of `3` (disabled). |
| 1078 | * |
| 1079 | * It isn't advised to use this in combination with me_cleaner. |
| 1080 | * |
| 1081 | * It is advisable to have a second cmos option called `me_state_counter`. |
| 1082 | * Whilst not essential, it avoid reboots loops if the (CS)ME fails to |
| 1083 | * change states after 3 attempts. Some versions of the (CS)ME need to be |
| 1084 | * reset 3 times. |
| 1085 | * |
| 1086 | * Ideal cmos values would be: |
| 1087 | * |
| 1088 | * # coreboot config options: cpu |
| 1089 | * 432 1 e 5 me_state |
| 1090 | * 440 4 h 0 me_state_counter |
| 1091 | * |
| 1092 | * #ID value text |
| 1093 | * 5 0 Enable |
| 1094 | * 5 1 Disable |
| 1095 | */ |
| 1096 | |
| 1097 | static void me_reset_with_count(void) |
| 1098 | { |
| 1099 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", UINT_MAX); |
| 1100 | |
| 1101 | if (cmos_me_state_counter != UINT_MAX) { |
| 1102 | printk(BIOS_DEBUG, "CMOS: me_state_counter = %u\n", cmos_me_state_counter); |
| 1103 | /* Avoid boot loops by only trying a state change 3 times */ |
| 1104 | if (cmos_me_state_counter < ME_DISABLE_ATTEMPTS) { |
| 1105 | cmos_me_state_counter++; |
| 1106 | set_uint_option("me_state_counter", cmos_me_state_counter); |
| 1107 | printk(BIOS_DEBUG, "ME: Reset attempt %u/%u.\n", cmos_me_state_counter, |
| 1108 | ME_DISABLE_ATTEMPTS); |
| 1109 | do_global_reset(); |
| 1110 | } else { |
| 1111 | /* |
| 1112 | * If the (CS)ME fails to change states after 3 attempts, it will |
| 1113 | * likely need a cold boot, or recovering. |
| 1114 | */ |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 1115 | printk(BIOS_ERR, "Failed to change ME state in %u attempts!\n", |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1116 | ME_DISABLE_ATTEMPTS); |
| 1117 | |
| 1118 | } |
| 1119 | } else { |
| 1120 | printk(BIOS_DEBUG, "ME: Resetting"); |
| 1121 | do_global_reset(); |
| 1122 | } |
| 1123 | } |
| 1124 | |
| 1125 | static void cse_set_state(struct device *dev) |
| 1126 | { |
| 1127 | |
| 1128 | /* (CS)ME Disable Command */ |
| 1129 | struct me_disable_command { |
| 1130 | struct mkhi_hdr hdr; |
| 1131 | uint32_t rule_id; |
| 1132 | uint8_t rule_len; |
| 1133 | uint32_t rule_data; |
| 1134 | } __packed me_disable = { |
| 1135 | .hdr = { |
| 1136 | .group_id = MKHI_GROUP_ID_FWCAPS, |
| 1137 | .command = MKHI_SET_ME_DISABLE, |
| 1138 | }, |
| 1139 | .rule_id = ME_DISABLE_RULE_ID, |
| 1140 | .rule_len = ME_DISABLE_RULE_LENGTH, |
| 1141 | .rule_data = ME_DISABLE_COMMAND, |
| 1142 | }; |
| 1143 | |
| 1144 | struct me_disable_reply { |
| 1145 | struct mkhi_hdr hdr; |
| 1146 | uint32_t rule_id; |
| 1147 | } __packed; |
| 1148 | |
| 1149 | struct me_disable_reply disable_reply; |
| 1150 | |
| 1151 | size_t disable_reply_size; |
| 1152 | |
| 1153 | /* (CS)ME Enable Command */ |
| 1154 | struct me_enable_command { |
| 1155 | struct mkhi_hdr hdr; |
| 1156 | } me_enable = { |
| 1157 | .hdr = { |
| 1158 | .group_id = MKHI_GROUP_ID_BUP_COMMON, |
| 1159 | .command = MKHI_SET_ME_ENABLE, |
| 1160 | }, |
| 1161 | }; |
| 1162 | |
| 1163 | struct me_enable_reply { |
| 1164 | struct mkhi_hdr hdr; |
| 1165 | } __packed; |
| 1166 | |
| 1167 | struct me_enable_reply enable_reply; |
| 1168 | |
| 1169 | size_t enable_reply_size; |
| 1170 | |
| 1171 | /* Function Start */ |
| 1172 | |
| 1173 | int send; |
| 1174 | int result; |
| 1175 | /* |
| 1176 | * Check if the CMOS value "me_state" exists, if it doesn't, then |
| 1177 | * don't do anything. |
| 1178 | */ |
| 1179 | const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); |
| 1180 | |
| 1181 | if (cmos_me_state == UINT_MAX) |
| 1182 | return; |
| 1183 | |
| 1184 | printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); |
| 1185 | |
| 1186 | /* |
| 1187 | * We only take action if the me_state doesn't match the CS(ME) working state |
| 1188 | */ |
| 1189 | |
| 1190 | const unsigned int soft_temp_disable = cse_is_hfs1_com_soft_temp_disable(); |
| 1191 | |
| 1192 | if (cmos_me_state && !soft_temp_disable) { |
| 1193 | /* me_state should be disabled, but it's enabled */ |
| 1194 | printk(BIOS_DEBUG, "ME needs to be disabled.\n"); |
| 1195 | send = heci_send_receive(&me_disable, sizeof(me_disable), |
| 1196 | &disable_reply, &disable_reply_size, HECI_MKHI_ADDR); |
| 1197 | result = disable_reply.hdr.result; |
| 1198 | } else if (!cmos_me_state && soft_temp_disable) { |
| 1199 | /* me_state should be enabled, but it's disabled */ |
| 1200 | printk(BIOS_DEBUG, "ME needs to be enabled.\n"); |
| 1201 | send = heci_send_receive(&me_enable, sizeof(me_enable), |
| 1202 | &enable_reply, &enable_reply_size, HECI_MKHI_ADDR); |
| 1203 | result = enable_reply.hdr.result; |
| 1204 | } else { |
| 1205 | printk(BIOS_DEBUG, "ME is %s.\n", cmos_me_state ? "disabled" : "enabled"); |
| 1206 | unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", |
| 1207 | UINT_MAX); |
| 1208 | /* set me_state_counter to 0 */ |
| 1209 | if ((cmos_me_state_counter != UINT_MAX && cmos_me_state_counter != 0)) |
| 1210 | set_uint_option("me_state_counter", 0); |
| 1211 | return; |
| 1212 | } |
| 1213 | |
| 1214 | printk(BIOS_DEBUG, "HECI: ME state change send %s!\n", |
Sridhar Siricilla | 6836da2 | 2022-02-23 23:36:45 +0530 | [diff] [blame] | 1215 | !send ? "success" : "failure"); |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1216 | printk(BIOS_DEBUG, "HECI: ME state change result %s!\n", |
| 1217 | result ? "success" : "failure"); |
| 1218 | |
| 1219 | /* |
| 1220 | * Reset if the result was successful, or if the send failed as some older |
| 1221 | * version of the Intel (CS)ME won't successfully receive the message unless reset |
| 1222 | * twice. |
| 1223 | */ |
| 1224 | if (send || !result) |
| 1225 | me_reset_with_count(); |
| 1226 | } |
| 1227 | |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1228 | /* |
| 1229 | * `cse_final_ready_to_boot` function is native implementation of equivalent events |
| 1230 | * performed by FSP NotifyPhase(Ready To Boot) API invocations. |
| 1231 | * |
| 1232 | * Operations are: |
Subrata Banik | 5214c40 | 2022-11-24 20:43:37 +0530 | [diff] [blame] | 1233 | * 1. Perform global reset lock. |
| 1234 | * 2. Put HECI1 to D0i3 and disable the HECI1 if the user selects |
Subrata Banik | 670572f | 2022-04-25 15:39:55 +0530 | [diff] [blame] | 1235 | * DISABLE_HECI1_AT_PRE_BOOT config or CSE HFSTS1 Operation Mode is |
| 1236 | * `Software Temporary Disable`. |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1237 | */ |
| 1238 | static void cse_final_ready_to_boot(void) |
| 1239 | { |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1240 | cse_control_global_reset_lock(); |
| 1241 | |
Subrata Banik | 670572f | 2022-04-25 15:39:55 +0530 | [diff] [blame] | 1242 | if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || cse_is_hfs1_com_soft_temp_disable()) { |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1243 | cse_set_to_d0i3(); |
| 1244 | heci1_disable(); |
| 1245 | } |
| 1246 | } |
| 1247 | |
| 1248 | /* |
| 1249 | * `cse_final_end_of_firmware` function is native implementation of equivalent events |
| 1250 | * performed by FSP NotifyPhase(End of Firmware) API invocations. |
| 1251 | * |
| 1252 | * Operations are: |
| 1253 | * 1. Set D0I3 for all HECI devices. |
| 1254 | */ |
| 1255 | static void cse_final_end_of_firmware(void) |
| 1256 | { |
| 1257 | heci_set_to_d0i3(); |
| 1258 | } |
| 1259 | |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1260 | /* |
Subrata Banik | 17a3da8 | 2022-11-24 21:51:42 +0530 | [diff] [blame] | 1261 | * This function to perform essential post EOP cse related operations |
| 1262 | * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config |
| 1263 | */ |
| 1264 | void cse_late_finalize(void) |
| 1265 | { |
| 1266 | if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) |
| 1267 | return; |
| 1268 | |
| 1269 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) |
| 1270 | cse_final_ready_to_boot(); |
| 1271 | |
| 1272 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) |
| 1273 | cse_final_end_of_firmware(); |
| 1274 | } |
| 1275 | |
| 1276 | /* |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1277 | * `cse_final` function is native implementation of equivalent events performed by |
| 1278 | * each FSP NotifyPhase() API invocations. |
| 1279 | */ |
| 1280 | static void cse_final(struct device *dev) |
| 1281 | { |
Subrata Banik | 5214c40 | 2022-11-24 20:43:37 +0530 | [diff] [blame] | 1282 | /* SoC user decided to send EOP late */ |
| 1283 | if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) |
| 1284 | return; |
| 1285 | |
| 1286 | /* 1. Send EOP to CSE if not done.*/ |
| 1287 | if (CONFIG(SOC_INTEL_CSE_SET_EOP)) |
| 1288 | cse_send_end_of_post(); |
| 1289 | |
Angel Pons | 28315f8 | 2022-04-19 10:03:56 +0200 | [diff] [blame] | 1290 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) |
| 1291 | cse_final_ready_to_boot(); |
| 1292 | |
| 1293 | if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) |
| 1294 | cse_final_end_of_firmware(); |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1295 | } |
| 1296 | |
Nico Huber | 5768619 | 2022-08-06 19:11:55 +0200 | [diff] [blame] | 1297 | struct device_operations cse_ops = { |
Subrata Banik | 38abbda | 2021-09-30 13:15:50 +0530 | [diff] [blame] | 1298 | .set_resources = pci_dev_set_resources, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1299 | .read_resources = pci_dev_read_resources, |
| 1300 | .enable_resources = pci_dev_enable_resources, |
| 1301 | .init = pci_dev_init, |
Subrata Banik | 6bbc91a | 2017-12-07 14:55:51 +0530 | [diff] [blame] | 1302 | .ops_pci = &pci_dev_ops_pci, |
Sean Rhodes | 69ed3ed | 2021-04-30 16:38:17 +0100 | [diff] [blame] | 1303 | .enable = cse_set_state, |
Subrata Banik | 90e318b | 2022-02-06 16:26:45 +0530 | [diff] [blame] | 1304 | .final = cse_final, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1305 | }; |
| 1306 | |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1307 | static const unsigned short pci_device_ids[] = { |
Wonkyu Kim | 9f40107 | 2020-11-13 15:16:32 -0800 | [diff] [blame] | 1308 | PCI_DID_INTEL_MTL_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1309 | PCI_DID_INTEL_APL_CSE0, |
| 1310 | PCI_DID_INTEL_GLK_CSE0, |
| 1311 | PCI_DID_INTEL_CNL_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1312 | PCI_DID_INTEL_LWB_CSE0, |
| 1313 | PCI_DID_INTEL_LWB_CSE0_SUPER, |
| 1314 | PCI_DID_INTEL_CNP_H_CSE0, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1315 | PCI_DID_INTEL_CMP_CSE0, |
| 1316 | PCI_DID_INTEL_CMP_H_CSE0, |
| 1317 | PCI_DID_INTEL_TGL_CSE0, |
| 1318 | PCI_DID_INTEL_TGL_H_CSE0, |
| 1319 | PCI_DID_INTEL_MCC_CSE0, |
| 1320 | PCI_DID_INTEL_MCC_CSE1, |
| 1321 | PCI_DID_INTEL_MCC_CSE2, |
| 1322 | PCI_DID_INTEL_MCC_CSE3, |
| 1323 | PCI_DID_INTEL_JSP_CSE0, |
| 1324 | PCI_DID_INTEL_JSP_CSE1, |
| 1325 | PCI_DID_INTEL_JSP_CSE2, |
| 1326 | PCI_DID_INTEL_JSP_CSE3, |
| 1327 | PCI_DID_INTEL_ADP_P_CSE0, |
| 1328 | PCI_DID_INTEL_ADP_P_CSE1, |
| 1329 | PCI_DID_INTEL_ADP_P_CSE2, |
| 1330 | PCI_DID_INTEL_ADP_P_CSE3, |
| 1331 | PCI_DID_INTEL_ADP_S_CSE0, |
| 1332 | PCI_DID_INTEL_ADP_S_CSE1, |
| 1333 | PCI_DID_INTEL_ADP_S_CSE2, |
| 1334 | PCI_DID_INTEL_ADP_S_CSE3, |
| 1335 | PCI_DID_INTEL_ADP_M_CSE0, |
| 1336 | PCI_DID_INTEL_ADP_M_CSE1, |
| 1337 | PCI_DID_INTEL_ADP_M_CSE2, |
| 1338 | PCI_DID_INTEL_ADP_M_CSE3, |
Hannah Williams | 6314215 | 2017-06-12 14:03:18 -0700 | [diff] [blame] | 1339 | 0, |
| 1340 | }; |
| 1341 | |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1342 | static const struct pci_driver cse_driver __pci_driver = { |
| 1343 | .ops = &cse_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 1344 | .vendor = PCI_VID_INTEL, |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1345 | /* SoC/chipset needs to provide PCI device ID */ |
Andrey Petrov | 0405de9 | 2017-06-05 13:25:29 -0700 | [diff] [blame] | 1346 | .devices = pci_device_ids |
Andrey Petrov | 04a72c4 | 2017-03-01 15:51:57 -0800 | [diff] [blame] | 1347 | }; |
| 1348 | |
| 1349 | #endif |