sb/intel/lynxpoint: Generate the ACPI FADT with a common function

The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x.

Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux
4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel
log. System reset, poweroff, and S3 suspend/resume continue to work.

General improvements
--------------------

- `fadt->preferred_pm_profile` is set based on the value of
  `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded.

- Constants are used instead of magic values in more locations.

- `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set
  appropriately depending on whether the system uses Lynx Point LP or
  not.

- Boards can indicate docking support in the FADT via the devicetree.

Changes to existing Lynx Point boards
-------------------------------------

- `header->asl_compiler_revision` changes from 1 to 0.

- `fadt->model` is left at 0 instead of being set to 1. This field is
  only needed for ACPI 1.0 compatibility.

- `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is
  because their values are ignored, since `ACPI_FADT_WBINVD` is set in
  `fadt->flags`.

- `fadt->duty_offset` is set to 0 instead of 1. None of the existing
  boards indicate support for changing the processor duty cycle (as
  `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not
  currently need to be set.

- Access sizes of registers are set.

- On mb/intel/baskingridge, the pmbase is now read using the common
  function `get_pmbase()` instead of `pci_read_config16(...)`.

- On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width`
  changes from 64 to 128. The correct value should be 128 (bits), to
  match `fadt->gpe0_blk_len`, which is set to 16 (bytes).

- On Lynx Point LP systems, the unused extended address
  `fadt->x_gpe0_blk` sets its address space ID to be consistent with
  other unused extended addresses. Such a change should not alter the
  interpretation of the registers as being unused. Why not set them all
  to zero? Simply because the existing practice, in both coreboot and
  some other vendors' firmware, has them set in such a case.

A diff of the FADT from a Google Peppy board is below:

--- pre/facp.dsl	2018-10-30 20:14:52.676570798 +1300
+++ post/facp.dsl	2018-10-30 20:15:06.904381436 +1300
@@ -1,179 +1,179 @@
 /*
  * Intel ACPI Component Architecture
  * AML/ASL+ Disassembler version 20180810 (64-bit version)
  * Copyright (c) 2000 - 2018 Intel Corporation
  *
- * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018
+ * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018
  *
  * ACPI Data Table [FACP]
  *
  * Format: [HexOffset DecimalOffset ByteLength]  FieldName : FieldValue
  */

 [000h 0000   4]                    Signature : "FACP"    [Fixed ACPI Description Table (FADT)]
 [004h 0004   4]                 Table Length : 000000F4
 [008h 0008   1]                     Revision : 04
-[009h 0009   1]                     Checksum : 61
+[009h 0009   1]                     Checksum : 6E
 [00Ah 0010   6]                       Oem ID : "CORE  "
 [010h 0016   8]                 Oem Table ID : "COREBOOT"
 [018h 0024   4]                 Oem Revision : 00000000
 [01Ch 0028   4]              Asl Compiler ID : "CORE"
-[020h 0032   4]        Asl Compiler Revision : 00000001
+[020h 0032   4]        Asl Compiler Revision : 00000000

 [024h 0036   4]                 FACS Address : 7BF46240
 [028h 0040   4]                 DSDT Address : 7BF46280
-[02Ch 0044   1]                        Model : 01
+[02Ch 0044   1]                        Model : 00
 [02Dh 0045   1]                   PM Profile : 02 [Mobile]
 [02Eh 0046   2]                SCI Interrupt : 0009
 [030h 0048   4]             SMI Command Port : 000000B2
 [034h 0052   1]            ACPI Enable Value : E1
 [035h 0053   1]           ACPI Disable Value : 1E
 [036h 0054   1]               S4BIOS Command : 00
 [037h 0055   1]              P-State Control : 00
 [038h 0056   4]     PM1A Event Block Address : 00001000
 [03Ch 0060   4]     PM1B Event Block Address : 00000000
 [040h 0064   4]   PM1A Control Block Address : 00001004
 [044h 0068   4]   PM1B Control Block Address : 00000000
 [048h 0072   4]    PM2 Control Block Address : 00001050
 [04Ch 0076   4]       PM Timer Block Address : 00001008
 [050h 0080   4]           GPE0 Block Address : 00001080
 [054h 0084   4]           GPE1 Block Address : 00000000
 [058h 0088   1]       PM1 Event Block Length : 04
 [059h 0089   1]     PM1 Control Block Length : 02
 [05Ah 0090   1]     PM2 Control Block Length : 01
 [05Bh 0091   1]        PM Timer Block Length : 04
 [05Ch 0092   1]            GPE0 Block Length : 20
 [05Dh 0093   1]            GPE1 Block Length : 00
 [05Eh 0094   1]             GPE1 Base Offset : 00
 [05Fh 0095   1]                 _CST Support : 00
 [060h 0096   2]                   C2 Latency : 0001
 [062h 0098   2]                   C3 Latency : 0057
-[064h 0100   2]               CPU Cache Size : 0400
-[066h 0102   2]           Cache Flush Stride : 0010
-[068h 0104   1]            Duty Cycle Offset : 01
+[064h 0100   2]               CPU Cache Size : 0000
+[066h 0102   2]           Cache Flush Stride : 0000
+[068h 0104   1]            Duty Cycle Offset : 00
 [069h 0105   1]             Duty Cycle Width : 00
 [06Ah 0106   1]          RTC Day Alarm Index : 0D
 [06Bh 0107   1]        RTC Month Alarm Index : 00
 [06Ch 0108   1]            RTC Century Index : 00
 [06Dh 0109   2]   Boot Flags (decoded below) : 0003
                Legacy Devices Supported (V2) : 1
             8042 Present on ports 60/64 (V2) : 1
                         VGA Not Present (V4) : 0
                       MSI Not Supported (V4) : 0
                 PCIe ASPM Not Supported (V4) : 0
                    CMOS RTC Not Present (V5) : 0
 [06Fh 0111   1]                     Reserved : 00
 [070h 0112   4]        Flags (decoded below) : 00008CAD
       WBINVD instruction is operational (V1) : 1
               WBINVD flushes all caches (V1) : 0
                     All CPUs support C1 (V1) : 1
                   C2 works on MP system (V1) : 1
             Control Method Power Button (V1) : 0
             Control Method Sleep Button (V1) : 1
         RTC wake not in fixed reg space (V1) : 0
             RTC can wake system from S4 (V1) : 1
                         32-bit PM Timer (V1) : 0
                       Docking Supported (V1) : 0
                Reset Register Supported (V2) : 1
                             Sealed Case (V3) : 1
                     Headless - No Video (V3) : 0
         Use native instr after SLP_TYPx (V3) : 0
               PCIEXP_WAK Bits Supported (V4) : 0
                      Use Platform Timer (V4) : 1
                RTC_STS valid on S4 wake (V4) : 0
                 Remote Power-on capable (V4) : 0
                  Use APIC Cluster Model (V4) : 0
      Use APIC Physical Destination Mode (V4) : 0
                        Hardware Reduced (V5) : 0
                       Low Power S0 Idle (V5) : 0

 [074h 0116  12]               Reset Register : [Generic Address Structure]
 [074h 0116   1]                     Space ID : 01 [SystemIO]
 [075h 0117   1]                    Bit Width : 08
 [076h 0118   1]                   Bit Offset : 00
-[077h 0119   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[077h 0119   1]         Encoded Access Width : 01 [Byte Access:8]
 [078h 0120   8]                      Address : 0000000000000CF9

 [080h 0128   1]         Value to cause reset : 06
 [081h 0129   2]    ARM Flags (decoded below) : 0000
                               PSCI Compliant : 0
                        Must use HVC for PSCI : 0

 [083h 0131   1]          FADT Minor Revision : 00
 [084h 0132   8]                 FACS Address : 000000007BF46240
 [08Ch 0140   8]                 DSDT Address : 000000007BF46280
 [094h 0148  12]             PM1A Event Block : [Generic Address Structure]
 [094h 0148   1]                     Space ID : 01 [SystemIO]
 [095h 0149   1]                    Bit Width : 20
 [096h 0150   1]                   Bit Offset : 00
-[097h 0151   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[097h 0151   1]         Encoded Access Width : 02 [Word Access:16]
 [098h 0152   8]                      Address : 0000000000001000

 [0A0h 0160  12]             PM1B Event Block : [Generic Address Structure]
 [0A0h 0160   1]                     Space ID : 01 [SystemIO]
 [0A1h 0161   1]                    Bit Width : 00
 [0A2h 0162   1]                   Bit Offset : 00
 [0A3h 0163   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0A4h 0164   8]                      Address : 0000000000000000

 [0ACh 0172  12]           PM1A Control Block : [Generic Address Structure]
 [0ACh 0172   1]                     Space ID : 01 [SystemIO]
 [0ADh 0173   1]                    Bit Width : 10
 [0AEh 0174   1]                   Bit Offset : 00
-[0AFh 0175   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0AFh 0175   1]         Encoded Access Width : 02 [Word Access:16]
 [0B0h 0176   8]                      Address : 0000000000001004

 [0B8h 0184  12]           PM1B Control Block : [Generic Address Structure]
 [0B8h 0184   1]                     Space ID : 01 [SystemIO]
 [0B9h 0185   1]                    Bit Width : 00
 [0BAh 0186   1]                   Bit Offset : 00
 [0BBh 0187   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0BCh 0188   8]                      Address : 0000000000000000

 [0C4h 0196  12]            PM2 Control Block : [Generic Address Structure]
 [0C4h 0196   1]                     Space ID : 01 [SystemIO]
 [0C5h 0197   1]                    Bit Width : 08
 [0C6h 0198   1]                   Bit Offset : 00
-[0C7h 0199   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0C7h 0199   1]         Encoded Access Width : 01 [Byte Access:8]
 [0C8h 0200   8]                      Address : 0000000000001050

 [0D0h 0208  12]               PM Timer Block : [Generic Address Structure]
 [0D0h 0208   1]                     Space ID : 01 [SystemIO]
 [0D1h 0209   1]                    Bit Width : 20
 [0D2h 0210   1]                   Bit Offset : 00
-[0D3h 0211   1]         Encoded Access Width : 00 [Undefined/Legacy]
+[0D3h 0211   1]         Encoded Access Width : 03 [DWord Access:32]
 [0D4h 0212   8]                      Address : 0000000000001008

 [0DCh 0220  12]                   GPE0 Block : [Generic Address Structure]
-[0DCh 0220   1]                     Space ID : 00 [SystemMemory]
+[0DCh 0220   1]                     Space ID : 01 [SystemIO]
 [0DDh 0221   1]                    Bit Width : 00
 [0DEh 0222   1]                   Bit Offset : 00
 [0DFh 0223   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0E0h 0224   8]                      Address : 0000000000000000

 [0E8h 0232  12]                   GPE1 Block : [Generic Address Structure]
 [0E8h 0232   1]                     Space ID : 01 [SystemIO]
 [0E9h 0233   1]                    Bit Width : 00
 [0EAh 0234   1]                   Bit Offset : 00
 [0EBh 0235   1]         Encoded Access Width : 00 [Undefined/Legacy]
 [0ECh 0236   8]                      Address : 0000000000000000

Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29387
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
6 files changed
tree: 5c39e21e5afdce052ff65e96497fa40c0ceb1e5e
  1. .checkpatch.conf
  2. .clang-format
  3. .gitignore
  4. .gitmodules
  5. .gitreview
  6. 3rdparty/
  7. COPYING
  8. Documentation/
  9. MAINTAINERS
  10. Makefile
  11. Makefile.inc
  12. README.md
  13. configs/
  14. gnat.adc
  15. payloads/
  16. src/
  17. toolchain.inc
  18. util/
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.