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Angel Pons6e5aabd2020-03-23 23:44:42 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer00636b02012-04-04 00:08:51 +02002
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07003config NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02004 bool
Arthur Heymans7539b8c2017-12-24 10:42:57 +01005 select CACHE_MRC_SETTINGS
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02006 select CPU_INTEL_MODEL_206AX
7 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Elyes Haouas9ee9cd32022-10-30 10:20:33 +01009 select USE_DDR3
10
Elyes Haouasd2ebc4d2023-01-02 15:28:41 +010011if NORTHBRIDGE_INTEL_SANDYBRIDGE
12
Arthur Heymans691d58f2021-08-11 13:42:40 +020013config CHIPSET_DEVICETREE
14 default "northbridge/intel/sandybridge/chipset.cb"
15
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010016config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
17 bool
18 default n
19 help
20 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
21
22config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
23 depends on VBOOT
24 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
25 bool "Start verstage in bootblock"
26 default y
27 select VBOOT_STARTS_IN_BOOTBLOCK
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010028 help
29 Sandy Bridge can either start verstage in a separate stage
30 right after the bootblock has run or it can start it
31 after romstage for compatibility reasons.
32 Sandy Bridge however uses a mrc.bin to initialize memory which
33 needs to be located at a fixed offset. Therefore even with
34 a separate verstage starting after the bootblock that same
35 binary is used meaning a jump is made from RW to the RO region
36 and back to the RW region after the binary is done.
37
Julius Werner1210b412017-03-27 19:26:32 -070038config VBOOT
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010039 select VBOOT_MUST_REQUEST_DISPLAY
40 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070041
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010042config USE_NATIVE_RAMINIT
43 bool "Use native raminit"
44 default y
45 help
46 Select if you want to use coreboot implementation of raminit rather than
47 System Agent/MRC.bin. You should answer Y.
Stefan Reinauer00636b02012-04-04 00:08:51 +020048
Patrick Rudolphb794a692017-08-08 13:13:51 +020049config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
50 bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
51 default n
52 depends on USE_NATIVE_RAMINIT
53 help
54 Ignore the mainboard's vendor programmed fuses that might limit the
55 maximum DRAM frequency. By selecting this option the fuses will be
56 ignored and the only limits on DRAM frequency are set by RAM's SPD and
57 hard fuses in southbridge's clockgen.
58 Disabled by default as it might causes system instability.
59 Handle with care!
60
Vagiz Trakhanov771be482017-10-02 10:02:35 +000061config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
62 bool "Ignore XMP profile max DIMMs per channel"
63 default n
64 depends on USE_NATIVE_RAMINIT
65 help
66 Ignore the max DIMMs per channel restriciton defined in XMP profiles.
67 Disabled by default as it might cause system instability.
68 Handle with care!
69
Angel Pons3170e9c2020-12-12 16:22:18 +010070config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
71 bool "Ignore XMP profile requested voltage"
72 default n
73 depends on USE_NATIVE_RAMINIT
74 help
75 Native raminit only supports 1.5V operation, but there are DIMMs
76 which request 1.65V operation in XMP profiles. This option allows
77 raminit to use these XMP profiles anyway, instead of falling back
78 to non-XMP settings.
79 Disabled by default because it allows forcing memory to run out of
80 specification. Consider this to be an overclocking option.
81 Handle with care!
82
Martin Roth59ff3402016-02-09 09:06:46 -070083config CBFS_SIZE
Martin Roth59ff3402016-02-09 09:06:46 -070084 default 0x100000
85
Stefan Reinauer00636b02012-04-04 00:08:51 +020086config VGA_BIOS_ID
87 string
88 default "8086,0106"
89
Shelley Chen4e9bb332021-10-20 15:43:45 -070090config ECAM_MMCONF_BASE_ADDRESS
Nico Huber2b5c0212017-07-29 01:10:49 +020091 default 0xf0000000
92 help
Arthur Heymans742a0e92018-01-29 16:34:46 +010093 The MRC blob requires it to be at 0xf0000000.
Nico Huber2b5c0212017-07-29 01:10:49 +020094
Shelley Chen4e9bb332021-10-20 15:43:45 -070095config ECAM_MMCONF_BUS_NUMBER
Angel Pons10f9b832021-01-20 14:58:32 +010096 int
97 default 64
98
Stefan Reinauer00636b02012-04-04 00:08:51 +020099config DCACHE_RAM_BASE
100 hex
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300101 default 0xfefe0000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200102
Arthur Heymans67d59d12019-11-16 20:06:20 +0100103config DCACHE_BSP_STACK_SIZE
104 hex
Arthur Heymans8d821092019-11-25 06:56:04 +0100105 default 0x10000
106 help
107 The amount of BSP stack anticipated in bootblock and
108 other stages.
Arthur Heymans01c83a22019-06-05 13:36:55 +0200109
110if USE_NATIVE_RAMINIT
111
Stefan Reinauer00636b02012-04-04 00:08:51 +0200112config DCACHE_RAM_SIZE
113 hex
114 default 0x20000
115
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300116config DCACHE_RAM_MRC_VAR_SIZE
117 hex
118 default 0x0
119
Angel Pons09fc4b92020-11-19 12:02:07 +0100120config RAMINIT_ALWAYS_ALLOW_DLL_OFF
121 bool "Also enable memory DLL-off mode on desktops and servers"
122 default n
123 help
124 If enabled, allow enabling DLL-off mode for platforms other than
125 mobile. Saves power at the expense of higher exit latencies. Has
126 no effect on mobile platforms, where DLL-off is always allowed.
127 Power down is disabled for stability when running at high clocks.
128
Patrick Rudolphdd662872017-10-28 18:20:11 +0200129config RAMINIT_ENABLE_ECC
130 bool "Enable ECC if supported"
131 default y
132 help
133 Enable ECC if supported by both, host and RAM.
134
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300135endif # USE_NATIVE_RAMINIT
136
137if !USE_NATIVE_RAMINIT
138
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300139config DCACHE_RAM_SIZE
140 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200141 default 0x17000
Kyösti Mälkkifbdb0852013-07-01 11:21:53 +0300142
Stefan Reinauer00636b02012-04-04 00:08:51 +0200143config DCACHE_RAM_MRC_VAR_SIZE
144 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200145 default 0x9000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200146
Stefan Reinauer00636b02012-04-04 00:08:51 +0200147config MRC_FILE
148 string "Intel System Agent path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200149 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
Stefan Reinauer00636b02012-04-04 00:08:51 +0200150 help
151 The path and filename of the file to use as System Agent
152 binary.
153
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300154endif # !USE_NATIVE_RAMINIT
Kyösti Mälkki0306e6a2016-06-23 12:41:40 +0300155
Nico Huber612a8672019-02-19 19:11:29 +0100156config INTEL_GMA_BCLV_OFFSET
157 default 0x48254
158
Angel Ponsd9e58dc2021-01-20 01:22:20 +0100159config FIXED_MCHBAR_MMIO_BASE
160 default 0xfed10000
161
162config FIXED_DMIBAR_MMIO_BASE
163 default 0xfed18000
164
165config FIXED_EPBAR_MMIO_BASE
166 default 0xfed19000
167
Stefan Reinauer00636b02012-04-04 00:08:51 +0200168endif