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Angel Pons6e5aabd2020-03-23 23:44:42 +01001## SPDX-License-Identifier: GPL-2.0-only
Stefan Reinauer00636b02012-04-04 00:08:51 +02002
Alexandru Gagniucecf2eb42015-09-28 21:39:12 -07003config NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02004 bool
Arthur Heymans7539b8c2017-12-24 10:42:57 +01005 select CACHE_MRC_SETTINGS
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02006 select CPU_INTEL_MODEL_206AX
7 select HAVE_DEBUG_RAM_SETUP
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +01008 select INTEL_GMA_ACPI
Vladimir Serbinenko309fc4c2014-08-24 22:35:29 +02009
Nico Huber772a1542019-05-10 16:48:14 +020010if NORTHBRIDGE_INTEL_SANDYBRIDGE
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010011
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010012config SANDYBRIDGE_VBOOT_IN_ROMSTAGE
13 bool
14 default n
15 help
16 Selected by boards to force VBOOT_STARTS_IN_ROMSTAGE.
17
18config SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
19 depends on VBOOT
20 depends on !SANDYBRIDGE_VBOOT_IN_ROMSTAGE
21 bool "Start verstage in bootblock"
22 default y
23 select VBOOT_STARTS_IN_BOOTBLOCK
24 select VBOOT_SEPARATE_VERSTAGE
25 help
26 Sandy Bridge can either start verstage in a separate stage
27 right after the bootblock has run or it can start it
28 after romstage for compatibility reasons.
29 Sandy Bridge however uses a mrc.bin to initialize memory which
30 needs to be located at a fixed offset. Therefore even with
31 a separate verstage starting after the bootblock that same
32 binary is used meaning a jump is made from RW to the RO region
33 and back to the RW region after the binary is done.
34
Julius Werner1210b412017-03-27 19:26:32 -070035config VBOOT
Patrick Rudolph1ee3dbc2020-02-28 13:11:13 +010036 select VBOOT_MUST_REQUEST_DISPLAY
37 select VBOOT_STARTS_IN_ROMSTAGE if !SANDYBRIDGE_VBOOT_IN_BOOTBLOCK
Julius Werner1210b412017-03-27 19:26:32 -070038
Vladimir Serbinenko144eea02016-02-10 02:36:04 +010039config USE_NATIVE_RAMINIT
40 bool "Use native raminit"
41 default y
42 help
43 Select if you want to use coreboot implementation of raminit rather than
44 System Agent/MRC.bin. You should answer Y.
Stefan Reinauer00636b02012-04-04 00:08:51 +020045
Patrick Rudolphb794a692017-08-08 13:13:51 +020046config NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES
47 bool "Ignore vendor programmed fuses that limit max. DRAM frequency"
48 default n
49 depends on USE_NATIVE_RAMINIT
50 help
51 Ignore the mainboard's vendor programmed fuses that might limit the
52 maximum DRAM frequency. By selecting this option the fuses will be
53 ignored and the only limits on DRAM frequency are set by RAM's SPD and
54 hard fuses in southbridge's clockgen.
55 Disabled by default as it might causes system instability.
56 Handle with care!
57
Vagiz Trakhanov771be482017-10-02 10:02:35 +000058config NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS
59 bool "Ignore XMP profile max DIMMs per channel"
60 default n
61 depends on USE_NATIVE_RAMINIT
62 help
63 Ignore the max DIMMs per channel restriciton defined in XMP profiles.
64 Disabled by default as it might cause system instability.
65 Handle with care!
66
Angel Pons3170e9c2020-12-12 16:22:18 +010067config NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE
68 bool "Ignore XMP profile requested voltage"
69 default n
70 depends on USE_NATIVE_RAMINIT
71 help
72 Native raminit only supports 1.5V operation, but there are DIMMs
73 which request 1.65V operation in XMP profiles. This option allows
74 raminit to use these XMP profiles anyway, instead of falling back
75 to non-XMP settings.
76 Disabled by default because it allows forcing memory to run out of
77 specification. Consider this to be an overclocking option.
78 Handle with care!
79
Martin Roth59ff3402016-02-09 09:06:46 -070080config CBFS_SIZE
81 hex
82 default 0x100000
83
Stefan Reinauer00636b02012-04-04 00:08:51 +020084config VGA_BIOS_ID
85 string
86 default "8086,0106"
87
Nico Huber2b5c0212017-07-29 01:10:49 +020088config MMCONF_BASE_ADDRESS
Nico Huber2b5c0212017-07-29 01:10:49 +020089 default 0xf0000000
90 help
Arthur Heymans742a0e92018-01-29 16:34:46 +010091 The MRC blob requires it to be at 0xf0000000.
Nico Huber2b5c0212017-07-29 01:10:49 +020092
Angel Pons10f9b832021-01-20 14:58:32 +010093config MMCONF_BUS_NUMBER
94 int
95 default 64
96
Stefan Reinauer00636b02012-04-04 00:08:51 +020097config DCACHE_RAM_BASE
98 hex
Kyösti Mälkki9551bed2016-07-20 10:49:38 +030099 default 0xfefe0000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200100
Arthur Heymans67d59d12019-11-16 20:06:20 +0100101config DCACHE_BSP_STACK_SIZE
102 hex
Arthur Heymans8d821092019-11-25 06:56:04 +0100103 default 0x10000
104 help
105 The amount of BSP stack anticipated in bootblock and
106 other stages.
Arthur Heymans01c83a22019-06-05 13:36:55 +0200107
108if USE_NATIVE_RAMINIT
109
Stefan Reinauer00636b02012-04-04 00:08:51 +0200110config DCACHE_RAM_SIZE
111 hex
112 default 0x20000
113
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300114config DCACHE_RAM_MRC_VAR_SIZE
115 hex
116 default 0x0
117
Angel Pons09fc4b92020-11-19 12:02:07 +0100118config RAMINIT_ALWAYS_ALLOW_DLL_OFF
119 bool "Also enable memory DLL-off mode on desktops and servers"
120 default n
121 help
122 If enabled, allow enabling DLL-off mode for platforms other than
123 mobile. Saves power at the expense of higher exit latencies. Has
124 no effect on mobile platforms, where DLL-off is always allowed.
125 Power down is disabled for stability when running at high clocks.
126
Patrick Rudolphdd662872017-10-28 18:20:11 +0200127config RAMINIT_ENABLE_ECC
128 bool "Enable ECC if supported"
129 default y
130 help
131 Enable ECC if supported by both, host and RAM.
132
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300133endif # USE_NATIVE_RAMINIT
134
135if !USE_NATIVE_RAMINIT
136
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300137config DCACHE_RAM_SIZE
138 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200139 default 0x17000
Kyösti Mälkkifbdb0852013-07-01 11:21:53 +0300140
Stefan Reinauer00636b02012-04-04 00:08:51 +0200141config DCACHE_RAM_MRC_VAR_SIZE
142 hex
Arthur Heymans01c83a22019-06-05 13:36:55 +0200143 default 0x9000
Stefan Reinauer00636b02012-04-04 00:08:51 +0200144
Stefan Reinauer00636b02012-04-04 00:08:51 +0200145config MRC_FILE
146 string "Intel System Agent path and filename"
Patrick Georgi26e24cc2015-05-05 22:27:25 +0200147 default "3rdparty/blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
Stefan Reinauer00636b02012-04-04 00:08:51 +0200148 help
149 The path and filename of the file to use as System Agent
150 binary.
151
Kyösti Mälkki9551bed2016-07-20 10:49:38 +0300152endif # !USE_NATIVE_RAMINIT
Kyösti Mälkki0306e6a2016-06-23 12:41:40 +0300153
Nico Huber612a8672019-02-19 19:11:29 +0100154config INTEL_GMA_BCLV_OFFSET
155 default 0x48254
156
Angel Ponsd9e58dc2021-01-20 01:22:20 +0100157config FIXED_MCHBAR_MMIO_BASE
158 default 0xfed10000
159
160config FIXED_DMIBAR_MMIO_BASE
161 default 0xfed18000
162
163config FIXED_EPBAR_MMIO_BASE
164 default 0xfed19000
165
Stefan Reinauer00636b02012-04-04 00:08:51 +0200166endif